JP2015122644A - Spread spectrum clock generation circuit and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a waveform from being disturbed by a clock load variation or the like in selective switching of a multiphase clock.SOLUTION: In a spread spectrum clock generation circuit, a control voltage corresponding to a phase difference between an input clock signal and a phase shift clock signal is outputted, an output clock signal having a frequency corresponding to a control voltage is generated, one of phases obtained by equally dividing one cycle of the output clock signal is selected, and a phase shift clock signal having a rising edge in the selected phase is generated. In the spread spectrum clock generation circuit, a phase controller determines and selects a phase of an edge of the phase shift clock signal that is selected in such a manner that the cycle becomes a length changed from the cycle of the output clock signal by a predetermined first phase shift amount, a second phase shift amount that is cyclically changed is generated and added to the first phase shift amount, the phase of the edge of the selected phase shift clock signal is determined, spread spectrum modulation is performed on the output clock signal by the second phase shift amount, and phase data selected just after updating a phase data update signal are changed.

Description

  The present invention relates to a spread spectrum clock generation (SSCG) circuit and an electronic apparatus using the same.

  In the technical field of clock generation circuits, in order to prevent the generation of EMI (radiated electromagnetic noise) having a peak at a specific frequency, the frequency of the clock signal was slightly spread spectrum modulated to have a peak at a specific frequency. There is known a spread spectrum clock generation circuit that disperses EMI energy to reduce a peak value. For example, the inventions of Patent Documents 1 and 2 are known as spread spectrum clock generation circuits.

  The spread spectrum clock generation circuit according to Patent Document 1 includes a phase frequency comparator, a charge pump, a loop filter, a voltage controlled oscillator, a phase controller, and a phase selection circuit. The phase selection circuit selects one of the phases obtained by equally dividing one period of the output clock signal vco_cko from the voltage controlled oscillator, and generates a phase-shifted clock signal pi_out having a rising edge in the selected phase. As a feedback signal to the phase frequency comparator. The phase controller changes the cycle of the phase shift clock signal pi_out by a first phase shift amount determined in advance from the cycle of the output clock signal vco_cko, and sets a second phase shift amount that periodically changes within a predetermined range. The phase interpolation circuit 6 is controlled to be added to the first phase shift amount.

  In the spread spectrum clock generation circuit according to Patent Document 2, the DLL circuit delays the oscillation clock signal CLKO from the VCO 7 and outputs delayed clock signals CLKD1 to CLKD10 having different phases. The selector 9 selects any one of the delayed clock signals CLKD1 to CLKD10 and outputs a selected clock signal CLKS. The control circuit 3 controls the signal selection operation of the selector 9. The feedback frequency divider circuit 10 divides the selected clock signal CLKS by a frequency division ratio N to generate a comparison clock signal CLKC. Thereby, the phase of the comparison clock signal CLKC can be finely adjusted. Therefore, a spread spectrum clock generation circuit capable of highly accurate frequency modulation can be realized.

  In the spread spectrum clock generation circuit according to Patent Document 2, any one of the delayed clocks having different phases is selected and input to the phase comparator, and the SSCG circuit is adjusted by finely adjusting the phase of the comparison clock. Realized. However, there has been a problem that when the multi-phase clock is switched, the waveform is disturbed due to fluctuations in the load of the clock, etc., and there is a risk that the clock may be lost, particularly during high-speed operation.

  An object of the present invention is to solve the above problems and provide a spread spectrum clock generation circuit capable of preventing the occurrence of waveform disturbance due to fluctuations in clock load at the time of selecting and switching multiphase clocks, and an electronic device using the same There is to do.

A spread spectrum clock generation circuit according to the present invention includes:
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage corresponding to the phase difference;
Voltage-controlled oscillation means for generating and outputting an output clock signal having a frequency corresponding to the control voltage;
One of the phases obtained by equally dividing one cycle of the output clock signal into a predetermined number is selected, a phase shift clock signal having a rising edge in the selected phase is generated, and the phase shift clock signal is used as the feedback signal. Phase interpolation means for sending to the phase comparison means;
The phase shift clock signal selected by the phase interpolating means is set so that the period of the phase shift clock signal is changed from the period of the output clock signal by a predetermined first phase shift amount. A phase control means for determining the phase of the rising edge and controlling the phase interpolation means so as to select the determined phase;
The phase control means generates a second phase shift amount that periodically changes within a predetermined range, and adds the second phase shift amount to the first phase shift amount. A spread-spectrum clock generation circuit that determines a phase of a rising edge of the phase-shifted clock signal selected by the means and spread-spectrum modulates the output clock signal by the second phase shift amount that periodically changes;
The phase control means controls to change the selected phase data immediately after the phase data update signal indicating the phase update is updated.

  According to the present invention, it is possible to prevent the occurrence of waveform disturbance due to fluctuations in the clock load at the time of selective switching of the multiphase clock, thereby preventing the occurrence of jitter and the loss of the clock particularly during high-speed operation.

1 is a block diagram showing a configuration of a spread spectrum clock generation circuit according to an embodiment of the present invention. FIG. It is a figure for demonstrating the phase of the output clock signal vco_cko selected by the phase selection circuit 21 of the phase interpolation circuit 6 of FIG. It is a figure for demonstrating the phase of the output clock signal vco_cko selected by the phase selection circuit 21 of FIG. FIG. 3 is a timing chart showing the phase shift by the phase selection circuit 21 of FIG. 1 when the phase shift amount Δph is positive. FIG. 5 is a graph showing a phase selected by a phase selection circuit 21 when performing the phase shift of FIG. 4. 6 is a timing chart showing phase data update in a spread spectrum clock generation circuit according to a comparative example. 3 is a timing chart showing phase data update in the spread spectrum clock generation circuit of FIG. FIG. 2 is a block diagram illustrating configurations of a voltage controlled oscillator 4 and a differential buffer circuit 20 in FIG. 1. It is a block diagram which shows the structure of the phase interpolation circuit 6 of FIG. It is a circuit diagram which shows the structure of the phase interpolation part 22 of FIG.9 and FIG.12. 11 is a timing chart showing the operation of the phase interpolation circuit 6 including the phase interpolation unit 22 of FIG. 10. It is a block diagram which shows the structure of 6 A of phase interpolation circuits and the voltage control oscillator 4 which concern on a modification.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment.
FIG. 1 is a block diagram showing a configuration of a spread spectrum clock generation circuit according to an embodiment of the present invention. In FIG. 1, the spread spectrum clock generation circuit is configured as a PLL circuit. The reference clock signal ref_ck generated by the reference clock generator 10 is divided by the input frequency divider 11, and the divided input clock signal comp_ck is input to the phase frequency comparator 1. The phase frequency comparator 1 detects a phase difference between the input clock signal comp_ck and the clock signal pi_out that is a feedback signal from the phase interpolation circuit 6 and outputs the phase difference to the charge pump 2. The charge pump 2 outputs the charge pump voltage increased or decreased according to the phase difference to the loop filter 3, and the loop filter 3 outputs the control voltage corresponding to the charge pump voltage to the voltage controlled oscillator (VCO) 4. The voltage controlled oscillator 4 generates and outputs an output clock signal vco_cko and a multiphase clock signal vco_ck (n) having a frequency and a phase corresponding to the control voltage. Here, for example, n = 0, 2, 3,. The output frequency divider 12 divides the output clock signal vco_cko for use by other circuits and outputs it as, for example, a pixel clock signal pix_ck for the image forming apparatus. The feedback circuit from the voltage controlled oscillator 4 to the phase frequency comparator 1 is provided with a phase interpolation circuit 6 that operates under the control of the phase controller 5.

  The phase controller 5 generates a phase data update signal pien based on the output clock signal vco_cko and the frequency division number setting value div_puck from the device controller 50 that controls the entire circuit device, and outputs the phase data update signal pien to the phase interpolation circuit 6. The phase controller 5 outputs phase data signals ph_sel (n) and pi_sel (m) to the phase interpolation circuit 6 for generating a modulation waveform. The phase interpolation circuit 6 selects a phase obtained by equally dividing one cycle of the output clock signal vco_cko based on the phase data signals ph_sel and pi_sel. Next, the phase interpolation circuit 6 generates the spread spectrum clock by outputting the clock signal pi_out during the effective (H) period of the output timing signal pieno generated based on the phase data update signal pien and outputting it to the phase frequency comparator 1 The operation of the circuit is realized. That is, the phase interpolation circuit 6 selects and outputs a phase predetermined by the phase controller 5 from a phase obtained by equally dividing one cycle of the output clock signal vco_cko, and sequentially performs spread spectrum modulation by changing the selected phase. Realize.

  The phase interpolation circuit 6 generates and outputs a phase-shifted clock signal pi_out having a cycle changed from the cycle of the output clock signal vco_cko by changing the phase of the rising edge of the output clock signal vco_cko. Specifically, the phase interpolation circuit 6 selects one of the phases obtained by equally dividing one period of the clock of the output clock signal vco_cko into a predetermined number, and outputs the phase-shifted clock signal pi_out having a rising edge in the selected phase. Generate and output. The phase controller 5 performs the following so that the period of the phase shift clock signal pi_out is changed from the period of the output clock signal vco_cko by a predetermined phase shift amount Δph (an integer multiple of the equally divided phase). Control like this. The phase controller 5 controls the phase interpolation circuit 6 by determining the phase of the rising edge of the phase shift clock signal pi_out selected by the phase interpolation circuit 6. Then, the phase shift clock signal pi_out is input to the phase frequency comparator 1 as a feedback signal.

  The PLL circuit included in the spread spectrum clock generation circuit of the present embodiment performs negative feedback control so that the frequency and phase of the phase shift clock signal pi_out coincide with the frequency and phase of the input clock signal comp_ck. Furthermore, the PLL circuit of the present embodiment generates the phase shift clock signal pi_out having a cycle changed from the cycle of the output clock signal vco_cko by the phase interpolation circuit 6. When the phase shift amount Δph is positive, the frequency of the phase shift clock signal pi_out is higher than the frequency of the input clock signal comp_ck. When the phase shift amount Δph is negative, the frequency of the phase shift clock signal pi_out is the input clock signal. It becomes lower than the frequency of comp_ck. Furthermore, in the present embodiment, the frequency of the output clock signal vco_cko can be spread spectrum modulated by changing the period of the phase-shifted clock signal pi_out by the phase interpolation circuit 6.

  The phase interpolation circuit 6 can further divide the output clock signal vco_cko when generating the phase shift clock signal pi_out having a period changed from the period of the output clock signal vco_cko. In the present embodiment, the set value of the division ratio of the phase interpolation circuit 6 is represented by div_puck = 0, 1, 2,..., And when div_puck = n, the division ratio is n + 1. When the output divider 12 has a division ratio of 2 or more, the phase interpolation circuit 6 further divides the output clock signal vco_cko in consideration of this division ratio. In this embodiment, the set value of the frequency division ratio of the output frequency divider 12 is represented by div_pll = 0, 1, 2,..., And when div_pll = n, the frequency division ratio is assumed to be n + 1. Therefore, the division ratio of the phase shift clock signal pi_out to the output clock signal vco_cko is the division ratio of the phase interpolation circuit 6, and the output divider 12 divides the output clock signal vco_cko into the pixel clock signal pix_ck.

  2 and 3 are diagrams for explaining the phase of the output clock signal vco_cko selected by the phase interpolation circuit 6. In the present embodiment, the phase interpolation circuit 6 selects one of the phases (indicated as “0” to “511” in FIGS. 2 and 3) obtained by equally dividing one cycle of the clock of the output clock signal vco_cko into 512 pieces. It will be explained as a thing. The phase interpolation circuit 6 functions as a phase insertion device that inserts a rising edge into an arbitrary phase.

  First, the operation of the spread spectrum clock generation circuit as a PLL circuit will be described in detail with reference to FIGS. For simplification of explanation, it is assumed that the frequency division ratios of the phase interpolation circuit 6 and the output frequency divider 12 are 1, that is, div_puck = 0.

  FIG. 4 is a timing chart showing the phase shift by the phase interpolation circuit 6 of FIG. 1 when the phase shift amount Δph is positive. The horizontal axis in FIG. 4 has a unit obtained by equally dividing one cycle of the clock of the output clock signal vco_cko into 512 units (the phase is also expressed in the same unit in FIG. 5). In the case of FIG. 4, the cycle of the phase shift clock signal pi_out is increased by the phase shift amount Δph from the cycle of the output clock signal vco_cko (that is, 512 + Δph). Accordingly, the rising edge of each clock of the phase-shifted clock signal pi_out is delayed by an amount of phase shift Δph from the rising edge of each corresponding clock of the output clock signal vco_cko every time the clock advances. Assume that the rising edges of the first clock vco_ck (0) of the output clock signal and the first clock pi_out (0) of the phase-shifted clock signal match. The rising edge of the second clock pi_out (1) of the phase-shifted clock signal is delayed by the phase shift amount Δph from the rising edge of the second clock vco_ck (1) of the output clock signal. The rising edge of the third clock pi_out (2) of the phase shift clock signal is delayed by twice the phase shift amount Δph from the rising edge of the third clock vco_ck (2) of the output clock signal. Similarly, the rising edge of the nth clock pi_out (n−1) of the phase shift clock signal is n−1 times the phase shift amount Δph from the rising edge of the nth clock vco_ck (n−1) of the output clock signal. Delayed.

  FIG. 5 is a graph showing the phase selected by the phase interpolation circuit 6 when the phase shift of FIG. 4 is performed. The phase interpolation circuit 6 selects any one of phases “0” to “511” obtained by equally dividing one cycle of the clock of the output clock signal vco_cko into 512 as the current phase. As shown in FIG. 5, every time the clock of the output clock signal vco_cko advances, the phase interpolation circuit 6 selects a phase incremented by the phase shift amount Δph as a new current phase. When the sum of the current phase and the phase shift amount Δph is less than one cycle of the clock of the output clock signal vco_cko even if incremented by the phase shift amount Δph, the rising edge of the clock next to the phase shift clock signal pi_out is the output clock signal. It is in the corresponding phase within the period of the clock next to vco_cko. Here, the case where the sum of the current phase and the phase shift amount Δph is less than one cycle of the clock of the output clock signal vco_cko is when the phase after the increment is “511” or less. On the other hand, when the phase shift amount Δph is incremented, when the sum of the current phase and the phase shift amount Δph is one cycle or more of the clock of the output clock signal vco_cko, the rising edge of the clock next to the phase shift clock signal pi_out is the output clock signal. It is not the clock next to vco_cko. The rising edge is in a phase obtained by subtracting “512” from the phase after the increment in the next clock cycle. Here, when the sum of the current phase and the phase shift amount Δph is equal to or longer than one cycle of the clock of the output clock signal vco_cko, the phase after the increment is “512” or more. In the latter case, for example, as illustrated in FIG. 4, the rising edge of the fifth clock pi_out (4) of the phase-shifted clock signal is not the fifth clock vco_ck (4) of the output clock signal. The rising edge is within the cycle of the sixth clock vco_ck (5). From the rising edge of the sixth clock vco_ck (5) of the output clock signal, mod (4 × Δph, 512), that is, 4 × Δph is 512. Delayed by the remainder when divided. This is indicated by a white arrow in FIG. 5, and instead of selecting the phase indicated by the dotted circle in the clocks vco_ck (4), vco_ck (8), and vco_ck (12) of the output clock signal, The solid white circle on the clock is selected.

  By selecting the phase as described with reference to FIGS. 4 and 5, the period of each clock pi_out (0), pi_out (1),..., Pi_out (n) of the phase-shifted clock signal is always the output clock signal. The length is increased by the phase shift amount Δph from the clock period of vco_cko. Here, the length is 512 + Δph.

  FIG. 6 is a timing chart showing phase data update in a spread spectrum clock generation circuit according to a comparative example (for example, Patent Document 1). 6 and 7, pieno is an output timing signal that rises at the falling edge of the phase update signal pien, and PICLK is a phase-interpolated clock signal (hereinafter referred to as a phase-interpolated clock signal) from the phase interpolator 22 in FIG. .) In the comparative example, the phase update signal pi and the phase data signals ph_sel and pi_sel are received from the phase controller 5 and the phase-shifted clock signal pi_out to be output to the phase comparator is selected from the multiphase clock signal vco_ck (n). Then, a clock is output during the valid (H) period of the output timing signal pieno. In the phase shift type spread spectrum clock generation circuit, when the phase data is switched, the waveform of the multiphase clock signal vco_ck (n) generated by the voltage controlled oscillator 4 is disturbed, and it takes time until the waveform becomes stable. When the voltage controlled oscillator 4 operates at high speed, this unstable period reaches several clocks, and therefore the phase shift clock signal pi_out output from the phase interpolation circuit 6 disappears (101). There was a problem that speeding up was difficult.

  FIG. 7 is a timing chart showing phase data update in the spread spectrum clock generation circuit of FIG. In the present embodiment, the next phase data signals ph_sel and pi_sel are changed immediately after the update of the phase update signal pien output from the phase controller 5. Alternatively, control is performed such that the next phase data signals ph_sel and pi_sel are changed by delaying by a fixed clock of the output clock signal vco_ck from the fall of the phase update signal pien. This ensures the longest period during which the waveform of the multiphase clock signal vco_ck (n) is stable, regardless of the multiplication factor of the spread spectrum clock generation circuit, and enables the circuit to operate at high speed.

  FIG. 8 is a block diagram showing the configuration of the voltage controlled oscillator 4 and the differential buffer circuit 20 of FIG. In FIG. 8, only the ring oscillator R1, which is a part of the block of the voltage controlled oscillator 4, is illustrated as the circuit of the voltage controlled oscillator 4. In an actual circuit, the voltage-controlled oscillator 4 includes a ring oscillator R1 having a voltage-current converter in the input stage and a delay circuit controlled by current in a ring shape in the subsequent stage. Here, the differential buffer circuit 20 is inserted between the voltage-controlled oscillator 4 and the phase selection circuit 21 of the phase interpolation circuit 6, and specifically, is provided in front of the phase selection circuit 21 of the phase interpolation circuit 6. . In FIG. 8, the voltage controlled oscillator 4 includes a ring oscillator R1 and a differential buffer B16. In the ring oscillator R1, for example, a plurality of 16 differential buffers B0 to B15 are cascade-connected, and the differential output signal of the last-stage differential buffer B15 is fed back to the differential input terminal of the first-stage differential buffer B0. Configured as follows. The differential output signal of the last-stage differential buffer B15 is output as the output clock signal vco_ck via the differential buffer B16. The differential buffer circuit 20 includes, for example, 16 differential buffers BA0 to BA15. The differential output signals from the differential output terminals of the differential buffers B0 to B15 are transferred to the differential multiphase clock signals (vco_ck0n, vco_ck0p) via the differential buffers BA0 to BA15 of the differential buffer circuit 20, respectively. To (vco_ck15n, vco_ck15p). These differential multi-phase clock signals (vco_ck0n, vco_ck0p) to (vco_ck15n, vco_ck15p) are output to the phase selection circuit 21 of the phase interpolation circuit 6 in FIG. Note that each differential buffer used in the present embodiment differentially buffers and amplifies an input signal and outputs it.

  FIG. 9 is a block diagram showing the configuration of the phase interpolation circuit 6 of FIG. The phase interpolation circuit 6 includes a phase selection circuit 21, a phase interpolation unit 22, and an output clock generation unit 23. The phase selection circuit 21 includes a phase selection circuit unit 21a for the previous phase and a phase selection circuit unit 21b for the subsequent phase.

  The phase selection circuit unit 21a includes, for example, 15 phase selection units PS0 to PS15 and a differential buffer BB1. Each of the phase selectors PS0 to PS15 includes three constant current sources Iaxn, Iaxp, and Ibx, a differential pair Dax (differential input stage circuit) including two MOS transistors Qaxn and Qaxp, and a switch SWm. (X = 1, 2, 3,..., 15). The switch SWm is a switch element made of, for example, a MOS transistor. The voltage source of the power supply voltage VDD is grounded via a constant current source Iaxn, a MOS transistor Qaxn, a constant current source Ibx, and a switch SWx, and via a constant current source Iaxp, a MOS transistor Qaxp, a constant current source Ibx, and a switch SWx. Grounded. When the switch SWx is turned on based on the high level signal ph_sel (n), the differential signals vco_ckxn and vco_ckxp are differentially amplified by the differential pair Dax including the MOS transistors Qaxn and Qaxp. Next, the differentially amplified differential signals are output to the phase interpolation unit 22 as differential clock signals FP and FN via the differential buffer BB1.

  The phase selection circuit unit 21b includes, for example, 15 phase selection units PT0 to PT15 and a differential buffer BB2. Each of the phase selectors PT0 to PT15 includes three constant current sources Icxn, Icxp, Idx, a differential pair Dcx composed of two MOS transistors Qcxn, Qcxp, and a switch SXx (x = 1). , 2, 3, ..., 15). The switch SXm is a switch element made of, for example, a MOS transistor. The voltage source of the power supply voltage VDD is grounded via a constant current source Icxn, a MOS transistor Qcxn, a constant current source Idx, and a switch SXx, and via a constant current source Icxp, a MOS transistor Qcxp, a constant current source Idx, and a switch SXx. Grounded. When the switch SXx is turned on based on the high level signal ph_sel (n), the differential signals vco_ckxn and vco_ckxp are differentially amplified by the differential pair Dcx including the MOS transistors Qcxn and Qcxp. Next, the differentially amplified differential signal is output to the phase interpolation unit 22 as the differential clock signals SP and SN via the differential buffer BB2.

  In the phase selection circuit 21 configured as described above, the multiphase clock signal output from the differential buffer circuit 20 is received by the differential pair Dax and Dcx composed of two MOS transistors. The constant current sources Ibx and Idx are provided with switches SWx and SXx for selecting two adjacent phases of the multiphase clock. The two differential signals are output to the phase interpolation unit 22 via the differential buffers BB1 and BB2, respectively. The phase interpolation unit 22 performs phase interpolation on two differential signals input based on the phase data signal pi_sel (m), selects a corresponding phase, generates a phase interpolation clock signal PICLK, and outputs an output clock. Output to the generation unit 23. The output clock generator 23 updates the phase of the phase interpolation clock signal input based on the phase update signal pien, and then generates and outputs the phase shift clock signal pi_out.

  In the comparative example, the differential buffer that has received the output clock signal from the ring oscillator R1 outputs the clock signal via the switch. At this time, the clock signal whose phase has been selected has an increased output load when updating the phase data, which may cause rounding and distortion of the waveform. On the other hand, in the present embodiment, by providing the differential buffer circuit 20 and the phase selection circuit 21 having a buffer function, the drive capability can be increased, and the rounding of the waveform of the clock signal can be suppressed, thereby achieving high-speed operation. It becomes possible to respond.

  FIG. 10 is a circuit diagram showing a configuration of the phase interpolation unit 22 of FIG. FIG. 11 is a timing chart showing the operation of the phase interpolation circuit 6 including the phase interpolation unit 22 of FIG.

  The phase interpolation unit 22 includes two constant current sources Ie1 and Ie2, two variable current sources If1 and If2, a differential pair De1 including two MOS transistors Qe11 and Qe12, and two MOS transistors Qe21. , Qe22 and a differential / single converter DSC1. The voltage source of the power supply voltage VDD is grounded through the constant current source Ie1, the MOS transistor Qe11, and the variable current source If1, and is grounded through the constant current source Ie1, the MOS transistor Qe21, and the variable current source If2. The voltage source of the power supply voltage VDD is grounded through the constant current source Ie2, the MOS transistor Qe12, and the variable current source If1, and is grounded through the constant current source Ie2, the MOS transistor Qe22, and the variable current source If2. The variable current source If1 is set to a 16-value current value according to the input 4-bit phase data signal pi_sel [3: 0], and flows a current having the set current value. The variable current source If2 is set to a 16-value current value according to the input 4-bit phase data signal / pi_sel [3: 0] (a signal inverted from the phase data signal pi_sel [3: 0]). A current having a current value is supplied.

  In the phase interpolator 22 described above, the variable current of the differential buffer with respect to the clock signal FP whose phase is the front and the clock signal SP whose phase is the back of the two adjacent phases from the ring oscillator R1 as shown in FIG. Phase interpolation is performed by changing the amount of delay by changing the current values of the sources If1 and If2. In the configuration of FIG. 10, each of the variable current sources If1 and If2 is configured by a 4-bit D / A converter, 16 current values can be set, and phase interpolation is performed in 16 divisions. Here, the clock signal FN is an inverted clock signal of the clock signal FP, and the clock signal SN is an inverted clock signal of the clock signal SP. The phase interpolated clock signals PIP and PIN are subjected to differential / single conversion by the differential / single converter DSC1 to generate and output a single-ended phase interpolated clock signal PICLK.

  According to the present embodiment configured as described above, control is performed so that the next phase data is changed immediately after the phase data update signal pien output from the phase controller 5 is updated. This ensures the longest period during which the waveform of the multiphase clock signal vco_ck (n) is stable regardless of the frequency division number setting value (multiplication rate) of the spread spectrum clock generation circuit, and allows the spread spectrum clock generation circuit to operate at high speed. Is possible.

  A ring oscillator R1 that generates a multiphase clock signal vco_ck (n), a differential buffer circuit 20 that buffers and amplifies a differential multiphase clock signal output therefrom, and a multiphase clock that is output from the differential buffer circuit 20 The signal was received by each differential pair Dax, Dcx of the phase selection circuit 21. Further, switches SWx and SXx for selecting two adjacent phases of the multiphase clock signal are provided in each constant current source Ibx and Idx, and differential buffers BB1 and BB2 output to the subsequent stage, and 2 output therefrom. The phases of two clock signals are interpolated to generate an interpolated clock signal. Thus, unlike the comparative example using the selector, the drive capability is increased by providing the buffer function, so that waveform rounding can be suppressed and high-speed operation can be supported.

Modified example of the embodiment.
FIG. 12 is a block diagram showing the configuration of the phase interpolation circuit 6A and the voltage controlled oscillator 4 according to the modification. The modification of FIG. 12 includes a switch circuit 31 having dummy loads BLxN, BLxP (x = 0, 1, 2,..., 15) and a selector 32 instead of the phase selection circuit 21 of FIG. The phase selection circuit 21A is provided. The differential clock signals output from the differential buffers Bx of the ring oscillator R1 are switches SWxN, SWxP (x = 0, 1, 2,..., 15) that are turned on when selected based on the phase data signal ph_sel (n). Are output to the phase interpolation unit 22 via the selector 32 and the differential buffers BB1 and BB2. Here, when the switches SWxN and SWxP (x = 0, 1, 2,..., 15) are not selected and are turned off, the switches SWxQ and SWxR (x = 0, 1, 2,..., 15) are turned on. Are connected to dummy loads BLxN and BLxP, which are differential buffers, for example. Note that the switches SWxN and SWxP are composed of, for example, MOS transistors.

  As described above, according to the modification of this embodiment, the switches SWxN and SWxP (x = 0, x) for selecting two adjacent phases of the differential multiphase clock signal output from the ring oscillator R1. 1, 2, ..., 15). Then, when not selected, dummy loads BLxN and BLxP are provided in advance so that a load equivalent to that at the time of selection is connected, and the phase of the differential clock signal output from the selector 32 is interpolated by the phase interpolation unit 22, The phase interpolation clock signal subjected to phase interpolation is generated. Therefore, the differential buffer circuit 20 that receives the multiphase clock signal from the ring oscillator R1 as in the comparative example is not necessary, and the circuit scale can be reduced and the current consumption can be reduced. Further, by providing dummy loads BLxN, BLxP (x = 0, 1, 2,..., 15), the fluctuation of the output load when the multiphase clock signal is selected and when the multiphase clock signal is not selected is offset, so that the oscillation frequency can be reduced. Change can be suppressed.

  The spread spectrum clock generation circuit according to the above-described embodiments and modifications thereof can be applied to electronic devices such as an image forming apparatus and a wireless communication circuit.

  In the spread spectrum clock generation circuit according to the above-described embodiment and its modification, the differential signal processing has been described. However, the present invention is not limited to this, and a single-ended signal is used instead of the differential signal. Also good.

Summary of embodiments.
The spread spectrum clock generation circuit according to the first aspect includes:
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage corresponding to the phase difference;
Voltage-controlled oscillation means for generating and outputting an output clock signal having a frequency corresponding to the control voltage;
One of the phases obtained by equally dividing one cycle of the output clock signal into a predetermined number is selected, a phase shift clock signal having a rising edge in the selected phase is generated, and the phase shift clock signal is used as the feedback signal. Phase interpolation means for sending to the phase comparison means;
Phase control means.
The phase control means selects the phase-shifted clock signal selected by the phase interpolating means so that the period of the phase-shifted clock signal is changed to a length changed from the period of the output clock signal by a predetermined first phase shift amount. The phase of the rising edge is determined, and the phase interpolation means is controlled to select the determined phase. The phase control unit generates a second phase shift amount that periodically changes within a predetermined range, and adds the second phase shift amount to the first phase shift amount. The phase control means determines the phase of the rising edge of the phase shift clock signal selected by the phase interpolation means, and performs spread spectrum modulation on the output clock signal with the second phase shift amount that periodically changes. The phase control means controls to change the selected phase data immediately after the phase data update signal indicating the phase update is updated.

The spread spectrum clock generation circuit according to the second aspect is
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage corresponding to the phase difference;
Voltage-controlled oscillation means for generating and outputting an output clock signal having a frequency corresponding to the control voltage;
One of the phases obtained by equally dividing one cycle of the output clock signal into a predetermined number is selected, a phase shift clock signal having a rising edge in the selected phase is generated, and the phase shift clock signal is used as the feedback signal. Phase interpolation means for sending to the phase comparison means;
Phase control means.
The phase control means selects the phase-shifted clock signal selected by the phase interpolating means so that the period of the phase-shifted clock signal is changed to a length changed from the period of the output clock signal by a predetermined first phase shift amount. The phase of the rising edge is determined, and the phase interpolation means is controlled to select the determined phase. The phase control unit generates a second phase shift amount that periodically changes within a predetermined range, and adds the second phase shift amount to the first phase shift amount. The phase control means determines the phase of the rising edge of the phase shift clock signal selected by the phase interpolation means, and performs spread spectrum modulation on the output clock signal with the second phase shift amount that periodically changes.
The voltage controlled oscillation means generates a multiphase clock signal synchronized with the output clock signal,
The phase interpolation means includes
A first buffer circuit for buffering and amplifying the multiphase clock signal output from the voltage controlled oscillation means;
An input stage circuit that receives the multiphase clock output from the first buffer circuit, a constant current source connected to the input stage circuit, and the received multiphase clock signal provided in the constant current source A phase selection circuit including a plurality of switches that select two adjacent phases and output a clock signal;
A second buffer circuit for buffering and amplifying the clock signal from the phase selection circuit;
Phase interpolation means for interpolating the phase of the clock signal from the second buffer and generating a phase-interpolated clock signal.

A spread spectrum clock generation circuit according to a third aspect is
Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage corresponding to the phase difference;
Voltage-controlled oscillation means for generating and outputting an output clock signal having a frequency corresponding to the control voltage;
One of the phases obtained by equally dividing one cycle of the output clock signal into a predetermined number is selected, a phase shift clock signal having a rising edge in the selected phase is generated, and the phase shift clock signal is used as the feedback signal. Phase interpolation means for sending to the phase comparison means;
Phase control means.
The phase control means selects the phase-shifted clock signal selected by the phase interpolating means so that the period of the phase-shifted clock signal is changed to a length changed from the period of the output clock signal by a predetermined first phase shift amount. The phase of the rising edge is determined, and the phase interpolation means is controlled to select the determined phase. The phase control unit generates a second phase shift amount that periodically changes within a predetermined range, and adds the second phase shift amount to the first phase shift amount. The phase control means determines the phase of the rising edge of the phase shift clock signal selected by the phase interpolation means, and performs spread spectrum modulation on the output clock signal with the second phase shift amount that periodically changes.
The voltage controlled oscillation means generates a multiphase clock signal synchronized with the output clock signal,
The phase interpolation means includes
A plurality of first switch means for selecting two adjacent phases from the received multi-phase clock signal and outputting a clock signal;
A plurality of second switch means for connecting a load equivalent to the selected time when not selected;
Selector means for outputting a clock signal having the determined phase from clock signals from the plurality of first switches;
Phase interpolation means for interpolating the phases of the two clock signals output from the selector means, and generating and outputting the interpolated clock signals.

A spread spectrum clock generation circuit according to a fourth aspect is the spread spectrum clock generation circuit according to the first aspect,
The voltage controlled oscillation means generates a multiphase clock signal synchronized with the output clock signal,
The phase interpolation means includes
A plurality of first switch means for selecting two adjacent phases from the received multi-phase clock signal and outputting a clock signal;
A plurality of second switch means for connecting a load equivalent to the selected time when not selected;
Selector means for outputting a clock signal having the determined phase from clock signals from the plurality of first switches;
Phase interpolation means for interpolating the phases of the two clock signals output from the selector means, and generating and outputting the interpolated clock signals.

A spread spectrum clock generation circuit according to a fifth aspect is the spread spectrum clock generation circuit according to the second aspect,
The voltage controlled oscillation means generates a multiphase clock signal synchronized with the output clock signal,
The phase interpolation means includes
A plurality of first switch means for selecting two adjacent phases from the received multi-phase clock signal and outputting a clock signal;
A plurality of second switch means for connecting a load equivalent to the selected time when not selected;
Selector means for outputting a clock signal having the determined phase from clock signals from the plurality of first switches;
3. The spread spectrum clock generation circuit according to claim 2, further comprising phase interpolation means for interpolating the phases of the two clock signals output from the selector means and generating and outputting the interpolated clock signals.

  An electronic apparatus according to a sixth aspect includes the spread spectrum clock generation circuit according to any one of the first to fifth aspects.

1 ... Phase frequency comparator,
2 ... Charge pump
3 ... Loop filter,
4 ... Voltage controlled oscillator,
5 ... Phase controller,
6, 6A ... Phase interpolation circuit,
10: Reference clock generator,
11 ... Input divider,
12: Output frequency divider.
20 ... Differential buffer circuit,
21, 21A ... phase selection circuit,
21a, 21b ... phase selection circuit section,
22: Phase interpolation unit,
23: Output clock generator,
31 ... Switch circuit,
32 ... selector,
50: Device controller,
B0 to B16, BA0 to BA15, BB1 to BB2, BB11 ... differential buffer,
BL0N to BL15N, BL0P to BL15P ... dummy load,
Da0 to Da15, Dc0 to Dc15, De1 to De2 ... differential pairs,
DSC1 ... differential / single converter,
Ia0n to Ia15n, Ia0p to Ia15p, Ib0 to Ib15, Ic0n to Ic15n, Ic0p to Ic15p, Id0 to Id15, Ie1, Ie2 ... constant current source,
If1, If2 ... variable current source,
PS0 to PS15, PT0 to PT15, PU0 to PU15, phase selection unit,
Qa0n to Qa15n, Qa0p to Qa15p, Qc0n to Qc15n, Qc0p to Qc15p, Qe11, Qe12, Qe21, Qe22 ... MOS transistors,
R1 ... Ring oscillator,
SW0 to SW15, SX0 to SX15, SW0N to SW15N, SW0P to SW15P, SW0Q to SW15Q, SW0R to SW15R, switches.

JP 2012-195826 A Japanese Patent Laid-Open No. 2005-020083

Claims (6)

Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage corresponding to the phase difference;
Voltage-controlled oscillation means for generating and outputting an output clock signal having a frequency corresponding to the control voltage;
One of the phases obtained by equally dividing one cycle of the output clock signal into a predetermined number is selected, a phase shift clock signal having a rising edge in the selected phase is generated, and the phase shift clock signal is used as the feedback signal. Phase interpolation means for sending to the phase comparison means;
The phase shift clock signal selected by the phase interpolating means is set so that the period of the phase shift clock signal is changed from the period of the output clock signal by a predetermined first phase shift amount. A phase control means for determining the phase of the rising edge and controlling the phase interpolation means so as to select the determined phase;
The phase control means generates a second phase shift amount that periodically changes within a predetermined range, and adds the second phase shift amount to the first phase shift amount. A spread-spectrum clock generation circuit that determines a phase of a rising edge of the phase-shifted clock signal selected by the means and spread-spectrum modulates the output clock signal by the second phase shift amount that periodically changes;
The spread spectrum clock generation circuit, wherein the phase control means controls to change the selected phase data immediately after the phase data update signal indicating the phase update is updated. Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage corresponding to the phase difference;
Voltage-controlled oscillation means for generating and outputting an output clock signal having a frequency corresponding to the control voltage;
One of the phases obtained by equally dividing one cycle of the output clock signal into a predetermined number is selected, a phase shift clock signal having a rising edge in the selected phase is generated, and the phase shift clock signal is used as the feedback signal. Phase interpolation means for sending to the phase comparison means;
The phase shift clock signal selected by the phase interpolating means is set so that the period of the phase shift clock signal is changed from the period of the output clock signal by a predetermined first phase shift amount. A phase control means for determining the phase of the rising edge and controlling the phase interpolation means so as to select the determined phase;
The phase control means generates a second phase shift amount that periodically changes within a predetermined range, and adds the second phase shift amount to the first phase shift amount. A spread-spectrum clock generation circuit that determines a phase of a rising edge of the phase-shifted clock signal selected by the means and spread-spectrum modulates the output clock signal by the second phase shift amount that periodically changes;
The voltage controlled oscillation means generates a multiphase clock signal synchronized with the output clock signal,
The phase interpolation means includes
A first buffer circuit for buffering and amplifying the multiphase clock signal output from the voltage controlled oscillation means;
An input stage circuit that receives the multiphase clock output from the first buffer circuit, a constant current source connected to the input stage circuit, and the received multiphase clock signal provided in the constant current source A phase selection circuit including a plurality of switches that select two adjacent phases and output a clock signal;
A second buffer circuit for buffering and amplifying the clock signal from the phase selection circuit;
A spread spectrum clock generation circuit comprising phase interpolation means for interpolating a phase of a clock signal from the second buffer and generating a phase-interpolated clock signal. Phase comparison means for detecting a phase difference between a reference input clock signal and a feedback signal and outputting a control voltage corresponding to the phase difference;
Voltage-controlled oscillation means for generating and outputting an output clock signal having a frequency corresponding to the control voltage;
One of the phases obtained by equally dividing one cycle of the output clock signal into a predetermined number is selected, a phase shift clock signal having a rising edge in the selected phase is generated, and the phase shift clock signal is used as the feedback signal. Phase interpolation means for sending to the phase comparison means;
The phase shift clock signal selected by the phase interpolating means is set so that the period of the phase shift clock signal is changed from the period of the output clock signal by a predetermined first phase shift amount. A phase control means for determining the phase of the rising edge and controlling the phase interpolation means so as to select the determined phase;
The phase control means generates a second phase shift amount that periodically changes within a predetermined range, and adds the second phase shift amount to the first phase shift amount. A spread-spectrum clock generation circuit that determines a phase of a rising edge of the phase-shifted clock signal selected by the means and spread-spectrum modulates the output clock signal by the second phase shift amount that periodically changes;
The voltage controlled oscillation means generates a multiphase clock signal synchronized with the output clock signal,
The phase interpolation means includes
A plurality of first switch means for selecting two adjacent phases from the received multi-phase clock signal and outputting a clock signal;
A plurality of second switch means for connecting a load equivalent to the selected time when not selected;
Selector means for outputting a clock signal having the determined phase from clock signals from the plurality of first switches;
A spread spectrum clock generation circuit comprising phase interpolation means for interpolating the phases of two clock signals output from the selector means and generating and outputting an interpolated clock signal. The voltage controlled oscillation means generates a multiphase clock signal synchronized with the output clock signal,
The phase interpolation means includes
A plurality of first switch means for selecting two adjacent phases from the received multi-phase clock signal and outputting a clock signal;
A plurality of second switch means for connecting a load equivalent to the selected time when not selected;
Selector means for outputting a clock signal having the determined phase from clock signals from the plurality of first switches;
2. The spread spectrum clock generation circuit according to claim 1, further comprising phase interpolation means for interpolating the phases of the two clock signals output from the selector means, and generating and outputting the interpolated clock signals. The voltage controlled oscillation means generates a multiphase clock signal synchronized with the output clock signal,
The phase interpolation means includes
A plurality of first switch means for selecting two adjacent phases from the received multi-phase clock signal and outputting a clock signal;
A plurality of second switch means for connecting a load equivalent to the selected time when not selected;
Selector means for outputting a clock signal having the determined phase from clock signals from the plurality of first switches;
3. The spread spectrum clock generation circuit according to claim 2, further comprising phase interpolation means for interpolating the phases of the two clock signals output from the selector means and generating and outputting the interpolated clock signals.   An electronic apparatus comprising the spread spectrum clock generation circuit according to any one of claims 1 to 5.

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