CN203747754U - 1/2 frequency divider circuit based on current mirror switching logic and frequency divider - Google Patents
1/2 frequency divider circuit based on current mirror switching logic and frequency divider Download PDFInfo
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- CN203747754U CN203747754U CN201320761521.XU CN201320761521U CN203747754U CN 203747754 U CN203747754 U CN 203747754U CN 201320761521 U CN201320761521 U CN 201320761521U CN 203747754 U CN203747754 U CN 203747754U
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Abstract
The utility model discloses a 1/2 frequency divider circuit based on a current mirror switching logic and a frequency divider and belongs to the technical field of integrated circuit. The 1/2 frequency divider circuit includes a power source positive input port, a power source negative input port, a difference clock positive phase signal input port, a different clock negative phase signal input port, a different positive phase data signal input port, a different negative phase data signal input port, a Q-channel difference positive phase frequency division signal output port, a Q-channel difference negative phase frequency division signal output port, a PMOS tube current mirror bias voltage input port, an NMOS tube current mirror bias voltage input port and 2 D-triggers. PMOS tubes are utilized for replacing load resistors in a traditional 1/2 frequency divider, such that chip area is reduced. By utilizing the active devices for replacing the passive devices, a shortcoming that the resistors have to work for the switching on of a current mirror switch is overcome. At the same time, power consumption in the same power frequency is reduced and the 1/2 frequency divider circuit can work in a low-voltage condition through the alternating switching-on of the two PMOS tubes. The 1/2 frequency divider circuit is low in noise, high in anti-interference capability and has a comparatively wide frequency input range.
Description
Technical field
The utility model based on current mirror switching logic except two-divider circuit and frequency divider, belong to the technical field of integrated circuit.
Background technology
Along with the development of IC industry, the continuous progress of cmos circuit manufacturing technology, adopt the Wireless Telecom Equipment of CMOS technique manufacture also to produce huge variation, these development trends that are changed to high-frequency, low-power consumption and become next stage wireless communication technology lay the foundation.
Present stage, the transceiver of wireless communication technology mainly adopts phase-locked loop frequency synthesizer to realize, phase-locked loop frequency is by voltage controlled oscillator (VCO, Voltage Controlled Oscillator) and pre-divider composition, and it can utilize local oscillation signal to realize the function of up-conversion and down-conversion.In this synthesizer, the module that operating frequency is higher is pre-divider, and its power consumption accounts for major part in whole phase-locked loop frequency synthesizer, and along with the increase of frequency, the shared power dissipation ratio of pre-divider will be larger.On the other hand, along with chip integrated in mobile device (as dull and stereotyped, mobile phone) is more and more, the power consumption that needs phase-locked loop to consume is lower with extending battery life, and this has also proposed the requirement of low-power consumption to the design of pre-divider.To sum up, attempting to design the pre-divider of a kind of high frequency, low-power consumption will be more difficult.
In accompanying drawing 1, provide traditional project organization, this structure is a kind of d type flip flop based on high speed current mode logic (CML, Current Mode Logic), can realize at a high speed except two-divider on the basis of this d type flip flop, reach operating rate relatively very fast, low noise object.But, this structure is owing to adopting the framework (two resistance R 1 in accompanying drawing 1 and R2) of load resistance, it is relatively little that the high speed that this framework is realized is removed two-divider output voltage swing voltage, and due to the existence of resistance, cause the chip area of realization larger, in addition, the limited of resistance can not turn-off part path in signal switching process completely, causes the power consumption of whole circuit relatively to increase.
Chinese patent (CN102291132B) has proposed a kind of new structure, this structure is on traditional C ML structure d type flip flop basis, remove tail current source biasing, and adopt PMOS pipe to do load, simultaneously, adopt again PMOS and NMOS complementary cross-coupled pair structure etc. in circuit output stage, finally realized and having ensured under the condition of circuit high speed operation, improve the amplitude of oscillation of output signal and make it reach the object of approximate long arc.But the structure that this patent proposes has increased by 4 metal-oxide-semiconductors than traditional structure, the increase of metal-oxide-semiconductor can make the area change of chip undoubtedly, on the other hand, also can make the power consumption of chip increase.
Thereby for making pre-frequency dividing circuit be widely used in wireless communication field, as WLAN (WLAN), in global positioning system (GPS) etc., the long arc that designs targetedly a kind of low-power consumption, high frequency will seem particularly important except two-divider circuit.
Utility model content
Technical problem to be solved in the utility model is the deficiency for above-mentioned background technology, provide based on current mirror switching logic except two-divider circuit and frequency divider.
The utility model adopts following technical scheme for realizing above-mentioned utility model object:
Based on current mirror switching logic except two-divider circuit, comprise:
Power supply positive input port, power-input port, differential clocks positive signal input port, differential clocks negative signal input port, difference positive data-signal input port, difference negative data-signal input port, Q road difference positive fractional frequency signal output port, Q road difference negative fractional frequency signal output port, first, second d type flip flop;
Wherein, the D end of the first d type flip flop is connected with the QN end of the second d type flip flop, the DN end of the first d type flip flop is connected with the Q end of the second d type flip flop, and the Q end of the first d type flip flop is connected with the D end of the second d type flip flop, and the first d type flip flop QN end is connected with the second d type flip flop DN end;
The described two-divider circuit that removes also comprises: pmos current mirror bias voltage input port, NMOS tube current mirror bias voltage input port;
Each d type flip flop comprises: first, the first common source differential pair of the second metal-oxide-semiconductor composition, the 3rd, the second common source differential pair of the 4th metal-oxide-semiconductor composition, the 5th, the 3rd common source differential pair of the 6th metal-oxide-semiconductor composition, the 7th, the 4th common source differential pair of the 8th metal-oxide-semiconductor composition, wake flow pipe, wherein, the source electrode tie point of the first common source differential pair connects power supply positive input port, described the first metal-oxide-semiconductor drain electrode, the 3rd metal-oxide-semiconductor drain electrode, the 5th metal-oxide-semiconductor drain electrode, the 6th metal-oxide-semiconductor grid is connected with Q road difference negative fractional frequency signal output port respectively, described the second metal-oxide-semiconductor drain electrode, the 4th metal-oxide-semiconductor drain electrode, the 5th metal-oxide-semiconductor grid, the 6th metal-oxide-semiconductor drain electrode is connected with Q road difference positive fractional frequency signal output port respectively, described the 3rd metal-oxide-semiconductor grid connects difference positive data-signal input port, described the 4th metal-oxide-semiconductor grid connects difference negative data-signal input port, described the 7th metal-oxide-semiconductor drain electrode is connected with the source electrode tie point of described the second common source differential pair, the 7th metal-oxide-semiconductor grid connects differential clocks negative signal input port, the source electrode tie point that described the 8th metal-oxide-semiconductor drain electrode connects described the 3rd common source differential pair connects, the 8th metal-oxide-semiconductor grid connects differential clocks positive signal input port, described wake flow pipe drain electrode connects the source electrode tie point of described the 4th common source differential pair, wake flow pipe source electrode connects power-input port,
Described first, second metal-oxide-semiconductor is PMOS pipe, and grid all connects pmos current mirror bias voltage input port;
Described the 3rd, the 4th, the 5th, the 6th, the 7th, the 8th metal-oxide-semiconductor and wake flow pipe are NMOS pipe, and grid all connects NMOS tube current mirror bias voltage input port.
As the described further prioritization scheme except two-divider circuit, first, second metal-oxide-semiconductor has equal breadth length ratio, and the 3rd, the 4th, the 5th, the 6th metal-oxide-semiconductor has equal breadth length ratio, and the 7th, the 8th metal-oxide-semiconductor has equal breadth length ratio.
Further, described in a cascade N claim 1 or 2 except two-divider circuit, form 2
nfrequency divider, N is natural number.
The utility model adopts technique scheme, has following beneficial effect:
(1) utilize PMOS pipe to substitute tradition except load resistance in two-divider, reduced chip area;
(2) replace passive device to avoid the defect of resistance as a kind of conducting of current mirror switch using active device, meanwhile, the alternate conduction of two PMOS pipes, less power consumption under same frequency, and can be under low-voltage condition;
(3) low noise, antijamming capability is high, frequency input range is wider.
Brief description of the drawings
Fig. 1 is the circuit diagram of traditional C ML structure d type flip flop.
Fig. 2 is described in the utility model except two-divider circuit block diagram.
Fig. 3 is the circuit diagram of d type flip flop in the utility model.
Fig. 4 is the simulation waveform figure that the utility model removes two-divider circuit.
Fig. 5 is the 32 frequency dividing circuit figure that 5 grades of the utility model of cascade form except two-divider.
Fig. 6 is the simulation waveform figure of 32 frequency dividing circuits shown in Fig. 5.
Number in the figure explanation: M1-M8 is the first to the 8th metal-oxide-semiconductor, and M9 is wake flow pipe, and R1, R2 are resistance.
Embodiment
Below in conjunction with accompanying drawing, the technical scheme of utility model is elaborated:
That in Fig. 1, the output of the d type flip flop Q road difference positive fractional frequency signal output port Q of traditional C ML framework, Q road difference negative fractional frequency signal output port QN adopts is two-way load resistance R1, R2, because load resistance resistance is limited, cause also limited (the traditional structure maximum output voltage amplitude of oscillation=load resistance * tail current/2) of maximum output voltage swing of Q road difference positive fractional frequency signal output port Q, Q road difference negative fractional frequency signal output port QN.
The utility model disclosed based on current mirror switching logic except two-divider circuit as shown in Figure 2, comprise: power supply positive input port Vdd, power-input port Vss, differential clocks positive signal input port CN, differential clocks negative signal input port CP, difference positive data-signal input port D, difference negative data-signal input port DN, Q road difference positive fractional frequency signal output port Q, Q road difference negative fractional frequency signal output port QN, pmos current mirror bias voltage input port Vbp, NMOS tube current mirror bias voltage input port Vbn, 2 d type flip flops.The first trigger DFF1:D end is connected with the QN end of the second d type flip flop DFF2, and DN end is connected with the Q end of the second d type flip flop DFF2, and Q end is connected with the D end of the second d type flip flop DFF2, and QN end is connected with the DN end of the second d type flip flop DFF2.Two d type flip flop cascade and feedbacks that CP clock is anti-phase; Total CP rising edge, the Q of prime d type flip flop equals D(and the QN of rear class d type flip flop is transmitted), the Q of rear class d type flip flop and QN keep; Total CP trailing edge, the Q of prime d type flip flop and QN keep, and rear class Q equals D, and Q and QN complete once inside out, are typical CP pulse trailing edge upset.
2 d type flip flop structures are identical, and each d type flip flop comprises as shown in Figure 3: first, the second metal-oxide-semiconductor M1, the first common source differential pair of M2 composition, the 3rd, the 4th metal-oxide-semiconductor M3, the second common source differential pair of M4 composition, the 5th, the 6th metal-oxide-semiconductor M5, the 3rd common source differential pair of M6 composition, the 7th, the 8th metal-oxide-semiconductor M7, the 4th common source differential pair of M8 composition, wake flow pipe M9, the source electrode tie point of the first common source differential pair meets power supply positive input port Vdd, the first metal-oxide-semiconductor M1 drain electrode, the 3rd metal-oxide-semiconductor M3 drain electrode, the 5th metal-oxide-semiconductor M5 drain electrode, the 6th metal-oxide-semiconductor M6 grid is connected with Q road difference negative fractional frequency signal output port QN respectively, the second metal-oxide-semiconductor M2 drain electrode, the 4th metal-oxide-semiconductor M4 drain electrode, the 5th metal-oxide-semiconductor M5 grid, the 6th metal-oxide-semiconductor M6 drain electrode is connected with Q road difference positive fractional frequency signal output port Q respectively, the 3rd metal-oxide-semiconductor M3 grid meets difference positive data-signal input port D, the 4th metal-oxide-semiconductor M4 grid meets difference negative data-signal input port DN, the 7th metal-oxide-semiconductor M7 drain electrode is connected with the source electrode tie point of the second common source differential pair, the 7th metal-oxide-semiconductor M7 grid meets differential clocks negative signal input port CP, the source electrode tie point that the 8th metal-oxide-semiconductor M8 drain electrode connects the 3rd common source differential pair connects, the 8th metal-oxide-semiconductor M8 grid meets differential clocks positive signal input port CN, wake flow pipe M9 drain electrode connects the source electrode tie point of the 4th common source differential pair, and wake flow pipe M9 source electrode meets power-input port Vss.First, second metal-oxide-semiconductor M1, M2 are PMOS pipe, and grid all meets pmos current mirror bias voltage input port Vbp.Three, the 4th, the 5th, the 6th, the 7th, the 8th metal-oxide-semiconductor and wake flow pipe M3, M4, M5, M6, M7, M8, M9 are NMOS pipe, and grid all meets NMOS tube current mirror bias voltage input port Vbn.
Power supply positive input port Vdd is 3.0V, power-input port Vss is 0V, pmos current mirror bias voltage input port Vbp is that the PMOS reference current that 1.642V(is corresponding is 10uA), NMOS tube current mirror bias voltage input port Vbn is that the NMOS reference current that 952mV(is corresponding is 10uA).Differential clocks negative signal input port CP, differential clocks positive signal input port CN, frequency is 500MHz, amplitude 500mV(is from 2.5V to 3V), phase phasic difference is 180 degree.
The first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 have equal breadth length ratio (W/L=1.4u/1.0u), the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 have equal breadth length ratio (W/L=1.2u/350n), the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 have equal breadth length ratio (W/L=2u/350n), the 9th metal-oxide-semiconductor M9 breadth length ratio (W/L=5u/4u).
Suppose that initial state difference positive data-signal input port D is for high, difference negative data-signal input port DN is low,
The d type flip flop structure working principle the utility model proposes is described as:
(1) suppose when initial, first differential clocks negative signal input signal CP is that high impulse first arrives, i.e. the 3rd, the 7th metal-oxide-semiconductor M3, M7 conducting, the first metal-oxide-semiconductor M1 conducting of left side branch road, image current Ia just all flows to tail current Ic, and the drain terminal of the first metal-oxide-semiconductor M1 is dragged down; The right branch road is because the 8th metal-oxide-semiconductor M8 ends, therefore image current Ib conductively-closed, image current Ib cannot pass through, and the second metal-oxide-semiconductor M2 drain terminal is drawn high to Vdd;
(2) suppose when initial, first differential clocks negative signal input signal CP is that low pulse first arrives, the positive phase signals input of differential clocks CN is high, the 8th metal-oxide-semiconductor M8 conducting, the 7th MOS closes M7 cut-off, five, common latch (Latch) structure that forms a positive feedback of the 6th metal-oxide-semiconductor M5, the cross-linked connection of M6 and load current mirror, Q and QN remain Last status, the state of Q and QN is not subject to the impact of D end and changes.
Thereby this d type flip flop is at CP rising edge of a pulse Q=D, at CP pulse trailing edge, Q and QN latch also keep laststate.
The oscillogram analogous diagram except two-divider circuit differential clocks negative signal input signal CP, Q road difference positive fractional frequency signal output signal Q that the utility model embodiment provides as shown in Figure 4, as can be seen from the figure the cycle of Q road difference positive fractional frequency signal output signal Q is 2 times of differential clocks negative signal input signal CP cycle, realized the function of 2 frequency divisions, the amplitude of oscillation of Q road difference positive fractional frequency signal output signal Q is 2.4V-3.0V.
5 grades of the utility model embodiment of cascade utilization except two-divider circuit form 32 frequency dividing circuit figure as shown in Figure 5, its operation principle is similar to two-divider circuit working principle, does not repeat at this.
As shown in Figure 6, the cycle of Q road difference positive fractional frequency signal output signal Q is 32 times of differential clocks negative signal input signal CP cycle to the wave simulation figure of 32 frequency dividing circuits shown in Fig. 5, has realized the function of 32 frequency divisions, and the amplitude of oscillation of signal Q is 1.75V-3.0V.
What the utility model related to removes two-divider circuit, has following beneficial effect:
(1) utilize PMOS pipe to substitute tradition except load resistance in two-divider, reduced chip area;
(2) replace passive device to avoid the defect of resistance as a kind of conducting of current mirror switch using active device, meanwhile, the alternate conduction of two PMOS pipes, less power consumption under same frequency, and can be under low-voltage condition;
(3) low noise, antijamming capability is high, frequency input range is wider.
Claims (3)
- Based on current mirror switching logic except two-divider circuit, comprise: power supply positive input port, power-input port, differential clocks positive signal input port, differential clocks negative signal input port, difference positive data-signal input port, difference negative data-signal input port, Q road difference positive fractional frequency signal output port, Q road difference negative fractional frequency signal output port, first, second d type flip flop;Wherein, the D end of the first d type flip flop is connected with the QN end of the second d type flip flop, the DN end of the first d type flip flop is connected with the Q end of the second d type flip flop, and the Q end of the first d type flip flop is connected with the D end of the second d type flip flop, and the first d type flip flop QN end is connected with the second d type flip flop DN end;It is characterized in that:The described two-divider circuit that removes also comprises: pmos current mirror bias voltage input port, NMOS tube current mirror bias voltage input port;Each d type flip flop comprises: first, the first common source differential pair of the second metal-oxide-semiconductor composition, the 3rd, the second common source differential pair of the 4th metal-oxide-semiconductor composition, the 5th, the 3rd common source differential pair of the 6th metal-oxide-semiconductor composition, the 7th, the 4th common source differential pair of the 8th metal-oxide-semiconductor composition, wake flow pipe, wherein, the source electrode tie point of the first common source differential pair connects power supply positive input port, described the first metal-oxide-semiconductor drain electrode, the 3rd metal-oxide-semiconductor drain electrode, the 5th metal-oxide-semiconductor drain electrode, the 6th metal-oxide-semiconductor grid is connected with Q road difference negative fractional frequency signal output port respectively, described the second metal-oxide-semiconductor drain electrode, the 4th metal-oxide-semiconductor drain electrode, the 5th metal-oxide-semiconductor grid, the 6th metal-oxide-semiconductor drain electrode is connected with Q road difference positive fractional frequency signal output port respectively, described the 3rd metal-oxide-semiconductor grid connects difference positive data-signal input port, described the 4th metal-oxide-semiconductor grid connects difference negative data-signal input port, described the 7th metal-oxide-semiconductor drain electrode is connected with the source electrode tie point of described the second common source differential pair, the 7th metal-oxide-semiconductor grid connects differential clocks negative signal input port, the source electrode tie point that described the 8th metal-oxide-semiconductor drain electrode connects described the 3rd common source differential pair connects, the 8th metal-oxide-semiconductor grid connects differential clocks positive signal input port, described wake flow pipe drain electrode connects the source electrode tie point of described the 4th common source differential pair, wake flow pipe source electrode connects power-input port,Described first, second metal-oxide-semiconductor is PMOS pipe, and grid all connects pmos current mirror bias voltage input port;Described the 3rd, the 4th, the 5th, the 6th, the 7th, the 8th metal-oxide-semiconductor and wake flow pipe are NMOS pipe, and grid all connects NMOS tube current mirror bias voltage input port.
- 2. according to claim 1 except two-divider circuit, it is characterized in that, described first, second metal-oxide-semiconductor has equal breadth length ratio, and the 3rd, the 4th, the 5th, the 6th metal-oxide-semiconductor has equal breadth length ratio, and the 7th, the 8th metal-oxide-semiconductor has equal breadth length ratio.
- 3. the frequency divider based on current mirror switching logic, is characterized in that, described in a cascade N claim 1 or 2 except two-divider circuit, form 2 nfrequency divider, N is natural number.
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| CN201320761521.XU CN203747754U (en) | 2013-11-27 | 2013-11-27 | 1/2 frequency divider circuit based on current mirror switching logic and frequency divider |
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| CN201320761521.XU CN203747754U (en) | 2013-11-27 | 2013-11-27 | 1/2 frequency divider circuit based on current mirror switching logic and frequency divider |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103825610A (en) * | 2013-11-27 | 2014-05-28 | 无锡芯响电子科技有限公司 | Dividing two frequency divider circuit based on current mirror switch logic |
| CN109039331A (en) * | 2018-10-30 | 2018-12-18 | 中国电子科技集团公司第五十四研究所 | A kind of digital 8/9 pre- frequency dividing circuit for local oscillation circuit |
| CN110504956A (en) * | 2019-07-05 | 2019-11-26 | 加驰（厦门）微电子股份有限公司 | A kind of broadband pre-divider that power consumption is adaptive |
| CN114564068A (en) * | 2022-03-02 | 2022-05-31 | 重庆吉芯科技有限公司 | Adaptive current generation circuit and method applied to high-speed ADC input buffer |
-
2013
- 2013-11-27 CN CN201320761521.XU patent/CN203747754U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103825610A (en) * | 2013-11-27 | 2014-05-28 | 无锡芯响电子科技有限公司 | Dividing two frequency divider circuit based on current mirror switch logic |
| CN103825610B (en) * | 2013-11-27 | 2017-01-18 | 无锡芯响电子科技有限公司 | Dividing two frequency divider circuit based on current mirror switch logic |
| CN109039331A (en) * | 2018-10-30 | 2018-12-18 | 中国电子科技集团公司第五十四研究所 | A kind of digital 8/9 pre- frequency dividing circuit for local oscillation circuit |
| CN110504956A (en) * | 2019-07-05 | 2019-11-26 | 加驰（厦门）微电子股份有限公司 | A kind of broadband pre-divider that power consumption is adaptive |
| CN114564068A (en) * | 2022-03-02 | 2022-05-31 | 重庆吉芯科技有限公司 | Adaptive current generation circuit and method applied to high-speed ADC input buffer |
| CN114564068B (en) * | 2022-03-02 | 2023-07-14 | 重庆吉芯科技有限公司 | Adaptive current generation circuit and method applied to high-speed ADC input buffer |
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Address after: Room E701 No. 20 building science and Technology Park Liye sensor network university 214135 Jiangsu province Wuxi City District Qingyuan Road Patentee after: Wuxi Xinxiang Electronic Technology Co., Ltd. Address before: 214135 Jiangsu Province, Wuxi City District Qingyuan Road Branch Park 530 building A room 512 Patentee before: Wuxi Xinxiang Electronic Technology Co., Ltd. |