CN110504956A - A kind of broadband pre-divider that power consumption is adaptive - Google Patents
A kind of broadband pre-divider that power consumption is adaptive Download PDFInfo
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- CN110504956A CN110504956A CN201910602948.7A CN201910602948A CN110504956A CN 110504956 A CN110504956 A CN 110504956A CN 201910602948 A CN201910602948 A CN 201910602948A CN 110504956 A CN110504956 A CN 110504956A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
Abstract
The invention discloses a kind of broadband pre-divider that power consumption is adaptive, including main latch and from latch；The main latch and described feedback loop is connected and composed from latch；The main latch and described input load adjustment signal and bias current adjustment signal are respectively used to from latch, and according to the load regulation Signal Regulation payload size, bias current size is adjusted according to the bias current adjustment signal, according to the work status after adjusting；Wherein, the load regulation signal and bias current adjustment signal are arranged according to the size of input frequency.Using the embodiment of the present invention, the bandwidth of operation of pre-divider can be improved while optimizing power consumption.
Description
Technical field
The present invention relates to electronic equipment, technical field of electronic devices more particularly to a kind of broadbands that power consumption is adaptive to divide in advance
Frequency device.
Background technique
In recent years, the fast development of wireless telecommunications brings unthinkable dramatic change to the life of people the present and the future
With convenience.Wireless communication technique is largely applied to mobile phone, Wireless LAN (WLAN), bluetooth (Bluetooth) etc.
Aspect, a variety of different agreements and application emerge one after another, and the working frequency of various wireless communication standards is extended from several hundred megahertzs
To G hertz several.In a wireless communication system, phase-locked loop frequency synthesizer is as part indispensable in wireless communication system
Channel needed for communication signal sends and receives offer, and be the local oscillation signal of communication system generation high-quality, and in feedback loop
On pre-divider be then phase-locked loop frequency synthesizer important component.
In high-speed high frequency circuit system, the power consumption of the higher circuit part consumption of general work frequency is bigger, and designs
On it is also the most key, pre-divider, which passes through, in radio-frequency front-end carries out pre- scaling down processing to VCO (voltage controlled oscillator) output, reduces
Signal frequency, in order to which digital frequency divider thereafter is further processed signal, therefore other than VCO, pre-divider is faced with
Highest frequency part in system consumes most power consumptions in communication system.
By being found to a variety of pre-divider structural researches, traditional pre-divider based on hypotactic dual latch
Structure chart is as shown in Figure 1, when clock falling edge is interim, the triggering of main latch 11 and fan-out is according to being updated, at this time from
Latch 12 is closed, and fan-out evidence is kept；When rising edge clock comes temporarily, main latch 11 is in hold mode, this
When be triggered from latch 12, fan-out is according to being updated.The pre-divider have biggish working range and to common-mode noise and
Common mode interference has very strong inhibiting effect, and has many advantages, such as that stability is good, in frequency applications by through frequently with.
But the pre-divider intrinsic disadvantage, when being the rising with working frequency, operating power consumption also significantly increases,
It is continuously maintained at high-frequency band power consumption even if radio-frequency front-end system working channel frequency hopping is to its power consumption of low-frequency range, to system function
Consumption is a greatly waste.
Summary of the invention
The embodiment of the present invention proposes a kind of broadband pre-divider that power consumption is adaptive, can improve while optimizing power consumption
The bandwidth of operation of pre-divider.
The embodiment of the present invention provides a kind of broadband pre-divider that power consumption is adaptive, including main latch and from latch；
The main latch and described feedback loop is connected and composed from latch；
The main latch and it is described be respectively used to input load adjustment signal and bias current adjustment signal from latch,
And according to the load regulation Signal Regulation payload size, bias current size is adjusted according to the bias current adjustment signal,
According to the work status after adjusting；
Wherein, the load regulation signal and bias current adjustment signal are arranged according to the size of input frequency
's.
Further, the main latch and described from latch to respectively include load defeated to pipe, clock to, Differential Input
Enter to pipe, output to pipe and biasing circuit；
The load is to for the payload size according to latch where the load regulation Signal Regulation；
The bias current size of latch where the biasing circuit is used to be adjusted according to the bias current adjustment signal；
The clock input is used for input clock signal to pipe；
The Differential Input is used to amplify the difference of the frequency signal of input to pipe；
The output is used to pipe carry out shaping output to the signal of amplification.
Further, the main latch and it is described from latch respectively further comprise load regulation signal input part, biasing
Current regulating signal input terminal, a pair of of differential data input terminal, a pair of of differential clock signal input terminal and a pair of of difference output end；
In each latch, it is described load to respectively with the load regulation signal input part, the Differential Input pair
Pipe, the connection of the pair of difference output end；The Differential Input to pipe respectively with the pair of differential data input terminal, described one
Difference output end, clock input connect pipe；It is described output to pipe respectively with the pair of difference output end, it is described when
Clock input connects pipe；Clock input to pipe respectively with the pair of differential clock signal input terminal, the biasing circuit
Connection；
A pair of of difference output of the main latch, which is rectified, connects a pair of of differential data input terminal from latch, described
A pair of of differential data input terminal of the main latch is reversely connected from a pair of of difference output end of latch.
Further, the load of each latch to include the first load circuit and the second load circuit, described first
Load circuit and second load circuit respectively include first resistor and k+1 load branch in parallel, k >=-1；Described
One resistance is in parallel with each load branch；
Each load branch includes a metal-oxide-semiconductor and a resistive load；
In each load branch, the source electrode of the metal-oxide-semiconductor connects power supply, and the grid of the metal-oxide-semiconductor connects the load
Adjustment signal input terminal, the drain electrode of the metal-oxide-semiconductor connect one end of the resistive load, the other end connection of the resistive load
The Differential Input is to pipe；
The other end of resistive load in first load circuit and the resistive load in second load circuit
The other end is also correspondingly connected with a pair of of difference output end of place latch respectively.
Further, the biasing circuit of each latch includes the 7th transistor and impedance network；
The collector of 7th transistor connects the clock input to pipe, and the base stage connection of the 7th transistor is inclined
Voltage is held, the emitter of the 7th transistor connects the impedance network；
The impedance network includes 3rd resistor and k+1 bigoted branch in parallel；The 3rd resistor with it is each bigoted
Branch circuit parallel connection；
Each bigoted branch includes a metal-oxide-semiconductor and a resistive load；
In each bigoted branch, one end of the resistive load connects the emitter of the 7th transistor, the resistance
Property load the other end connect the drain electrode of the metal-oxide-semiconductor, the source electrode ground connection of the metal-oxide-semiconductor, described in the grid connection of the metal-oxide-semiconductor
Bias current adjustment signal input terminal.
Further, the Differential Input of each latch includes the first transistor and second transistor to Guan Jun；
The collector of the collector of the first transistor and second transistor a pair with place latch respectively
Difference output end is correspondingly connected with；The base stage of the first transistor and the base stage of the second transistor respectively with place latch
A pair of of differential data input terminal be correspondingly connected with；The emitter of the emitter of the first transistor and the second transistor point
The clock input is not connected to pipe.
Further, the output of each latch is cross-coupling output to pipe, each cross-coupling output pair to pipe
Guan Jun includes third transistor and the 4th transistor；
The collector of the collector of the third transistor and the 4th transistor a pair with place latch respectively
Difference output end is correspondingly connected with；The emitter of the emitter of the third transistor and the 4th transistor is separately connected described
Clock is inputted to pipe；The base stage of the third transistor connects the collector of the 4th transistor, the 4th transistor
Base stage connects the collector of the third transistor.
Further, the clock input of each latch includes the 5th transistor and the 6th transistor to Guan Jun；
The collector of 5th transistor is separately connected the emitter of the first transistor, the second transistor
Emitter；The collector of 6th transistor is separately connected the emitter of the third transistor, the 4th transistor
Emitter；The base stage of 5th transistor and the base stage of the 6th transistor respectively a pair of of difference with place latch when
Clock signal input part is correspondingly connected with；The emitter of 5th transistor and the emitter of the 6th transistor are separately connected institute
State the collector of the 7th transistor.
Further, the metal-oxide-semiconductor in the load branch is PMOS tube, and the metal-oxide-semiconductor in the bigoted branch is NMOS tube；
The load regulation signal and the bias current adjustment signal input terminal of the load regulation signal input part input
The bias current adjustment signal reverse phase of input.
The implementation of the embodiments of the present invention has the following beneficial effects:
The adaptive broadband pre-divider of power consumption provided in an embodiment of the present invention can be set according to the size of input frequency
It sets load regulation signal and bigoted current regulating signal and is input in two latch, make two latch according to load regulation
Signal Regulation payload size adjusts bigoted size of current according to bigoted current regulating signal, to reach adjustment circuit delay
Purpose, and then circuit power consumption is saved, improve pre-divider working band width.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of one embodiment of pre-divider in the prior art；
Fig. 2 is the structural schematic diagram of one embodiment of the adaptive broadband pre-divider of power consumption provided by the invention；
Fig. 3 is the graph of relation of latch delay and latch bias current；
Fig. 4 is the structural schematic diagram of another embodiment of the adaptive broadband pre-divider of power consumption provided by the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It referring to fig. 2, is the adaptive broadband pre-divider of power consumption provided by the invention, including two latch, i.e., main lock
Storage 1 and from latch 2；The main latch 1 and described feedback loop is connected and composed from latch 2；
The main latch 1 and described input load adjustment signal and bias current are respectively used to from latch 2 adjust letter
Number, and according to the load regulation Signal Regulation payload size, it is big that bias current is adjusted according to the bias current adjustment signal
It is small, according to the work status after adjusting；
Wherein, the load regulation signal and bias current adjustment signal are arranged according to the size of input frequency
's.
It should be noted that main latch is identical with the structure from latch.It is used in cooperation VCO (voltage controlled oscillator)
When, VCO voltage control signal digital signal be can be converted into through analog-digital converter, load regulation signal and bias current constituted
Adjustment signal is input to main latch and from latch, the size of input frequency can also be measured by frequency measurement, thus root
According to the size of measurement to main latch and from latch input load adjustment signal and bias current adjustment signal.Main latch and
From latch after inputting adjustment signal, it is loaded respectively and bias current is adjusted, and then according to the state after adjusting
Work to make the power consumption of pre-divider according to input frequency self-regulation, preferably saving circuit power consumption, and improves pre- point simultaneously
Frequency device working band width.
Further, as shown in Fig. 2, the main latch 1 includes that load inputs 21, Differential Input to pipe 23, clock
To pipe 25, output to pipe 24 and biasing circuit 26；It is described defeated to pipe 27, clock to 22, Differential Input including loading from latch 2
Enter to pipe 29, output to pipe 28 and biasing circuit 30；
The load is respectively used to be born according to latch where the load regulation Signal Regulation to 21 and load to 22
Carry size；
The biasing circuit 26 and biasing circuit 30 are respectively used to lock where adjusting according to the bias current adjustment signal
The bias current size of storage；
The clock input is respectively used to input clock signal to pipe 29 to pipe 25 and clock input；
The Differential Input is respectively used to put the difference of the frequency signal of input to pipe 23 and Differential Input to pipe 27
Greatly；
The output is respectively used to pipe 28 to carry out shaping output to the signal of amplification to pipe 24 and output.
Specifically, the load branch that multiple parallel connections are respectively included to 22 to 21 and load is loaded, according to load regulation signal
The each load branch of on or off realizes the adjusting to the payload size of place latch.Biasing circuit 26 and biasing circuit
30 respectively include the bigoted branch of multiple parallel connections, according to each bigoted branch of bias current adjustment signal on or off, realize
Adjusting to the bias current size of place latch.
It should be noted that pre-divider maximum operating frequency depends on circuit delay size, in document Jan
M.Rabaey, et al digital integrated electronic circuit --- the definition of circuit delay is given in design perspective (second edition):
Wherein, tpIt is transmission delay, A (s) is the transfer function of circuit.
Pre-divider digital for current mode logic (Current Mode Logic, CML), the delay of circuit depend on electricity
The pull-up and pulldown network on road approximate can be indicated with single order RC retardation ratio, define input to pipe and load pipe in analysis
(upper transistors) is managed for top, by clock input to pipe hereinafter defined as following pipe (lower
Transistors), delay time can regard the product of equivalent RC as, so total delay time can be with function representation
ttotal=(req_up+rload_up)ceq_up
Wherein, req_upIt indicates to remove rload_upExcept equivalent output impedance, rload_upGo out impedance for the defeated ZL1 of load equivalent,
ceq_upFor the equivalent output capacitance of half of circuit.Can be seen that from the function can be changed by changing circuit chip pipe size
req_upOr load impedance rload_upTo adjust the delay of pre-divider.
Equivalent capacity or equivalent impedance and transistor working condition for transistor in pre-divider is closely related, by with
Minor function it can be concluded that electric current and equivalent impedance relationship, wherein triode equivalent resistance and bias current relationship are as follows:
Wherein, VEIt depending on technique, is determined by base width, ICEFor the electric current of transistor collector to emitter.According to
Relationship in circuit between bias current and circuit delay, the relationship of circuit delay and bias current in available pre-divider
As shown in figure 3, circuit delay can be obviously improved by as can be seen from the figure changing bias current, but when being more than certain value,
Opposite effect can be played instead by increasing bias current value, and the electric current for defining minimum delay point is Ipeak.And it further analyzes
Know there was only 20% when influence of the biased electrical flow point lower than 60% or so to circuit delay, compromise considers speed and power consumption relationship
Generally take bias current 60%~80%.
By above-mentioned function it is found that load resistance can be adjusted simultaneously other than adjusting bias current to reach adjustment circuit
The purpose of delay.Assuming that when design parameter makes counter-divider circuit reach highest working frequency fmax=fK, corresponding at this time inclined
Set electric current IbK, load impedance size is RLK, it is assumed that circuit delay ttotal=tk, in linear system, different frequency input letter
It is constant that number delay can centainly regard the effective fixed error of linear system as with original signal periodic ratio, does not influence system stability.
So when pre-divider input frequency drops to fK-1, it is assumed that corresponding bias current is Ib at this timek-1, load impedance size is
RLK-1, circuit delay time t at this timetotal=tk-1, then
So each frequency relation is when it is D < k:0 > that current offset and load circuit, which adjust digit,
Wherein a > 1, it is assumed that in K=0, bias current Ib0, load resistance RL0, in order to keep the defeated of pre-divider
The amplitude of oscillation is constant out, then
Δ V=IbK*RLK=IbK-1*RLK-1...=Ib1*RL1=Ib0*RL0
Bias current and load resistance meet relationship and are simultaneously
Wherein, b > 1.
According to power consumption expression formula Ppower=Vdd*Ibk
So pre-divider power consumption relationship in the case of each frequency can be obtained being
Therefore the present invention is in the range for extending pre-divider working band, while not influencing circuit system working performance
Reduce the system power dissipation of circuit.Because a and b is constant, it assumes that
A=m*b
Then the relationship of the pre- frequency of pre-divider power consumption can be expressed as
So with traditional pre-divider mutually this, the power consumption of pre-divider provided by the present invention can be according to input frequency self-regulated
Section preferably can save power consumption for system, and improve pre-divider working band width simultaneously.
Further, as shown in Fig. 2, the main latch 1 and described respectively further comprising load regulation signal from latch 2
Input terminalBias current adjustment signal input terminal D<k:0>and a pair of of differential clock signal input terminal CLK,
CLKN；Main latch 1 further includes a pair of of differential data input terminal MD, MDN and a pair of of difference output end MQ, MQN, from latch 1
It further include a pair of of differential data input terminal D, DN and a pair of of difference output end Q, QN.
In main latch 1, it is described load to 21 respectively with the load regulation signal input partIt is described
Differential Input connects pipe 23, the pair of difference output end MQ, MQN；The Differential Input to pipe 23 respectively with it is the pair of
Differential data input terminal MD, MDN, the pair of difference output end MQ, MQN, clock input connect pipe 25；The output
Pipe 24 respectively connect pipe 25 with the pair of difference output end MQ, MQN, clock input；The clock input is to pipe
25 connect with the pair of differential clock signal input terminal CLK, CLKN, the biasing circuit 26 respectively；
From latch 2, the load to 22 respectively with the load regulation signal input partIt is described
Differential Input connects pipe 27, the pair of difference output end MQ, MQN；The Differential Input to pipe 27 respectively with it is the pair of
Differential data input terminal D, DN, the pair of difference output end Q, QN, clock input connect pipe 29；The output is to pipe
28 respectively connect pipe 29 with the pair of difference output end Q, QN, clock input；Pipe 29 is distinguished in the clock input
It is connect with the pair of differential clock signal input terminal CLK, CLKN, the biasing circuit 30.
In addition, a pair of of difference output end MQ, MQN of the main latch 1 are just connecing a pair of of difference number from latch 2
According to input terminal D, DN, a pair of of differential data that the main latch 1 is reversely connected from a pair of of difference output end Q, QN of latch 2
Input terminal MD, MDN.
Specifically, differential data input terminal D of the difference output end MQ connection of main latch 1 from latch 2, main latch
Differential data input terminal DN of the 1 difference output end MQN connection from latch 2；It is led from the difference output end Q connection of latch 2
The differential data input terminal MDN of latch 1, from the differential data input of the difference output end QN connection main latch 1 of latch 2
Hold MD.
Further, as shown in Figures 2 and 4, the load of main latch 1 includes identical first load circuit 41 of structure to 21
With the second load circuit 42, first load circuit 41 and second load circuit 42 respectively include resistance Rc and k+1
Load branch in parallel, k >=-1；The resistance Rc is in parallel with each load branch；
Each load branch includes a metal-oxide-semiconductor Qc_i and a resistive load Rc_i；The load regulation signal is defeated
Entering end has k+1 terminal, and any terminal is set asWherein, i=0,1 ..., k.
In each load branch of main latch, the source electrode of the metal-oxide-semiconductor Qc_i connects power supply Vdd, the metal-oxide-semiconductor
The grid of Qc_i connects the terminal of the load regulation signal input partThe drain electrode connection of the metal-oxide-semiconductor Qc_i is described resistive
One end of Rc_i is loaded, the other end of the resistive load Rc_i connects the Differential Input to pipe 43；
The other end of resistive load Rc_i in first load circuit 41 is also connected with the difference output end of main latch 1
The other end of MQN, the resistive load Rc_i in second load circuit 42 are also connected with the difference output end MQ of main latch 1.
It should be noted that the resistance Rc in the first load circuit 41 and the second load circuit 42 is not connected to switching tube to protect
It holds and always exists electric current in main latch, reduce delay time when mode conversion.Metal-oxide-semiconductor Qc_i's in each load branch
Grid is separately connected load regulation signal input partPayload size is adjusted with input load adjustment signal.
Further, as shown in figure 4, the biasing circuit 26 of main latch 1 includes the 7th transistor T7 and impedance network；
The collector of the 7th transistor T7 connects the clock and inputs to pipe 25, the base stage of the 7th transistor T7
Bias voltage Vbs is connected, the emitter of the 7th transistor T7 connects the impedance network；
The impedance network includes resistance Rd and k+1 bigoted branch in parallel；The resistance Rd and each bigoted branch
It is in parallel；
Each bigoted branch includes a metal-oxide-semiconductor Qd_i and a resistive load Rd_i；The bias current adjusts letter
Number input terminal has k+1 terminal, and any terminal is set as Di；Wherein, i=0,1 ..., k.
In each bigoted branch, one end of the resistive load Rd_i connects the emitter of the 7th transistor T7,
The other end of the resistive load Rd_i connects the drain electrode of the metal-oxide-semiconductor Rd_i, and the source electrode ground connection of the metal-oxide-semiconductor Rd_i is described
The grid of metal-oxide-semiconductor Rd_i connects the terminal Di of the bias current adjustment signal input terminal.
It should be noted that the resistance Rd in impedance network, which does not connect switching tube, always exists electric current with holding circuit, reduce
The delay time of pattern switching.It is defeated that the grid of metal-oxide-semiconductor Rd_i in each bigoted branch is separately connected bias current adjustment signal
Enter to hold D < k:0 >, bias current size is adjusted with input bias current adjustment signal.
Further, as shown in figure 4, the Differential Input of main latch 1 includes the first transistor T1 and second brilliant to pipe 23
Body pipe T2；
The difference output end MQN, the second transistor T2 of the collector connection main latch 1 of the first transistor T1
Collector connection main latch 1 difference output end MQ；The difference of the base stage connection main latch 1 of the first transistor T1
The differential data input terminal DN of the base stage connection main latch 1 of data input pin D, the second transistor T2；Described first is brilliant
The emitter of the emitter of body pipe T1 and the second transistor T2 are separately connected the clock input to pipe 25.
Further, as shown in figure 4, the output of each latch is cross-coupling output to pipe, main latch 1 to pipe
Cross-coupling output to pipe 24 include third transistor T3 and the 4th transistor T4；
The difference output end MQN, the 4th transistor T4 of the collector connection main latch 1 of the third transistor T3
Collector connection main latch 1 difference output end MQ；The emitter of the third transistor T3 and the 4th transistor
The emitter of T4 is separately connected the clock input to pipe 25；The base stage of the third transistor T3 connects the 4th transistor
The base stage of the collector of T4, the 4th transistor T4 connects the collector of the third transistor T3.
Further, as shown in figure 4, the clock input of main latch 1 includes the 5th transistor T5 and the 6th brilliant to pipe 25
Body pipe T6；
The collector of the 5th transistor T5 is separately connected the emitter of the first transistor T1, second crystal
The emitter of pipe T2；The collector of the 6th transistor T6 is separately connected the emitter of the third transistor T3, described
The emitter of four transistor T4；The base stage of the 5th transistor T5 connects differential clock signal input terminal CLKN, and the described 6th
The base stage of transistor T6 connects differential clock signal input terminal CLK；The emitter of the 5th transistor T5 and the 6th crystalline substance
The emitter of body pipe T6 is separately connected the collector of the 7th transistor T7.
It should be noted that differential clock signal input terminal CLKN and differential clock signal input terminal CLK input phase phase
Anti- same frequency clock.
Similarly, as shown in figure 4, including identical first load circuit 47 of structure and the to 22 from the load of latch 2
Two load circuits 48, first load circuit 47 and second load circuit 48 respectively include resistance Rs and k+1 in parallel
Load branch, k >=-1；The resistance Rs is in parallel with each load branch；
Each load branch includes a metal-oxide-semiconductor Qs_i and a resistive load Rs_i；The load regulation signal is defeated
Entering end has k+1 terminal, and any terminal is set asWherein, i=0,1 ..., k.
In each load branch from latch, the source electrode of the metal-oxide-semiconductor Qs_i connects power supply Vdd, the metal-oxide-semiconductor
The grid of Qs_i connects the load regulation signal input partThe drain electrode of the metal-oxide-semiconductor Qs_i connects the resistive load Rs_
One end of i, the other end of the resistive load Rs_i connect the Differential Input to pipe 49；
The other end of resistive load Rs_i in first load circuit 47 is also connected with the difference output end from latch 2
The other end of Q, the resistive load Rs_i in second load circuit 48 are also connected with the difference output end QN from latch 2.
It should be noted that the resistance Rs in the first load circuit 47 and the second load circuit 48 is not connected to switching tube to protect
It holds and always exists electric current from latch, reduce delay time when mode conversion.Metal-oxide-semiconductor Qs_i's in each load branch
Grid is separately connected load regulation signal input partPayload size is adjusted with input load adjustment signal.
It similarly, include the 7th transistor T14 and impedance network from the biasing circuit 30 of latch 2；
The collector of the 7th transistor T14 connects the clock and inputs to pipe 29, the base of the 7th transistor T14
Pole connects bias voltage Vbs, and the emitter of the 7th transistor T14 connects the impedance network；
The impedance network includes resistance Re and k+1 bigoted branch in parallel；The resistance Re and each bigoted branch
It is in parallel；
Each bigoted branch includes a metal-oxide-semiconductor Qe_i and a resistive load Re_i；The bias current adjusts letter
Number input terminal has k+1 terminal, and any terminal is set as Di；Wherein, i=0,1 ..., k.
In each bigoted branch, one end of the resistive load Re_i connects the emitter of the 7th transistor T14,
The other end of the resistive load Re_i connects the drain electrode of the metal-oxide-semiconductor Re_i, and the source electrode ground connection of the metal-oxide-semiconductor Re_i is described
The grid of metal-oxide-semiconductor Re_i connects the terminal Di of the bias current adjustment signal input terminal.
It should be noted that the resistance Re in impedance network, which does not connect switching tube, always exists electric current with holding circuit, reduce
The delay time of pattern switching.It is defeated that the grid of metal-oxide-semiconductor Re_i in each bigoted branch is separately connected bias current adjustment signal
Enter to hold D < k:0 >, bias current size is adjusted with input bias current adjustment signal.
It similarly, include the first transistor T8 and second transistor T9 to pipe 27 from the Differential Input of latch 2；
The collector of the first transistor T8 connects the difference output end Q from latch 2, the second transistor T9's
Collector connects the difference output end QN from latch 2；Difference number of the base stage connection of the first transistor T8 from latch 2
According to input terminal DN, the base stage of the second transistor T9 connects the differential data input terminal D from latch 2；The first crystal
The emitter of the emitter of pipe T8 and the second transistor T9 are separately connected the clock input to pipe 27.
Similarly, exporting from the cross-coupling of latch 2 to pipe 28 includes third transistor T11 and the 4th transistor T12；
Difference output end Q, the fourth transistor T12 of the collector connection of the third transistor T11 from latch 2
Collector connection from the difference output end QN of latch 2；The emitter of the third transistor T11 and the 4th transistor
The emitter of T12 is separately connected the clock input to pipe 29；The base stage of the third transistor T11 connects the 4th crystal
The base stage of the collector of pipe T12, the 4th transistor T12 connects the collector of the third transistor T11.
Similarly, inputting from the clock of latch 2 to pipe 29 includes the 5th transistor T10 and the 6th transistor T13；
The collector of the 5th transistor T10 is separately connected the emitter of the first transistor T8, second crystalline substance
The emitter of body pipe T9；The collector of the 6th transistor T13 is separately connected the emitter of the third transistor T11, institute
State the emitter of the 4th transistor T12；The base stage of the 5th transistor T10 connects differential clock signal input terminal CLK, described
The base stage of 6th transistor T13 connects differential clock signal input terminal CLKN；The emitter of the 5th transistor T10 and described
The emitter of 6th transistor T13 is separately connected the collector of the 7th transistor T14.
It should be noted that differential clock signal input terminal CLKN and differential clock signal input terminal CLK input phase phase
Anti- same frequency clock.
Preferably, main latch and from the metal-oxide-semiconductor of the load branch in latch be PMOS tube, main latch and from lock
The metal-oxide-semiconductor of bigoted branch in storage is NMOS tube；
The load regulation signal and the bias current adjustment signal input terminal of the load regulation signal input part input
The bias current adjustment signal reverse phase of input.
The adaptive broadband pre-divider of power consumption provided in an embodiment of the present invention can be set according to the size of input frequency
It sets load regulation signal and bigoted current regulating signal and is input in two latch, make two latch according to load regulation
Signal Regulation payload size adjusts bigoted size of current according to bigoted current regulating signal, to reach adjustment circuit delay
Purpose, and then circuit power consumption is saved, improve pre-divider working band width.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (9)
1. a kind of broadband pre-divider that power consumption is adaptive, which is characterized in that including main latch and from latch；The main lock
Storage and described feedback loop is connected and composed from latch；
The main latch and described input load adjustment signal and bias current adjustment signal, and root are respectively used to from latch
According to the load regulation Signal Regulation payload size, bias current size is adjusted according to the bias current adjustment signal, with root
According to the work status after adjusting；
Wherein, the load regulation signal and bias current adjustment signal are arranged according to the size of input frequency.
2. the adaptive broadband pre-divider of power consumption as described in claim 1, which is characterized in that the main latch and described
From latch respectively include load to, Differential Input to pipe, clock input to pipe, output to pipe and biasing circuit；
The load is to for the payload size according to latch where the load regulation Signal Regulation；
The bias current size of latch where the biasing circuit is used to be adjusted according to the bias current adjustment signal；
The clock input is used for input clock signal to pipe；
The Differential Input is used to amplify the difference of the frequency signal of input to pipe；
The output is used to pipe carry out shaping output to the signal of amplification.
3. the adaptive broadband pre-divider of power consumption as claimed in claim 2, which is characterized in that the main latch and described
Load regulation signal input part, bias current adjustment signal input terminal, a pair of of differential data input are respectively further comprised from latch
End, a pair of of differential clock signal input terminal and a pair of of difference output end；
In each latch, the load is to respectively with the load regulation signal input part, the Differential Input to pipe, institute
State a pair of of difference output end connection；The Differential Input to pipe respectively with the pair of differential data input terminal, the pair of difference
Output end, clock input is divided to connect pipe；The output is defeated with the pair of difference output end, the clock respectively to pipe
Enter and pipe is connected；The clock input connect pipe with the pair of differential clock signal input terminal, the biasing circuit respectively；
A pair of of difference output of the main latch, which is rectified, connects a pair of of differential data input terminal from latch, described from lock
A pair of of difference output end of storage is reversely connected a pair of of differential data input terminal of the main latch.
4. the adaptive broadband pre-divider of power consumption as claimed in claim 3, which is characterized in that the load pair of each latch
It include the first load circuit and the second load circuit, first load circuit and second load circuit respectively include the
One resistance and k+1 load branch in parallel, k >=-1；The first resistor is in parallel with each load branch；
Each load branch includes a metal-oxide-semiconductor and a resistive load；
In each load branch, the source electrode of the metal-oxide-semiconductor connects power supply, and the grid of the metal-oxide-semiconductor connects the load regulation
Signal input part, draining for the metal-oxide-semiconductor connect one end of the resistive load, described in the other end connection of the resistive load
Differential Input is to pipe；
The other end of resistive load in first load circuit and the resistive load in second load circuit it is another
End is also correspondingly connected with a pair of of difference output end of place latch respectively.
5. the adaptive broadband pre-divider of power consumption as claimed in claim 4, which is characterized in that the biased electrical of each latch
Road includes the 7th transistor and impedance network；
The collector of 7th transistor connects the clock input to pipe, and the base stage of the 7th transistor connects bigoted electricity
The emitter of pressure, the 7th transistor connects the impedance network；
The impedance network includes 3rd resistor and k+1 bigoted branch in parallel；The 3rd resistor and each bigoted branch
It is in parallel；
Each bigoted branch includes a metal-oxide-semiconductor and a resistive load；
In each bigoted branch, one end of the resistive load connects the emitter of the 7th transistor, described resistive negative
The other end of load connects the drain electrode of the metal-oxide-semiconductor, the source electrode ground connection of the metal-oxide-semiconductor, and the grid of the metal-oxide-semiconductor connects the biasing
Current regulating signal input terminal.
6. the adaptive broadband pre-divider of power consumption as claimed in claim 5, which is characterized in that the difference of each latch is defeated
Entering to Guan Jun includes the first transistor and second transistor；
The collector of the collector of the first transistor and the second transistor a pair of of difference with place latch respectively
Output end is correspondingly connected with；The base stage of the first transistor and the base stage of the second transistor respectively with place latch one
Differential data input terminal is correspondingly connected with；The emitter of the emitter of the first transistor and the second transistor connects respectively
The clock input is connect to pipe.
7. the adaptive broadband pre-divider of power consumption as claimed in claim 6, which is characterized in that the output pair of each latch
Pipe is cross-coupling output to pipe, and each cross-coupling output includes third transistor and the 4th transistor to Guan Jun；
The collector of the collector of the third transistor and the 4th transistor respectively with a pair of of difference of place latch
Output end is correspondingly connected with；The emitter of the emitter of the third transistor and the 4th transistor is separately connected the clock
Input is to pipe；The base stage of the third transistor connects the collector of the 4th transistor, the base stage of the 4th transistor
Connect the collector of the third transistor.
8. the adaptive broadband pre-divider of power consumption as claimed in claim 7, which is characterized in that the clock of each latch is defeated
Entering to Guan Jun includes the 5th transistor and the 6th transistor；
The collector of 5th transistor is separately connected the transmitting of the emitter, the second transistor of the first transistor
Pole；The collector of 6th transistor is separately connected the transmitting of the emitter, the 4th transistor of the third transistor
Pole；The base stage of 5th transistor and the base stage of the 6th transistor are believed with a pair of of differential clocks of place latch respectively
Number input terminal is correspondingly connected with；The emitter of the emitter of 5th transistor and the 6th transistor is separately connected described
The collector of seven transistors.
9. the adaptive broadband pre-divider of power consumption as claimed in claim 5, which is characterized in that in the load branch
Metal-oxide-semiconductor is PMOS tube, and the metal-oxide-semiconductor in the bigoted branch is NMOS tube；
The load regulation signal and the bias current adjustment signal input terminal of the load regulation signal input part input input
Bias current adjustment signal reverse phase.
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