CN102291132A - Current-mode-logic-based high speed high-oscillation amplitude divide-by-two frequency divider circuit - Google Patents
Current-mode-logic-based high speed high-oscillation amplitude divide-by-two frequency divider circuit Download PDFInfo
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Abstract
The invention discloses a high speed high-oscillation amplitude divide-by-two frequency divider circuit, which belongs to the technical fields of integrated circuit designing and signal processing. Specifically, the circuit mainly comprises two high speed high-oscillation amplitude D triggers which are cascaded. The D trigger of each stage eliminates the bias of a tail current source based on the conventional D trigger having a current-mode logic (CML) structure, and adopts a P-channel metal oxide semiconductor (PMOS) transistor as a load; and simultaneously, a PMOS and N-channel metal oxide semiconductor (NMOS) complementary cross coupling pair structure and the like are adopted by the output stage of the circuit to finally achieve the aims of increasing the oscillation amplitude of an output signal and making the oscillation amplitude of the output signal approximate to full oscillation amplitude under the condition of ensuring the high speed working of the circuit. The circuit not only can directly drive a post circuit, reduces system power consumption to a certain extent, compensates for the shortcomings of a conventional divide-by-two frequency divider, and is suitable for a high speed frequency divider part in a low-power consumption preposed dual-mode prescaler front-end without any additional level conversion amplification circuit.
Description
Technical field
The invention belongs to integrated circuit (IC) design and signal processing technology field, be specifically related to a kind of 2.5GHz-5.5GHz of working in, remove the two-divider circuit, be mainly used in the frequency synthesizer of hyperfrequency wireless communication system based on the high speed long arc of current mode logic.
Background technology
In recent years, under the promotion that IC industry develops rapidly, variation with rapid changepl. never-ending changes and improvements is taking place in wireless communication technology.What wireless communication technology was a large amount of is applied to such as mobile phone, WLAN (WLAN), super high frequency radio frequency identification (UHF RFID), global positioning system aspects such as (GPS), and various standard agreement and technical application level go out not poor.Wireless communication system is also more and more faster to transmission rate thereupon, and security performance is more and more higher, and the direction that reliability is become better and better develops.Frequency synthesizer has been obtained sufficient development as the pith of wireless communication system front end in recent years, be more widely used method and constitute frequency synthesizer with phase-locked loop (PLL) at present.
In phase-locked loop frequency integrator, frequency divider is positioned at the feedback fraction of whole cyclic system, also is one of module that is operated in highest frequency, and its performance often has decisive influence to systematic function.Because the output of voltage controlled oscillator directly inserts frequency divider, so be operated in the preposition dual-modulus prescaler of highest frequency, its power consumption accounts for the major part of whole frequency synthesizer power consumption.Along with the continuous rising of Modern Communication System operating frequency, its power consumption also sharply increases.In this case, the design difficulty of preposition dual-modulus prescaler is very high in the frequency divider, and becomes the bottleneck of whole system speed and optimised power consumption.At present, be positioned at dual-modulus prescaler high speed foremost and remove two-divider, adopt the high speed d type flip flop of current mode logic (CML) to realize mostly.Shown in the accompanying drawing 1 is the circuit diagram of this traditional C ML structure d type flip flop.Its comprises sampling and latchs two stages when working, its operation principle mainly is to switch by switch, carries out current delivery, thereby realizes difference output.Because the differential pair structure of CML is equivalent to a switch, differential signal only need be higher than the threshold voltage of metal-oxide-semiconductor just can open metal-oxide-semiconductor, so differential signal only needs less voltage swing just can finish function, and power consumption is relatively low, and operating rate is also very fast.Simultaneously,, therefore have better common-mode noise suppression characteristic, have stronger antijamming capability with respect to single-ended cmos circuit because circuit has adopted differential configuration.But the characteristics that traditional C ML structure d type flip flop voltage swing is less relatively, can not reach full swing also make and bring extra circuit overhead in actual applications.Shown in the accompanying drawing 2 is that a typical phase place is switched high speed dual-modulus prescaler circuit block diagram.The preceding two-stage of circuit is removed two-divider by two of cascade and is formed, if they all adopt the CML structure, then Half Speed can be less except that the output voltage swing of two-divider, it just can not switch four with phase place and select a data selector directly to link to each other, and at this moment just need remove two-divider and phase place in Half Speed and switch four and select and add CML-CMOS level shifting circuit between the data selector.Final this can make whole dual-mode frequency divider produce certain extra power consumption and take more chip area.
In sum, design a kind of have high speed, long arc, a low-power consumption for the lifting of whole preposition dual-modulus prescaler performance significant meaning is arranged except that the two-divider circuit.
Summary of the invention
The objective of the invention is to design a kind of high speed long arc and remove the two-divider circuit based on current mode logic, should remove the two-divider circuit not only can be operated under the very high velocity conditions, and has an advantage of low noise, high anti-jamming capacity, simultaneously can also directly drive late-class circuit and needn't add the amplifying circuit of level conversion again, reduce system power dissipation to a certain extent, remedied the deficiency of removing two-divider that traditional C ML structure d type flip flop constitutes.
In order to solve the technical problem of above-mentioned traditional C ML structure d type flip flop, the present invention adopts following technical scheme.It is on the traditional C ML structure d type flip flop basis shown in the accompanying drawing 1 that described high speed long arc is removed the two-divider circuit, remove the tail current source biasing, and make clock to the direct ground connection of the source electrode of pipe, thereby a part of overdrive voltage of having avoided tail current source to consume makes the power consumption of system also less relatively.Adopt the PMOS pipe to replace ohmic load commonly used simultaneously, and with the direct ground connection of its grid, the PMOS plumber is done at linear zone, because these PMOS active loads impedance difference under the different operating state of d type flip flop, thereby can make the propagation delay time constant of system less, improve the operating rate of entire circuit, and obtained bigger output voltage swing.Adopt PMOS and the coupling of NMOS complementary chiasma to replace simple NMOS coupling to structure again in the circuit output stage, thereby under the condition that guarantees the circuit high speed operation, further improved the amplitude of oscillation of output signal and reached approximate full swing structure.
Concrete technical scheme of the present invention is:
A kind of high speed long arc is removed the two-divider circuit, mainly is made of the cascade of two high speed long arc d type flip flops, and the described two-divider circuit that removes includes power positive end VDD, power supply negative terminal GND, dc offset voltage input port V
BIAS, remove two-divider difference positive clock signal input terminal mouth V
CLK, remove two-divider difference negative clock signal input terminal mouth
, remove two-divider I road difference positive fractional frequency signal output port V
I0, remove two-divider I road difference negative fractional frequency signal output port V
I180, remove two-divider Q road difference positive fractional frequency signal output port V
Q90, remove two-divider Q road difference negative fractional frequency signal output port V
Q270The described two-divider circuit that removes also includes first capacitor C 1, second capacitor C 2, first resistance R 1, second resistance R 2, the first d type flip flop D1 and the second d type flip flop D2; Wherein the circuit structure of the first d type flip flop D1 and the second d type flip flop D2 is identical.The first d type flip flop D1 includes positive source signal access port V+, power cathode signal access port V-, d type flip flop difference positive data-signal input port A, d type flip flop difference negative data-signal input port
, d type flip flop difference positive clock signal input terminal mouth CLK, d type flip flop difference negative clock signal input terminal mouth
, d type flip flop difference positive data-signal output port Q, d type flip flop difference negative data-signal output port
The A end of the described first d type flip flop D1 is with the second d type flip flop D2's
End links to each other, the first d type flip flop D1's
End links to each other with the Q end of the second d type flip flop D2; The A end of the Q of the described first d type flip flop D1 end and the second d type flip flop D2 all with except that two-divider I road difference positive fractional frequency signal output port V
I0Link to each other, the first d type flip flop D1's
The end and the second d type flip flop D2's
End all with remove two-divider I road difference negative fractional frequency signal output port V
I180Link to each other, the Q of the second d type flip flop D2 holds and removes two-divider Q road difference positive fractional frequency signal output port V
Q90Link to each other, the second d type flip flop D2's
Hold and remove two-divider Q road difference negative fractional frequency signal output port V
Q270Link to each other; The V+ end of the described first d type flip flop D1 and the V+ end of the second d type flip flop D2 all link to each other with power positive end VDD, and the V-end of the first d type flip flop D1 and the V-end of the second d type flip flop D2 all link to each other with power supply negative terminal GND; The CLK end of the described first d type flip flop D1, the second d type flip flop D2's
End all links to each other with an end of first capacitor C 1 with an end of first resistance R 1, the first d type flip flop D1's
End, the CLK end of the second d type flip flop D2 all links to each other with an end of second capacitor C 2 with an end of second resistance R 2; The other end of first capacitor C 1 with remove two-divider difference positive clock signal input terminal mouth V
CLKLink to each other, the other end of second capacitor C 2 with remove two-divider difference negative clock signal input terminal mouth
Link to each other, the other end of the other end of first resistance R 1 and second resistance R 2 all with dc offset voltage input port V
BIASLink to each other.
Remove in the two-divider circuit in high speed long arc of the present invention, the described first d type flip flop D1 circuit includes the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11 metal-oxide-semiconductor M11, the first metal-oxide-semiconductor M1 among the described first d type flip flop D1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 all are NMOS pipes, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10 and the 11 MOS pipe M11 all are PMOS pipes; The source electrode of the source electrode of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 all links to each other with power cathode signal access port V-, the grid of the first metal-oxide-semiconductor M1 all links to each other with d type flip flop difference positive clock signal input terminal mouth CLK with the grid of the 11 metal-oxide-semiconductor M11, the grid of the second metal-oxide-semiconductor M2 and d type flip flop difference negative clock signal input terminal mouth
Link to each other; The source electrode of the source electrode of the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 all links to each other with the drain electrode of the first metal-oxide-semiconductor M1, the grid of the 3rd metal-oxide-semiconductor M3 links to each other with d type flip flop difference positive data-signal input port A, the grid of the 4th metal-oxide-semiconductor M4 and d type flip flop difference negative data-signal input port
Link to each other; The drain electrode of the drain electrode of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 links to each other with the drain electrode of the 3rd metal-oxide-semiconductor M3 and the drain electrode of the 4th metal-oxide-semiconductor M4 respectively, the source electrode of the source electrode of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 all links to each other with positive source signal access port V+, and the grid of the grid of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 all links to each other with power cathode signal access port V-; The source electrode of the source electrode of the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 all links to each other with the drain electrode of the second metal-oxide-semiconductor M2, the grid of the grid of the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 links to each other with the grid of the 9th metal-oxide-semiconductor M9 and the grid of the tenth metal-oxide-semiconductor M10 respectively, the drain electrode of the drain electrode of the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 links to each other with the drain electrode of the 9th metal-oxide-semiconductor M9 and the drain electrode of the tenth metal-oxide-semiconductor M10 respectively, the source electrode of the source electrode of the 9th metal-oxide-semiconductor M9 and the tenth metal-oxide-semiconductor M10 all links to each other with the drain electrode of the 11 metal-oxide-semiconductor M11, and the source electrode of the 11 metal-oxide-semiconductor M11 links to each other with positive source signal access port V+; The grid of the drain electrode of the drain electrode of the 5th metal-oxide-semiconductor M5, the 9th metal-oxide-semiconductor M9 and the tenth metal-oxide-semiconductor M10 all with d type flip flop difference negative data-signal output port
Link to each other, the drain electrode of the 6th metal-oxide-semiconductor M6, the drain electrode of the grid of the 9th metal-oxide-semiconductor M9 and the tenth metal-oxide-semiconductor M10 all link to each other with d type flip flop difference positive data-signal output port Q.
Compare with the two-divider circuit that removes that traditional C ML structure d type flip flop constitutes, the present invention has obtained following beneficial effect:
1, the two-divider circuit that removes of the present invention can be operated under the hyperfrequency condition, has the advantage of the frequency input range of high speed, low noise, high anti-jamming capacity and broad.
2, the two-divider circuit that removes of the present invention, adopt PMOS pipe active load to replace ohmic load commonly used, adopt PMOS and the coupling of NMOS complementary chiasma to replace simple NMOS coupling to structure again in the circuit output stage to structure, thereby under the condition that guarantees the circuit high speed operation, make the amplitude of oscillation of output signal reach approximate full swing.
3, the two-divider circuit that removes of the present invention, removed the tail current source biasing, a part of overdrive voltage of having avoided tail current source to consume, and can directly drive late-class circuit, greatly reduce the complexity of system design to a certain extent, make the power consumption of system lower, also saved area of chip.
Description of drawings
Fig. 1 is the circuit diagram of traditional C ML structure d type flip flop;
Fig. 2 switches high speed dual-modulus prescaler circuit block diagram for an existing typical phase place;
Fig. 3 is a circuit diagram of the present invention;
Fig. 4 is the circuit diagram of the present invention first d type flip flop D1.
Embodiment
Below; will the present invention is described further by specific embodiment; yet embodiment only is giving an example of alternative embodiment of the present invention, and its disclosed feature only is used for explanation and sets forth technical scheme of the present invention, and is not intended to limit the scope of the invention.
Now describe technical scheme of the present invention in conjunction with the accompanying drawings and embodiments in detail.
Embodiment
Present embodiment has and the identical circuit structure of circuit shown in the accompanying drawing 3,4, and the components and parts of present embodiment and circuit parameter are enumerated as follows:
The capacitance of first capacitor C 1, second capacitor C 2 is respectively: 2.45544pF, 2.45544pF.
The resistance of first resistance R 1, second resistance R 2 is respectively: 1.13398 K Ω, 1.13398 K Ω.
The breadth length ratio size (W/L) of the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10 and the 11 metal-oxide-semiconductor M11 is respectively: 140um/0.2um, 140um/0.2um, 9um/0.18um, 9um/0.18um, 8.2um/0.18um, 8.2um/0.18um, 9um/0.18um, 9um/0.18um, 18um/0.18um, 18um/0.18um, 280um/0.2um.
Components and parts and the circuit parameter of the second d type flip flop D2 and the first d type flip flop D1 are in full accord.
The power positive end vdd voltage is: 1.8V, power supply negative terminal (GND) is: 0V.
Dc offset voltage input port V
BIASInput voltage be: 0.572V.
Remove two-divider difference positive clock signal input terminal mouth V
CLKWith remove two-divider difference negative clock signal input terminal mouth
The input clock signal frequency range be: 2.5GHz-5.5GHz, DC potential is: 0.9V, the peak-to-peak value of signal amplitude is: 1.8V.Wherein remove two-divider difference positive clock signal input terminal mouth V
CLKThe input clock signal initial phase be 0 degree, remove two-divider difference negative clock signal input terminal mouth
The input clock signal initial phase be 180 the degree.
Describe the course of work of the present invention below in detail:
Consult Fig. 3, Fig. 4, do not have clock signal input (V at circuit
CLKWith
Be 0) time, the direct grid current bias voltage of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 equals dc offset voltage input port V
BIASInput voltage.When high frequency clock signal is imported, because two clock signal input terminals have adopted first capacitor C 1 respectively, 2 two capacitances of second capacitor C, so the flip-flop in the input high frequency clock signal is by filtering, and alternating component is added on the direct grid current bias voltage of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2.Simultaneously, because first resistance R 1 and second resistance R 2 have all adopted big resistance, so these high-frequency ac compositions also can't be transferred to dc offset voltage input port V by them
BIASThereby, for the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 provide metastable direct grid current bias voltage.The 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 have formed one group of differential pair tube, can improve except that the inhibition ability of two-divider circuit to common-mode noise.Owing to should not design the bigger resistance of resistance in the CMOS technology, so all direct ground connection of the grid of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 has replaced ohmic load commonly used, and form two active loads that sectional area is less relatively, this two active loads impedance under the different conditions of circuit working is also inequality, thereby both improved the operating rate of entire circuit, can obtain bigger output voltage swing again.The 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 have formed the coupling of NMOS complementary chiasma to pipe, the 9th metal-oxide-semiconductor M9 and the tenth metal-oxide-semiconductor M10 have formed the coupling of PMOS complementary chiasma to pipe, the circuit output stage adopts these two groups of complementary chiasma couplings to replace NMOS complementary chiasma coupling simple in the traditional structure to pipe to pipe simultaneously, can strengthen the positive feedback effect of output-stage circuit, thereby under the condition that guarantees the circuit high speed operation, further improved the amplitude of oscillation of output signal and reached approximate full swing.
For the first trigger D1 or the second trigger D2, comprise during its work the sampling and latch two stages.When d type flip flop difference positive clock signal input terminal mouth CLK is effective high level, the first metal-oxide-semiconductor M1 opens, its bias current flows through from the 3rd metal-oxide-semiconductor M3 or the 4th metal-oxide-semiconductor M4 place branch road fully, the input transfer of data of d type flip flop difference positive data-signal input port A is to d type flip flop difference positive data-signal output port Q, d type flip flop difference negative data-signal input port
The input transfer of data to d type flip flop difference negative data-signal output port
Thereby, realize sampling process; Simultaneously, because d type flip flop difference negative clock signal input terminal mouth
Be invalid low level, the second metal-oxide-semiconductor M2 turn-offs, so in the sampling process, the complementary chiasma coupling is closed pipe and inoperative.When d type flip flop difference positive clock signal input terminal mouth CLK was invalid low level, the first metal-oxide-semiconductor M1 turn-offed input difference is closed pipe and inoperative; Simultaneously, because d type flip flop difference negative clock signal input terminal mouth
Be effective high level, the second metal-oxide-semiconductor M2 opens, its bias current flows through the dateout of d type flip flop difference positive data-signal output port Q and d type flip flop difference negative data-signal output port from NMOS, the coupling of PMOS complementary chiasma to a branch road of each group the pipe fully
Dateout be held by the positive feedback effect of NMOS, PMOS complementary chiasma coupling pipe, thereby realize the process that latchs.
For the whole two-divider circuit that removes, it is to be made of the hypotactic first d type flip flop D1 and the second trigger D2 cascade.When removing two-divider difference positive clock signal input terminal mouth V
CLKDuring for high level, the first d type flip flop D1 enters sample phase, and the second trigger D2 enters latch stage.Like this, the d type flip flop difference negative data-signal output port of the second trigger D2
Dateout constant owing to keep latch mode, and, after first trigger D1 sampling, directly be transferred to the d type flip flop difference positive data-signal output port Q of the first trigger D1 simultaneously as the input data of the d type flip flop difference positive data-signal input port A of the first d type flip flop D1; The d type flip flop difference negative data-signal output port of the d type flip flop difference positive data-signal output port Q of the second trigger D2 and the second trigger D2
The working condition of dateout similar.When removing two-divider difference positive clock signal input terminal mouth V
CLKDuring for low level, the first d type flip flop D1 enters latch stage, and the second trigger D2 enters sample phase.The dateout of the d type flip flop difference positive data-signal output port Q of the first d type flip flop D1 is still constant owing to keep latch mode, and, after second trigger D2 sampling, directly be transferred to the d type flip flop difference positive data-signal output port Q of the second trigger D2 simultaneously as the input data of the d type flip flop difference positive data-signal input port A of the second d type flip flop D2; The d type flip flop difference negative data-signal output port of the first trigger D1
Similar with the working condition of the dateout of the d type flip flop difference positive data-signal output port Q of the first trigger D1.
Foregoing is exemplifying of specific embodiments of the invention, for the wherein not equipment of detailed description and structure, should be understood to take existing common apparatus in this area and universal method to be implemented.
Claims (3)
1. the high speed long arc based on current mode logic is removed the two-divider circuit, it is characterized in that this circuit includes power positive end (VDD), power supply negative terminal (GND), dc offset voltage input port (V
BIAS), remove two-divider difference positive clock signal input terminal mouth (V
CLK), remove two-divider difference negative clock signal input terminal mouth (
), remove two-divider I road difference positive fractional frequency signal output port (V
I0), remove two-divider I road difference negative fractional frequency signal output port (V
I180), remove two-divider Q road difference positive fractional frequency signal output port (V
Q90), remove two-divider Q road difference negative fractional frequency signal output port (V
Q270), described circuit also includes first electric capacity (C1), second electric capacity (C2), first resistance (R1), second resistance (R2), first d type flip flop (D1) and second d type flip flop (D2); Wherein the circuit structure of first d type flip flop (D1) and second d type flip flop (D2) is identical; First d type flip flop (D1) include positive source signal access port (V+), power cathode signal access port (V-), d type flip flop difference positive data-signal input port (A), d type flip flop difference negative data-signal input port (
), d type flip flop difference positive clock signal input terminal mouth (CLK), d type flip flop difference negative clock signal input terminal mouth (
), d type flip flop difference positive data-signal output port (Q), d type flip flop difference negative data-signal output port (
); The A end of described first d type flip flop (D1) and second d type flip flop (D2)
End links to each other, first d type flip flop (D1)
End links to each other with the Q end of second d type flip flop (D2); The A end of the Q of described first d type flip flop (D1) end and second d type flip flop (D2) all with except that two-divider I road difference positive fractional frequency signal output port (V
I0) link to each other, first d type flip flop (D1)
End and second d type flip flop (D2)
End all with remove two-divider I road difference negative fractional frequency signal output port (V
I180) link to each other, the Q of second d type flip flop (D2) holds and removes two-divider Q road difference positive fractional frequency signal output port (V
Q90) link to each other, second d type flip flop (D2)
Hold and remove two-divider Q road difference negative fractional frequency signal output port (V
Q270) link to each other; The V+ end of described first d type flip flop (D1) and the V+ end of second d type flip flop (D2) all link to each other with power positive end (VDD), and the V-end of first d type flip flop (D1) and the V-end of second d type flip flop (D2) all link to each other with power supply negative terminal (GND); The CLK end of described first d type flip flop (D1), second d type flip flop (D2)
End all links to each other with an end of first electric capacity (C1) with an end of first resistance (R1), first d type flip flop (D1)
The CLK end of end, second d type flip flop (D2) all links to each other with an end of second electric capacity (C2) with an end of second resistance (R2); The other end of first electric capacity (C1) with remove two-divider difference positive clock signal input terminal mouth (V
CLK) link to each other, the other end of second electric capacity (C2) with remove two-divider difference negative clock signal input terminal mouth (
) link to each other, the other end of the other end of first resistance (R1) and second resistance (R2) all with dc offset voltage input port (V
BIAS) link to each other.
2. high speed long arc as claimed in claim 1 is removed the two-divider circuit, it is characterized in that described first d type flip flop (D1) circuit includes first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4), the 5th metal-oxide-semiconductor (M5), the 6th metal-oxide-semiconductor (M6), the 7th metal-oxide-semiconductor (M7), the 8th metal-oxide-semiconductor (M8), the 9th metal-oxide-semiconductor (M9), the tenth metal-oxide-semiconductor (M10), the 11 metal-oxide-semiconductor (M11), the source electrode of the source electrode of first metal-oxide-semiconductor (M1) and second metal-oxide-semiconductor (M2) all links to each other with power cathode signal access port (V-), the grid of first metal-oxide-semiconductor (M1) all links to each other with d type flip flop difference positive clock signal input terminal mouth (CLK) with the grid of the 11 metal-oxide-semiconductor (M11), the grid of second metal-oxide-semiconductor (M2) and d type flip flop difference negative clock signal input terminal mouth (
) link to each other; The source electrode of the source electrode of the 3rd metal-oxide-semiconductor (M3) and the 4th metal-oxide-semiconductor (M4) all links to each other with the drain electrode of first metal-oxide-semiconductor (M1), the grid of the 3rd metal-oxide-semiconductor (M3) links to each other with d type flip flop difference positive data-signal input port (A), the grid of the 4th metal-oxide-semiconductor (M4) and d type flip flop difference negative data-signal input port (
) link to each other; The drain electrode of the drain electrode of the 5th metal-oxide-semiconductor (M5) and the 6th metal-oxide-semiconductor (M6) links to each other with the drain electrode of the 3rd metal-oxide-semiconductor (M3) and the drain electrode of the 4th metal-oxide-semiconductor (M4) respectively, the source electrode of the source electrode of the 5th metal-oxide-semiconductor (M5) and the 6th metal-oxide-semiconductor (M6) all links to each other with positive source signal access port (V+), and the grid of the grid of the 5th metal-oxide-semiconductor (M5) and the 6th metal-oxide-semiconductor (M6) all links to each other with power cathode signal access port (V-); The source electrode of the source electrode of the 7th metal-oxide-semiconductor (M7) and the 8th metal-oxide-semiconductor (M8) all links to each other with the drain electrode of second metal-oxide-semiconductor (M2), the grid of the grid of the 7th metal-oxide-semiconductor (M7) and the 8th metal-oxide-semiconductor (M8) links to each other with the grid of the 9th metal-oxide-semiconductor (M9) and the grid of the tenth metal-oxide-semiconductor (M10) respectively, the drain electrode of the drain electrode of the 7th metal-oxide-semiconductor (M7) and the 8th metal-oxide-semiconductor (M8) links to each other with the drain electrode of the 9th metal-oxide-semiconductor (M9) and the drain electrode of the tenth metal-oxide-semiconductor (M10) respectively, the source electrode of the source electrode of the 9th metal-oxide-semiconductor (M9) and the tenth metal-oxide-semiconductor (M10) all links to each other with the drain electrode of the 11 metal-oxide-semiconductor (M11), and the source electrode of the 11 metal-oxide-semiconductor (M11) links to each other with positive source signal access port (V+); The grid of the drain electrode of the drain electrode of the 5th metal-oxide-semiconductor (M5), the 9th metal-oxide-semiconductor (M9) and the tenth metal-oxide-semiconductor (M10) all with d type flip flop difference negative data-signal output port (
) link to each other, the grid of the drain electrode of the 6th metal-oxide-semiconductor (M6), the 9th metal-oxide-semiconductor (M9) all links to each other with d type flip flop difference positive data-signal output port (Q) with the drain electrode of the tenth metal-oxide-semiconductor (M10).
3. high speed long arc as claimed in claim 2 is removed the two-divider circuit, it is characterized in that first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4), the 7th metal-oxide-semiconductor (M7) and the 8th metal-oxide-semiconductor (M8) in described first d type flip flop (D1) is the NMOS pipe; The 5th metal-oxide-semiconductor (M5), the 6th metal-oxide-semiconductor (M6), the 9th metal-oxide-semiconductor (M9), the tenth metal-oxide-semiconductor (M10) and the 11 MOS pipe (M11) are the PMOS pipe.
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| CN 201110154956 CN102291132B (en) | 2011-06-10 | 2011-06-10 | Current-mode-logic-based high speed high-oscillation amplitude divide-by-two frequency divider circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916695A (en) * | 2012-11-02 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | High-speed preposed dual frequency divider circuit and implementing method thereof |
| CN103281071A (en) * | 2013-06-21 | 2013-09-04 | 上海中科高等研究院 | Latch and frequency divider circuit including same |
| CN103532544A (en) * | 2013-09-24 | 2014-01-22 | 南京中科微电子有限公司 | Low-power-consumption divide-by-two frequency divider with gating function |
| CN103825610A (en) * | 2013-11-27 | 2014-05-28 | 无锡芯响电子科技有限公司 | Dividing two frequency divider circuit based on current mirror switch logic |
| CN113381752A (en) * | 2021-06-24 | 2021-09-10 | 成都纳能微电子有限公司 | Half-frequency dividing circuit and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1767391A (en) * | 2005-11-25 | 2006-05-03 | 清华大学 | Frequency divider for 8 phase output in phase switching type pre-divider |
| US20070069810A1 (en) * | 2005-09-23 | 2007-03-29 | Korea Advanced Institute Of Science And Technology. | SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof |
| CN101854173A (en) * | 2010-06-11 | 2010-10-06 | 西安电子科技大学 | InGaP/GaAs HBT (Heterojunction Bipolar Transistor) super-high-speed frequency-halving circuit based on ECL (Emitter-Coupled Logic) |
-
2011
- 2011-06-10 CN CN 201110154956 patent/CN102291132B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070069810A1 (en) * | 2005-09-23 | 2007-03-29 | Korea Advanced Institute Of Science And Technology. | SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof |
| CN1767391A (en) * | 2005-11-25 | 2006-05-03 | 清华大学 | Frequency divider for 8 phase output in phase switching type pre-divider |
| CN101854173A (en) * | 2010-06-11 | 2010-10-06 | 西安电子科技大学 | InGaP/GaAs HBT (Heterojunction Bipolar Transistor) super-high-speed frequency-halving circuit based on ECL (Emitter-Coupled Logic) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916695A (en) * | 2012-11-02 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | High-speed preposed dual frequency divider circuit and implementing method thereof |
| CN102916695B (en) * | 2012-11-02 | 2014-03-12 | 长沙景嘉微电子股份有限公司 | High-speed preposed dual frequency divider circuit and implementing method thereof |
| CN103281071A (en) * | 2013-06-21 | 2013-09-04 | 上海中科高等研究院 | Latch and frequency divider circuit including same |
| CN103281071B (en) * | 2013-06-21 | 2016-04-13 | 中国科学院上海高等研究院 | Latch and comprise the divider circuit of this latch |
| CN103532544A (en) * | 2013-09-24 | 2014-01-22 | 南京中科微电子有限公司 | Low-power-consumption divide-by-two frequency divider with gating function |
| CN103532544B (en) * | 2013-09-24 | 2016-06-01 | 南京中科微电子有限公司 | The low-power consumption of a kind of band gating function is except two-divider |
| CN103825610A (en) * | 2013-11-27 | 2014-05-28 | 无锡芯响电子科技有限公司 | Dividing two frequency divider circuit based on current mirror switch logic |
| CN103825610B (en) * | 2013-11-27 | 2017-01-18 | 无锡芯响电子科技有限公司 | Dividing two frequency divider circuit based on current mirror switch logic |
| CN113381752A (en) * | 2021-06-24 | 2021-09-10 | 成都纳能微电子有限公司 | Half-frequency dividing circuit and method |
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| CN102291132B (en) | 2013-01-23 |
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