CN109660253B - Digital amplitude controlled voltage controlled oscillator - Google Patents
Digital amplitude controlled voltage controlled oscillator Download PDFInfo
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- CN109660253B CN109660253B CN201811309397.7A CN201811309397A CN109660253B CN 109660253 B CN109660253 B CN 109660253B CN 201811309397 A CN201811309397 A CN 201811309397A CN 109660253 B CN109660253 B CN 109660253B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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Abstract
The invention relates to a voltage-controlled oscillator controlled by digital amplitude, which comprises a voltage-controlled oscillation circuit and a digital amplitude control circuit connected with the voltage-controlled oscillation circuit, wherein the digital amplitude control circuit comprises a negative peak value detection module, a comparison module and a logic circuit module, wherein the negative peak value detection module is used for detecting the negative peak value of an input signal; the comparison module is connected with the negative peak value detection module and used for judging whether the negative peak value exceeds the reference voltage range or not and outputting a judgment result, wherein the judgment result comprises that the negative peak value exceeds the reference voltage range and the negative peak value does not exceed the reference voltage range; and the logic circuit module is connected with the comparison module and used for determining whether to output the control signal to adjust the amplitude according to the judgment result, wherein the judgment result indicates that the negative peak value exceeds the reference voltage range, and the control signal is output to adjust the amplitude. The invention reduces the phase noise introduced to the voltage-controlled oscillator by adopting the analog amplitude control circuit by using the digital amplitude control circuit, thereby improving the performance of the voltage-controlled oscillator.
Description
Technical Field
The invention belongs to the field of microwave communication integrated circuits, and particularly relates to a voltage-controlled oscillator controlled by digital amplitude.
Background
With the rapid development of mobile communication technology, it is difficult to obtain a wide continuous spectrum in the gold communication frequency band below 6GHz, which severely restricts the development of the communication industry. In contrast, the frequency spectrum resources of the millimeter wave band are abundant and are not fully developed and utilized at present, so millimeter wave communication will become a research hotspot of 5 th generation mobile communication.
Millimeter wave communication belongs to microwave communication, the wavelength range is 1-10 mm, and the frequency range is 30-300 GHz. Therefore, a Phase-Locked Loop (PLL) applied to the millimeter wave communication technology needs a higher frequency. A typical PLL includes a Phase Frequency Detector (PFD), a Charge Pump (CP), a Low-pass Filter (LF), a Voltage Controlled Oscillator (VCO), and a Frequency divider. Among other things, the VCO plays a key role in output amplitude control in the circuit. To achieve a wider tuning frequency, the capacitance of a parallel capacitor in the VCO circuit is typically varied. However, this method has a certain disadvantage that when the capacitance of the parallel capacitor is large, the output amplitude of the VCO circuit is reduced, and even oscillation cannot be started. In this regard, a conventional solution is to control the output amplitude of the VCO using an analog amplitude control circuit.
However, an operational amplifier is usually introduced into the analog amplitude control circuit, and the operational amplifier introduces phase noise into the VCO circuit, and the introduced phase noise has a great influence on the performance of the VCO circuit.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a digital amplitude control circuit and a voltage controlled oscillator thereof.
An embodiment of the present invention provides a digital amplitude control circuit, including:
negative peak detection module, comparison module, logic circuit module, wherein:
the negative peak value detection module is used for detecting the negative peak value of the input signal;
the comparison module is connected with the negative peak value detection module and used for judging whether the negative peak value exceeds a reference voltage range or not and outputting a judgment result, wherein the judgment result comprises that the negative peak value exceeds the reference voltage range and the negative peak value does not exceed the reference voltage range;
and the logic circuit module is connected with the comparison module and used for determining whether to output a control signal to adjust the amplitude according to the judgment result, wherein the judgment result indicates that the negative peak value does not exceed the reference voltage range and does not need to output the control signal to adjust the amplitude, and the judgment result indicates that the negative peak value exceeds the reference voltage range and outputs the control signal to adjust the amplitude.
In one embodiment of the invention, the comparison module comprises a first comparator and a second comparator, wherein:
a positive input end of the first comparator is connected with a first reference voltage, a negative input end of the first comparator is connected with an output end of the negative peak detection module, and an output end of the first comparator is connected with a first input end of the logic circuit module;
the positive input end of the second comparator is connected with a second reference voltage, the negative input end of the second comparator is connected with the output end of the negative peak detection module, and the output end of the second comparator is connected with the second input end of the logic circuit module.
In one embodiment of the invention, the first comparator is a hysteresis comparator.
In one embodiment of the invention, the second comparator is a hysteresis comparator.
An embodiment of the present invention provides a digital amplitude controlled voltage-controlled oscillator, including a digital amplitude control circuit as in any of the above embodiments.
The embodiment of the invention provides a voltage-controlled oscillator for digital amplitude control, which also comprises a voltage-controlled oscillating circuit connected with the digital amplitude control circuit; the voltage-controlled oscillation circuit comprises a constant current source I D First resistance R 1 A second resistance R 2 Third resistor R 3 Fourth resistor R 4 Fifth resistor R 5 First inductance L 1 Second inductance L 2 First capacitor C 1 A second capacitor C 2 Third capacitor C 3 Fourth capacitor C 4 First transistor N 1 Second transistor N 2 A third transistor N 3 Fourth transistor N 4 Fifth transistor N 5 The sixth transistor N 6 The seventh transistor N 7 The eighth transistor N 8 First switch S 1 A second switch S 2 Third switch S 3 Fourth switch S 4 Wherein, in the step (A),
a power supply VDD and the constant current source I D Of the first inductor L 1 One terminal of the second inductor L 2 Is connected to one end of the first inductor L 1 And the other end of the first capacitor C 1 One terminal of the first transistor N 1 The drain of the first inductor L is connected with the drain of the second inductor L 2 And the other end of the first capacitor C 2 Of the second transistor N 2 Is connected to the drain of the first capacitor C 1 And the other end of the second transistor N 2 The gate of (1), the fifth resistor R 5 Is connected to said second capacitor C 2 And the other end of the first transistor N 1 The fourth resistor R 4 Is connected to the fourth resistor R 4 And the other end of the first resistor R 1 One terminal of said third capacitor C 3 Is connected to the fifth resistor R 5 Is connected to the other end of the first resistor R 1 And a terminal of the third capacitor C 3 Is connected to the first transistor N 1 And the second transistor N 2 OfElectrode, the fourth transistor N 4 Drain electrode of (1), the first switch S 1 First terminal of, the second switch S 2 The first terminal of (1), the third switch S 3 First terminal of, the fourth switch S 4 Is connected to the first terminal of the second transistor N, the second transistor N 2 And the first switch S 1 First terminal of, the second switch S 2 The first terminal of (1), the third switch S 3 The first terminal of (1), the fourth switch S 4 Is connected to the first terminal of the first switch S 1 And the second terminal of the fifth transistor N 5 The drain of the second switch S 2 And the sixth transistor N 6 Drain electrode of (b), the third switch S 3 And the seventh transistor N 7 Of the fourth switch S, the fourth switch S 4 And the eighth transistor N 8 Of said fourth transistor N, said fourth transistor N 4 The gate of the fifth transistor N 5 The gate of the sixth transistor N 6 Gate of (2), the seventh transistor N 7 The eighth transistor N 8 The grid electrodes of the fourth transistors N are sequentially connected in series 4 And the fourth capacitor C 4 One end of the third resistor R 3 Is connected to the third resistor R 3 And the other end of the second resistor R 2 One terminal of the third transistor N 3 The third transistor N 3 The drain of the first resistor R, the second resistor R 2 And the other end of the first resistor R 1 The other end of (1), the constant current source I D Is connected to the output terminal of the third capacitor C 3 Another terminal of the fourth capacitor C 4 The other end of (b), the third transistor N 3 Source electrode of, the fourth transistor N 4 Source of (b), the fifth transistor N 5 Source electrode of the sixth transistor N 6 Source electrode of the seventh transistor N 7 Source of (b), the eighth transistor N 8 All sources of (a) are grounded.
In one embodiment of the invention, the first electrodeFeeling L 1 The first capacitor C 1 The first transistor N 1 The connection point of the drain electrode is connected with the first input end of the negative peak detection module, and the second inductor L 2 The second capacitor C 2 The second transistor N 2 And the connection point of the drain electrode is connected with the second input end of the negative peak value detection module.
In an embodiment of the present invention, the first control signal output terminal of the logic circuit module and the first switch S 1 Is connected to the first terminal of the first switch, a second control signal output terminal of the logic circuit module is connected to the second switch S 2 Is connected to the first terminal of the first switch, and the third control signal output terminal of the logic circuit module is connected to the third switch S 3 Is connected to the fourth switch S, a fourth control signal output terminal of the logic circuit module is connected to the fourth switch S 4 Is connected.
In one embodiment of the present invention, the fifth transistor N 5 The sixth transistor N 6 The seventh transistor N 7 The eighth transistor N 8 The process size ratio is 8.
In one embodiment of the present invention, the first transistor N 1 The second transistor N 2 The third transistor N 3 The fourth transistor N 4 The fifth transistor N 5 The sixth transistor N 6 The seventh transistor N 7 The eighth transistor N 8 Are all N-type MOS tubes.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention reduces the phase noise introduced to the voltage-controlled oscillator by adopting the analog amplitude control circuit by using the digital amplitude control circuit, thereby improving the performance of the voltage-controlled oscillator.
2. The digital amplitude control circuit is integrated in the voltage-controlled oscillation circuit, and a control signal is not required to be introduced through an external chip, so that the amplitude of the voltage-controlled oscillation circuit is controlled, and the circuit design is simple.
3. The invention controls the bias current of the voltage-controlled oscillation circuit by using the digital amplitude control circuit, so that the amplitude of the voltage-controlled oscillation circuit can be kept in a certain range.
4. The invention ensures the voltage-controlled oscillation circuit amplitude of the voltage-controlled oscillator under different temperatures and different process characteristics by using the digital amplitude control circuit, thereby widening the tuning frequency of the voltage-controlled oscillator.
5. The invention filters the high-frequency noise in the circuit and improves the performance of the high-frequency phase noise in the circuit through the low-pass filter in the voltage-controlled oscillator circuit.
Drawings
Fig. 1 is a block diagram of a digital amplitude control circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a digital amplitude control circuit according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a digital amplitude controlled voltage-controlled oscillator according to an embodiment of the present invention;
fig. 4 is a schematic diagram of comparing phase noise of a digital amplitude-controlled vco according to an embodiment of the present invention with phase noise of a conventional analog amplitude-controlled vco.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 2, and fig. 3, fig. 1 is a block diagram of a digital amplitude control circuit according to an embodiment of the present invention, fig. 2 is a circuit structure diagram of the digital amplitude control circuit according to the embodiment of the present invention, and fig. 3 is a circuit diagram of a digital amplitude controlled voltage-controlled oscillator according to the embodiment of the present invention. The embodiment of the invention provides a digital amplitude control circuit and a voltage-controlled oscillator thereof, and the circuit structure of the circuit comprises:
the present embodiment provides a digital amplitude control circuit, including:
negative peak detection module, comparison module, logic circuit module, wherein:
a negative peak detection module for detecting a negative peak of the input signal;
the comparison module is connected with the negative peak value detection module and used for judging whether the negative peak value exceeds a reference voltage range or not and outputting a judgment result, wherein the judgment result comprises that the negative peak value exceeds the reference voltage range and the negative peak value does not exceed the reference voltage range;
and the logic circuit module is connected with the comparison module and used for determining whether to output the control signal to adjust the amplitude according to the judgment result, wherein the judgment result indicates that the negative peak value does not exceed the reference voltage range and does not need to output the control signal to adjust the amplitude, and the judgment result indicates that the negative peak value exceeds the reference voltage range and outputs the control signal to adjust the amplitude.
Further, the comparison module comprises a first comparator and a second comparator, wherein:
the positive input end of the first comparator is connected with a first reference voltage, the negative input end of the first comparator is connected with the output end of the negative peak value detection module, and the output end of the first comparator is connected with the first input end of the logic circuit module;
the positive input end of the second comparator is connected with the second reference voltage, the negative input end of the second comparator is connected with the output end of the negative peak detection module, and the output end of the second comparator is connected with the second input end of the logic circuit module.
Preferably, the first comparator is a hysteresis comparator.
Preferably, the second comparator is a hysteresis comparator.
In this embodiment, the negative peak detection module is implemented by a negative peak detector, and the first comparator is specifically a first hysteresis comparator CMP 1 The second comparator is specifically a second hysteresis comparator CMP 2 The reference voltage range is a first reference voltage V REF1 And a second reference voltage V REF2 In the meantime.
The present embodiment provides a digital amplitude-controlled voltage-controlled oscillator including a digital amplitude control circuit, which is constituted by the above-mentioned digital amplitude control circuit.
The voltage-controlled oscillator for digital amplitude control provided by the embodiment further comprises a voltage-controlled oscillation circuit connected with the digital amplitude control circuit; the voltage-controlled oscillating circuit comprises a constant current source I D First resistance R 1 A second resistance R 2 Third resistance R 3 Fourth resistance R 4 Fifth resistor R 5 First inductance L 1 Second inductance L 2 First capacitor C 1 A second capacitor C 2 Third capacitor C 3 Fourth capacitor C 4 First transistor N 1 Second transistor N 2 A third transistor N 3 Fourth transistor N 4 Fifth transistor N 5 The sixth transistor N 6 The seventh transistor N 7 The eighth transistor N 8 First switch S 1 A second switch S 2 Third switch S 3 Fourth switch S 4 Wherein, in the process,
power supply VDD and constant current source I D Input terminal of, first inductance L 1 One terminal of (1), a second inductance L 2 Is connected to a first inductor L 1 The other end of which is connected to the first capacitor C 1 One terminal of (1), a first transistor N 1 Is connected to the drain of the first inductor L 2 And the other end of the first capacitor C 2 One terminal of (1), a second transistor (N) 2 Is connected to the drain of the first capacitor C 1 And the other end of the first transistor N with the second transistor N 2 Grid electrode of (1), fifth resistor R 5 Is connected to a second capacitor C 2 And the other end of the first transistor N 1 Grid electrode of, fourth resistor R 4 Is connected to a fourth resistor R 4 The other end of (1) and a first resistor R 1 One terminal of (C), a third capacitor C 3 Is connected to a fifth resistor R 5 Is connected to the other end of the first resistor R 1 And a third capacitor C 3 Is connected to a first transistor N 1 And the second transistor N 2 Source electrode of (1), fourth transistor N 4 Drain electrode of (1), first switch S 1 First terminal of (2), second switch S 2 First terminal of (2), third switch S 3 First terminal, fourth switch S 4 Is connected to the first terminal of the second transistor N 2 Source electrode of and first switch S 1 First terminal, second switch S 2 First terminal of (1), third switch S 3 First terminal, fourth switch S 4 Is connected to a first terminal of a first switch S 1 Second terminal of and fifth transistor N 5 Is connected to the drain of the second switch S 2 Second terminal of and sixth transistor N 6 Of the third switch S 3 Second terminal and seventh transistor N 7 Is connected to the drain of the fourth switch S 4 Second terminal of and eighth transistor N 8 Is connected to the drain of the fourth transistor N 4 Gate of (1), fifth transistor N 5 Gate of (1), sixth transistor N 6 Gate of (1), seventh transistor N 7 Gate of (1), eighth transistor N 8 Are connected in series in sequence, a fourth transistor N 4 Gate of and fourth capacitor C 4 One terminal of (1), a third resistor R 3 Is connected to a third resistor R 3 And the other end of the first resistor and a second resistor R 2 One terminal of (1), a third transistor N 3 Gate of (2), third transistor N 3 Is connected to the drain of the first resistor R 2 The other end of (1) and a first resistor R 1 Another terminal of (1), constant current source I D Is connected to the output terminal of a third capacitor C 3 The other end of (C), a fourth capacitor C 4 The other end of (1), a third transistor N 3 Source electrode of (1), fourth transistor N 4 Source electrode of (1), fifth transistor N 5 Source electrode of (1), sixth transistor N 6 Source electrode of, seventh transistor N 7 Source electrode of (1), eighth transistor N 8 Are all grounded.
Further, the first inductance L 1 A first capacitor C 1 A first transistor N 1 The connection point of the drain electrode is connected with the first input end of the negative peak value detection module, and the second inductor L 2 A second capacitor C 2 A second transistor N 2 And the connection point of the drain electrode is connected to the second input end of the negative peak value detection module. Wherein, in this embodiment, the first inductor L 1 A first capacitor C 1 A first transistor N 1 The connection point of the drain is a first output voltage V N Second inductance L 2 A second capacitor C 2 A second transistor N 2 The connection point of the drain is a second output voltage V P 。
Furthermore, the first control signal output end of the logic circuit module and the first switch S 1 Is connected with the first end of the logic circuit module, and the second control signal output end of the logic circuit module is connected with the second switch S 2 Is connected with the first end of the logic circuit module, and the third control signal output end of the logic circuit module is connected with the third switch S 3 Is connected with the fourth control signal output end of the logic circuit module and the fourth switch S 4 Is connected to the first end of the first housing.
Preferably, the fifth transistor N 5 A sixth transistor N 6 The seventh transistor N 7 An eighth transistor N 8 The process size ratio is 8.
Preferably, the first transistor N 1 A second transistor N 2 A third transistor N 3 A fourth transistor N 4 The fifth transistor N 5 And a sixth transistor N 6 The seventh transistor N 7 The eighth transistor N 8 Are all N-type MOS tubes.
Referring to fig. 3 again, the present embodiment provides a circuit implementation principle of a digital amplitude-controlled voltage-controlled oscillator, which is described in detail as follows:
the amplitude of the digitally amplitude controlled voltage controlled oscillator of the present invention is designed to be:
wherein, A diff Is the amplitude, I, of a voltage-controlled oscillating circuit bias Is a bias current of a voltage-controlled oscillating circuit, R t The resonant cavity parallel resistor of the voltage-controlled oscillation circuit. It can be seen that the amplitude of the voltage controlled oscillator circuit is represented by I bias Controlled by regulating I bias Thereby adjusting the amplitude A of the voltage-controlled oscillating circuit diff . Wherein, the voltage-controlled oscillating circuit resonant cavity is connected with a resistor R in parallel t And a first inductor L in the voltage-controlled oscillating circuit 1 The second electricityFeeling L 2 It is related.
In the present embodiment, the bias current I of the voltage-controlled oscillation circuit bias From a first bias voltage V B1 Acting on the fourth transistor N 4 A fifth transistor N 5 A sixth transistor N 6 The seventh transistor N 7 An eighth transistor N 8 And a fourth transistor N 4 A fifth transistor N 5 A sixth transistor N 6 The seventh transistor N 7 An eighth transistor N 8 Is determined by the drain of the transistor. Wherein the first bias voltage V B1 Is a third resistor R 3 A fourth capacitor C 4 A fourth transistor N 4 The voltage at the gate connection point. Flows through the fourth transistor N 4 Is a current I 1 Flows through the fifth transistor N 5 Has a current of I 2 Flows through the sixth transistor N 6 Has a current of I 3 Through the seventh transistor N 7 Has a current of I 4 Flows through the eighth transistor N 8 Has a current of I 5 Current I of 1 Current I 2 Current I 3 Current I 4 Current I 5 Together forming a bias current I bias . While the current I 2 Current I 3 Current I 4 Current I 5 Whether or not it can become a bias current I bias Are respectively dependent on the first switch S 1 A first switch S 2 A second switch S 3 And a third switch S 4 Open and close.
In particular, when the first switch S 1 A second switch S 2 And a third switch S 3 And a fourth switch S 4 All are off, current I 2 Current I 3 Current I 4 Current I 5 Are all 0, then the bias current I bias ＝I 1 (ii) a When there is only the first switch S 1 When closed, current I 3 Current I 4 Current I 5 Are all 0, current I 2 If not 0, the bias current I bias ＝I 1 +I 2 (ii) a When the first switch S 1 A second switch S 2 And a third switch S 3 And a fourth switchS 4 Are all closed, current I 2 Current I 3 Current I 4 Current I 5 All are not 0, then the bias current is I bias ＝I 1 +I 2 +I 3 +I 4 +I 5 (ii) a In other cases, the switch is closed, the corresponding current of the switch is not 0, and a bias current I needs to be added bias Otherwise, the switch is off, the current corresponding to the switch is 0, and the bias current I does not need to be added bias In (1). It can be seen that the current flows through the fourth transistor N 4 Current of (I) 1 Must be bias current I bias Through the fifth transistor N 5 Has a current of I 2 Whether or not it can become a bias current I bias Is determined in part by the first switch S 1 Through the sixth transistor N 6 Has a current of I 3 Whether or not it can become a bias current I bias Is determined by the second switch S 2 Through a seventh transistor N 7 Has a current of I 4 Whether or not it can become a bias current I bias Is determined by the third switch S 3 Through the eighth transistor N 8 Has a current of I 5 Whether or not it can become a bias current I bias Is determined in part by the fourth switch S 4 I.e. the corresponding switch is closed, then the corresponding current becomes the bias current I bias When the corresponding switch is turned off, the corresponding current does not become the bias current I bias A part of (a). Wherein, the current I 2 Current I 3 Current I 4 Current I 5 The ratio of (1) 2 Current I 3 Current I 4 Current I 5 The ratio of (8) 5 A sixth transistor N 6 The seventh transistor N 7 An eighth transistor N 8 Process size impact, fifth transistor N in this embodiment 5 And a sixth transistor N 6 The seventh transistor N 7 An eighth transistor N 8 The process size ratio is 8.
Further, the voltage-controlled oscillator of digital amplitude control realizes the originalThe reason is as follows: negative peak detector in digital amplitude control circuit for detecting first output voltage V in voltage-controlled oscillating circuit N And a second output voltage V P Outputting the current amplitude of the voltage-controlled oscillation circuit by the negative peak detector, and respectively passing the amplitude of the voltage-controlled oscillation circuit through the first hysteresis comparator CMP 1 A second hysteresis comparator CMP 2 And a first reference voltage V REF1 A second reference voltage V REF2 For comparison, the first reference voltage V in this embodiment REF1 Taking 0.60V and a second reference voltage V REF2 The value is 0.64V, and the amplitude of the voltage-controlled oscillation circuit is limited within the amplitude range of the voltage-controlled oscillation circuit, wherein the amplitude range of the voltage-controlled oscillation circuit in this embodiment is the first reference voltage V REF1 And a second reference voltage V REF2 Namely, 0.60V to 0.64V, that is, the amplitude fluctuation range of the voltage-controlled oscillation circuit is within plus or minus 20mV. When the first hysteresis comparator CMP 1 If the amplitude of the voltage-controlled oscillation circuit is within the amplitude range of the voltage-controlled oscillation circuit, the first hysteresis comparator CMP 1 The output is 0, and when the amplitude of the VCO exceeds the range of the VCO, the first hysteresis comparator CMP 1 The output is inverted, i.e. the first hysteresis comparator CMP 1 The output changes from 0 to 1; similarly, when the second hysteresis comparator CMP 2 If the amplitude of the voltage-controlled oscillation circuit is within the amplitude range of the voltage-controlled oscillation circuit, the second hysteresis comparator CMP 2 The output is 1, and when the amplitude of the VCO exceeds the range of the amplitude of the VCO, the second hysteresis comparator CMP 2 The output being inverted, i.e. the second hysteresis comparator CMP 2 The output changes from 1 to 0. Finally, a first control signal B is output through a first control signal output end of the logic circuit 1 The second control signal output end outputs a second control signal B 2 A third control signal output terminal for outputting a third control signal B 3 The fourth control signal output end outputs a fourth control signal B 4 Thereby regulating and controlling bias current I of voltage-controlled oscillating circuit bias And adjusting the amplitude of the voltage-controlled oscillation circuit within the amplitude range of the voltage-controlled oscillation circuit.
For example, in the initial stage, the logic circuit adjusts the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 Is 1, 0, and the bias current is I bias ＝I 1 +I 2 . When the negative peak detector detects that the amplitude of the voltage-controlled oscillating circuit is less than the first reference voltage V REF1 First hysteresis comparator CMP 1 The output is inverted, i.e. the first hysteresis comparator CMP 1 The output changes from 0 to 1, then the logic circuit will adjust the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 Has an output value of 1, 0, 1, a bias current I bias Will increase, I bias ＝I 1 +I 2 +I 5 At this time, the amplitude of the voltage controlled oscillation circuit increases. If the negative peak detector detects that the amplitude of the voltage-controlled oscillating circuit is still less than the first reference voltage V REF1 First hysteresis comparator CMP 1 The hold output is 1 and the logic circuit will adjust the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 Has an output value of 1, 0, a bias current I bias Continues to increase, I bias ＝I 1 +I 2 +I 4 At this time, the amplitude of the voltage controlled oscillation circuit increases. If the amplitude negative peak detector detects that the amplitude of the voltage-controlled oscillating circuit is still less than the first reference voltage V REF1 The circuit continues with the above step by adjusting the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 To increase the bias current I bias Thereby increasing the amplitude of the voltage-controlled oscillation circuit until the amplitude of the voltage-controlled oscillation circuit is at the first reference voltage V REF1 And a second reference voltage V REF2 In the meantime. When the amplitude of the voltage-controlled oscillation circuit is at the first reference voltage V REF1 And a second reference voltage V REF2 In between, the first hysteresis comparator CMP 1 The output being reversed, i.e.First hysteresis comparator CMP 1 The output changes from 1 to 0. In this embodiment, the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 The variations are not limited thereto, and the specific variations relate to the temperature in the environment, the process flow, and the like.
As another example, during the initial stage, the logic circuit adjusts the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 Is 1, 0, in which case I bias ＝I 1 +I 2 . When the negative peak detector detects that the amplitude of the voltage-controlled oscillating circuit is larger than the second reference voltage V REF2 Second hysteresis comparator CMP 2 The output is inverted, i.e. the first hysteresis comparator CMP 2 The output changes from 1 to 0, then the logic circuit will adjust the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 Has an output value of 0, 1, a bias current I bias Will be reduced, i.e. I bias ＝I 1 +I 3 +I 4 +I 5 At this time, the amplitude of the voltage controlled oscillation circuit decreases. Similarly, if the negative peak detector detects that the amplitude of the voltage controlled oscillator circuit is still greater than the second reference voltage V REF2 The circuit continues with the above step by adjusting the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 To reduce the bias current I bias So as to obtain smaller amplitude of the voltage-controlled oscillating circuit until the amplitude of the voltage-controlled oscillating circuit is positioned at the first reference voltage V REF1 And a second reference voltage V REF2 In the meantime. When the amplitude of the voltage-controlled oscillation circuit is at the first reference voltage V REF1 And a second reference voltage V REF2 In between, the second hysteresis comparator CMP 2 The output being inverted, i.e. the second hysteresis comparator CMP 2 The output changes from 0 to 1. In this embodiment, the first control signal B 1 A second control signal B 2 A third control signal B 3 A fourth control signal B 4 The variations are not limited thereto and the specific variations are related to the temperature in the environment, the process flow, etc.
The digital amplitude control circuit is integrated in the voltage-controlled oscillation circuit, and control signals do not need to be introduced through an external chip, so that the amplitude of the voltage-controlled oscillation circuit is controlled, and the circuit design is simple.
In order to confirm the superiority of the digital amplitude control circuit in the present application to amplitude adjustment of the voltage-controlled oscillation circuit, the present embodiment compares the method without using the digital amplitude control circuit with the method using the digital amplitude control circuit in the present application under three different processes, namely, the standard process, the slow process, and the fast process, specifically please refer to table 1.
TABLE 1 amplitude control of voltage controlled oscillators at different temperatures and different processes
Table 1 shows the amplitude control of the vco at different temperatures and different processes. In this embodiment, the amplitude range of the voltage controlled oscillating circuit in this embodiment is the first reference voltage V REF1 And a second reference voltage V REF2 I.e., 0.60V to 0.64V. As can be seen from the table, when the digital amplitude control circuit is not used, the amplitude of the voltage-controlled oscillation circuit is controlled to be 0.535V-0.655V, namely, plus or minus 60mV; when the digital amplitude control circuit of the present application is used, the amplitude of the voltage-controlled oscillation circuit is controlled to be 0.60V to 0.64V, i.e., positive or negative 20mV. Therefore, the digital amplitude control circuit can provide a wider amplitude range of the voltage-controlled oscillation circuit for the voltage-controlled oscillator. Where tt denotes a standard process, ss denotes a slow speed process, and ff denotes a fast speed process.
In the embodiment, the amplitude of the voltage-controlled oscillation circuit of the voltage-controlled oscillator at different temperatures and different process characteristics is ensured by using the digital amplitude control circuit, so that the tuning frequency of the voltage-controlled oscillator is widened.
Fig. 4 is a schematic diagram of comparing noise phases of a digital amplitude-controlled vco and a conventional analog amplitude-controlled vco according to an embodiment of the present invention. It can be seen that the digital amplitude controlled voltage controlled oscillator of the present invention has better noise rejection performance than the conventional analog amplitude controlled voltage controlled oscillator at any frequency. For example, at 1MHZ, the phase noise of the present invention is improved by 5dBc over the phase noise of conventional analog amplitude control circuits.
The beneficial effects of this embodiment:
1. the embodiment reduces the phase noise introduced to the voltage-controlled oscillator by adopting the analog amplitude control circuit by using the digital amplitude control circuit, thereby improving the performance of the voltage-controlled oscillator.
2. The digital amplitude control circuit is integrated in the voltage-controlled oscillation circuit, and a control signal is not required to be introduced through an external chip, so that the amplitude of the voltage-controlled oscillation circuit is controlled, and the circuit design is simple.
3. The present embodiment controls the bias current of the voltage-controlled oscillation circuit by using the digital amplitude control circuit, so that the amplitude of the voltage-controlled oscillation circuit can be maintained within a certain range.
4. In the embodiment, the amplitude of the voltage-controlled oscillation circuit of the voltage-controlled oscillator at different temperatures and different process characteristics is ensured by using the digital amplitude control circuit, so that the tuning frequency of the voltage-controlled oscillator is widened.
5. In the embodiment, the low-pass filter in the voltage-controlled oscillator circuit is used for filtering high-frequency noise in the circuit and improving the performance of the circuit on high-frequency phase noise.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (5)
1. A digital amplitude controlled voltage controlled oscillator comprising a voltage controlled oscillation circuit, and a digital amplitude control circuit connected to said voltage controlled oscillation circuit, wherein,
the voltage controlled oscillation circuit comprises a constant current source (I) D ) First resistance (R) 1 ) Second resistance (R) 2 ) Third resistance (R) 3 ) Fourth resistance (R) 4 ) Fifth resistance (R) 5 ) First inductance (L) 1 ) Second inductance (L) 2 ) First capacitance (C) 1 ) A second capacitance (C) 2 ) Third capacitance (C) 3 ) Fourth capacitance (C) 4 ) First transistor (N) 1 ) Second transistor (N) 2 ) A third transistor (N) 3 ) Fourth transistor (N) 4 ) Fifth transistor (N) 5 ) Sixth transistor (N) 6 ) Seventh transistor (N) 7 ) An eighth transistor (N) 8 ) First switch (S) 1 ) Second switch (S) 2 ) Third switch (S) 3 ) Fourth switch (S) 4 ) Wherein the power supply VDD and the constant current source I D ) Said first inductor (L) 1 ) One terminal of, the second inductance (L) 2 ) Is connected to said first inductor (L) 1 ) And the other end of said first capacitor (C) 1 ) One terminal of (a), the first transistor (N) 1 ) The drain of the first inductor (L) is connected to 2 ) And the other end of said first capacitor (C) 2 ) One terminal of (b), the second transistor (N) 2 ) The first capacitor (C) 1 ) And the other end of the second transistor (N) with the second transistor (N) 2 ) The gate of (2), the fifth resistor (R) 5 ) Is connected to one terminal of the second capacitor (C) 2 ) And the other end of the first transistor (N) 1 ) The fourth resistor (R) 4 ) Is connected to one end of the fourth resistor (R), the fourth resistor (R) 4 ) And the other end of the first resistor (R) 1 ) One terminal of, the third capacitance (C) 3 ) Is connected to the fifth resistor (R) 5 ) Is connected to the other end of the first resistor (R) 1 ) Is also connected withThird capacitance (C) 3 ) Is connected to one terminal of the first transistor (N) 1 ) And the second transistor (N) 2 ) Source of (b), the fourth transistor (N) 4 ) Drain of (a), the first switch (S) 1 ) The first terminal, the second switch (S) 2 ) The first terminal of (S), the third switch (S) 3 ) Said fourth switch (S) 4 ) Is connected to the first terminal of the second transistor (N), the second transistor (N) 2 ) And the first switch (S) 1 ) First terminal of, the second switch (S) 2 ) First terminal of (a), the third switch (S) 3 ) Said fourth switch (S) 4 ) Is connected to the first terminal of the first switch (S) 1 ) And the second terminal of the fifth transistor (N) 5 ) The second switch (S) 2 ) And the sixth transistor (N) 6 ) The drain of the third switch (S) is connected, the third switch (S) 3 ) And the seventh transistor (N) 7 ) Is connected to the drain of the fourth switch (S) 4 ) And the eighth transistor (N) 8 ) Is connected to the drain of the fourth transistor (N) 4 ) The gate of (b), the fifth transistor (N) 5 ) The gate of (b), the sixth transistor (N) 6 ) Gate of (b), the seventh transistor (N) 7 ) The eighth transistor (N) 8 ) Are connected in series in sequence, the fourth transistor (N) 4 ) And the fourth capacitor (C) 4 ) One terminal of (d), the third resistance (R) 3 ) Is connected to the third resistor (R) 3 ) And the other end of the second resistor (R) and the second resistor (R) 2 ) One terminal of (b), the third transistor (N) 3 ) Of the third transistor (N) 3 ) The second resistor (R), the second resistor (R) 2 ) And the other end of said first resistor (R) 1 ) The other end of (a), the constant current source (I) D ) Is connected to the output of the third capacitor (C) 3 ) The other end of (C), the fourth capacitance (C) 4 ) Another terminal of (b), the third transistor (N) 3 ) Source of (b), the fourth transistor (N) 4 ) Source of (b), the fifth transistor (N) 5 ) The sixth transistor (N) 6 ) The source of (b), the seventh transistor (N) 7 ) Source of (b), the eighth transistor (N) 8 ) The source electrodes of the first and second transistors are all grounded;
the digital amplitude control circuit comprises a negative peak value detection module, a comparison module and a logic circuit module, wherein the negative peak value detection module is used for detecting the negative peak value of an input signal; the comparison module is connected with the negative peak value detection module and used for judging whether the negative peak value exceeds a reference voltage range or not and outputting a judgment result, wherein the judgment result comprises that the negative peak value exceeds the reference voltage range and the negative peak value does not exceed the reference voltage range; a logic circuit module, connected to the comparison module, for determining whether to output a control signal to adjust the amplitude according to the determination result, wherein the determination result indicates that the negative peak value does not exceed the reference voltage range and does not need to output the control signal to adjust the amplitude, and the determination result indicates that the negative peak value exceeds the reference voltage range and outputs the control signal to adjust the amplitude, wherein a first control signal output end of the logic circuit module and the first switch (S) are connected to each other 1 ) Is connected to the first terminal of the first switch (S), a second control signal output terminal of the logic circuit module is connected to the second switch (S) 2 ) Is connected to the first terminal of the first switch, and a third control signal output terminal of the logic circuit module is connected to the third switch (S) 3 ) Is connected to the fourth switch (S), a fourth control signal output terminal of the logic circuit module is connected to the fourth switch (S) 4 ) Is connected;
the first control signal, the second control signal, the third control signal and the fourth control signal are sequentially and respectively used for controlling the on or off states of the first switch, the second switch, the third switch and the fourth switch;
the first switch, the second switch, the third switch and the fourth switch are used for controlling the bias current of the voltage-controlled oscillation circuit so as to realize amplitude adjustment of the voltage-controlled oscillation circuit;
the first inductor (L) 1 ) The first capacitor (C) 1 ) The first transistor (N) 1 ) The connection point of the drain is connected to the first input terminal of the negative peak detection module, the second inductor (L) 2 ) The second capacitor (C) 2 ) The second transistor (N) 2 ) The connection point of the drain electrode is connected to the second input end of the negative peak value detection module;
the comparison module comprises a first comparator and a second comparator, wherein:
a positive input end of the first comparator is connected with a first reference voltage, a negative input end of the first comparator is connected with an output end of the negative peak detection module, and an output end of the first comparator is connected with a first input end of the logic circuit module;
a positive input end of the second comparator is connected with a second reference voltage, a negative input end of the second comparator is connected with an output end of the negative peak detection module, and an output end of the second comparator is connected with a second input end of the logic circuit module;
when the negative peak detection module detects that the amplitude of the voltage-controlled oscillation circuit is smaller than the first reference voltage, the output of the first comparator is inverted, the output values of the first control signal, the second control signal, the third control signal and the fourth control signal are adjusted by the logic circuit, the bias current is increased, and the amplitude of the voltage-controlled oscillation circuit is further increased;
when the negative peak detection module detects that the amplitude of the voltage-controlled oscillation circuit is larger than the second reference voltage, the output of the second comparator is inverted, the logic circuit adjusts the output values of the first control signal, the second control signal, the third control signal and the fourth control signal, the bias current is reduced, and the amplitude of the voltage-controlled oscillation circuit is further reduced.
2. Voltage controlled oscillator according to claim 1, characterized in that the fifth transistor (N) 5 ) The sixth transistor (N) 6 ) The seventh transistor (N) 7 ) The eighth transistor (N) 8 ) The process size ratio is 8.
3. The digital amplitude controlled press of claim 1A controlled oscillator, characterized in that said first transistor (N) 1 ) The second transistor (N) 2 ) The third transistor (N) 3 ) The fourth transistor (N) 4 ) The fifth transistor (N) 5 ) The sixth transistor (N) 6 ) The seventh transistor (N) 7 ) The eighth transistor (N) 8 ) Are all N-type MOS tubes.
4. The digital amplitude controlled voltage controlled oscillator of claim 1, wherein the first comparator is a hysteretic comparator.
5. The digital amplitude controlled voltage controlled oscillator of claim 1, wherein the second comparator is a hysteretic comparator.
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| CN110768667B (en) * | 2019-09-17 | 2023-08-01 | 西安电子科技大学 | Double-digital loop controlled low-power consumption low-phase noise C-type VCO |
| CN113783528B (en) * | 2021-09-08 | 2024-04-12 | 苏州磐启微电子有限公司 | Low-power-consumption oscillator circuit |
| CN115309220A (en) * | 2022-08-16 | 2022-11-08 | 上海芯问科技有限公司 | Readout circuit of magnetic-sensitive protein sensor |
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