CN102299707A - Secondary frequency divider with quadrature phase error correction - Google Patents
Secondary frequency divider with quadrature phase error correction Download PDFInfo
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- CN102299707A CN102299707A CN2011101068722A CN201110106872A CN102299707A CN 102299707 A CN102299707 A CN 102299707A CN 2011101068722 A CN2011101068722 A CN 2011101068722A CN 201110106872 A CN201110106872 A CN 201110106872A CN 102299707 A CN102299707 A CN 102299707A
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Abstract
The invention discloses a secondary frequency divider with quadrature phase error correction. The divider comprises a main latch generating I channel signals and a slave latch generating Q channel signals. The secondary frequency divider is characterized in that the tail current source of the main latch is a correction circuit composed of N N-metal-oxide-semiconductor transistors (NMOS) namely MI1, MI2......MIN; the grid electrodes of N transistors namely MI1, MI2......MIN are respectively controlled by N control signals namely IB1, IB2...... and IBN, thus controlling the bias current of the main latch; the tail current source of the slave latch is the correction circuit composed of N NMOS transistors namely MQ1, MQ2......MQN; and the grid electrodes of N transistors namely MQ1, MQ2......MQN are respectively controlled by N control signals namely QB1, QB2...QBN, thus controlling the bias current of the slave latch. By utilizing the secondary frequency divider provided by the invention, the control words are increased, the bias current of the latch is adjusted, and the phase error of the orthogonal two-path signal of the secondary frequency divider with a serial communication loop (SCL) structure is corrected.
Description
Technical field
The utility model belongs to the technical field of frequency microwave communication, is specifically related to local oscillator generation device wherein.
Background technology
At present, under the more and more higher requirement of level of integrated system, all built-in local oscillator of now nearly all transceiver produces circuit.Local oscillator produces circuit and generally comprises voltage controlled oscillator and phase-locked loop circuit and local oscillator treatment circuit.The local oscillator treatment circuit generally comprises the content of three aspects: the one, and the frequency translation of local oscillator, generally be to remove two in the zero intermediate frequency circuit, the 2nd, the generation of orthogonal signalling, the 3rd, the amplification of local oscillation signal, the present invention relate generally to the quadrature of handling preceding two aspects and remove two-divider.
The two-divider that removes of general local oscillator comprises two classes: the one, the arrowband based on ultraharmonics injection locking, the 2nd, the broadband based on principal and subordinate's d type flip flop.The first kind is injected two stronger frequency-doubled signals by giving a vibration, and the traction oscillator also makes it to lock onto 1/2 frequency of the signal that is injected.This class circuit power consumption is lower, but there are two problems: the one, the frequency of work is narrow, has limited its application in Modern Communication System, and the 2nd, circuit itself can not produce the local oscillation signal of quadrature, must use other the whole circuitry phase of filtering, this will bring the loss of local oscillation signal power.The broadband character of second class formation has determined speed and power consumption to become a pair of contradiction, that is to say that the raising of speed must be with high power consumption as cost.Have again, device on the second class formation signal path (as the device of two triggers or latch) does not match or not matching of associating also can be introduced extra phase error, but also the influence of receiving the duty ratio of input signal, when duty ratio was not 50%, the quadrature performance can worsen.Local oscillator I, the transceiver performance that the phase place of Q two paths of signals does not match and can have a strong impact on communication system.
At present common local oscillator produces the two-divider that removes of circuit, as shown in Figure 1, the master-slave mode d type flip flop that utilizes two D-latchs to constitute, link to each other by the d type flip flop input and output then and constitute a high speed two-divider, if input signal is a duty ratio is 50% fully differential signal, then main latch and be exactly the orthogonal signalling of difference from the output signal of latch.
Shown in Figure 2 is the common SCL two-divider that does not have the phase error calibration, be example with the main latch that produces the I path signal earlier, wherein R1, R2 are biasing resistor, in CMOS technology, these two resistance can be polysilicon resistance, trap resistance, diffusion region active pull-up and the PMOS that is operated in linear zone pipe; It is right that two of M5, M6 constitute a pair of NMOS mutual coupling, forms a negative resistance, mainly is to keep output signal; M3, the M4 differential pair that partners mainly is that transmission, amplification input signal are to output; Two of M1, M2 are the switches in Control current source, and the control signal of M1 is input clock CLKp, and the control signal of M2 is the inversion signal CLKn of input clock.These two transistor switched conductive are being controlled latch and are being transmitted and keeping changing between two states.Transistor MI is the tail current source of main latch, provides control voltage Vbias by external bias circuit.
Consistent with main latch from the structure of latch, wherein R3, R4 are biasing resistor; It is right that two of M11, M12 constitute a pair of NMOS mutual coupling, forms a negative resistance, keeps output signal; M9, the M10 differential pair that partners mainly is that transmission, amplification input signal are to output; Two of M7, M8 are the switches in Control current source, and the control signal of M8 is input clock CLKp, and the control signal of M7 is the inversion signal CLKn of input clock.Transistor MQ is the tail current source of main latch, provides control voltage Vbias by external bias circuit.Because not matching of device and line, there are phase mismatch in this two-divider I, Q two-way orthogonal signalling.
If device does not match or not matching of line can be mirrored extra phase error on the two-divider signal path, and the duty ratio of working as input differential signal is not 50% or is not the fully differential signal, the quadrature performance also can worsen, and therefore needs to add calibration circuit.
Summary of the invention
The technical problem to be solved in the present invention is to utilize the quadrature mismatch problem of the two-divider that master and slave trigger constitutes, and a kind of two-divider that has the quadrature phase error calibration is provided.
For solving the problems of the technologies described above, the technical solution used in the present invention is: the two-divider that has the quadrature phase error calibration, comprise the main latch that produces the I path signal and produce the Q channel signal from latch, the tail current source of described main latch is by MI1, MI2 ... this N of MIN the calibration circuit that nmos pass transistor is formed, MI1, MI2 ... this N of MIN transistorized grid is respectively by IB1, IB2 ... this N of IBN control signal is controlled, thereby is controlling the size of the bias current of main latch; Described tail current source from latch is by MQ1, MQ2 ... this N of MQN the calibration circuit that nmos pass transistor is formed, MQ1, MQ2 ... this N of MQN transistorized grid is respectively by QB1, QB2 ... this N of QBN control signal is controlled, thereby is controlling from the size of the bias current of latch.
The present invention is by utilizing 2N position control word (IB1 ... IBN and QB1 ... QBN) controlling respectively main latch, from the size of the bias current of latch, thereby change the I road or the delay of Q road signal calibrate the phase mismatch of I, Q two-way orthogonal signalling.
Described control word control main latch, from the size of the bias current of latch concrete derive as follows:
As the phase place of I road signal in advance than the phase place of Q road signal, just the signal transmission delay T on I road is less than the signal transmission delay on Q road, the two-way orthogonal signalling have produced phase mismatch, begin to reduce the bias current of I branch road (main latch), just reduce control word IBN ... the value of IB1, like this according to following capacitor charge and discharge equation:
（2）
Wherein
Be charging (or discharge) average current of latch state when changing,
Be latch output equivalent load capacitance,
Be the amplitude of oscillation of output signal,
Be the change-over time of latch,
Be the propagation delay time,
By formula (2) as can be known, under the constant prerequisite of the output signal amplitude of oscillation, output equivalent load capacitance, the propagation delay time of latch
With average charge (discharge) electric current
Be inversely proportional to, and
Be approximately equal to the bias current of latch, so, just can increase the time of delay of I path by reducing the bias current value of I path
, according to the relational expression of phase place and time of delay:
Wherein T is the cycle of output signal, increases by the transmission delay that increases the I path signal like this, just can increase the phase place of I path signal, perhaps increase the bias current of Q channel, reduce the transmission delay of Q channel signal, reduce the phase error that its phase place is eliminated two path signal
Through careful size of regulating the control word in two passage current sources, can eliminate the phase error of I, Q two-way orthogonal signalling;
As the phase place of Q channel in advance than the phase place on I road, then reduce control word QBN ... the value of QB1, reduce bias current from latch, thereby increase the signal transmission delay of Q channel, increase the phase place of Q channel, perhaps increase control word IB1 ... the value of IBN, increase the bias current of main latch, thereby reduce the transmission delay of I path, reduce the phase place of I path, so also eliminated the phase error of I, Q two quadrature channel signals.
Beneficial effect of the present invention: the present invention has increased control word, regulates the latch bias current, has calibrated the phase error of quadrature two paths of signals of the two-divider of SCL structure.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail, but does not constitute any limitation of the invention.
Fig. 1 is the two-divider structure chart that present master and slave trigger constitutes.
Fig. 2 is the existing common SCL structure two-divider circuit diagram of not calibrating phase error.
Fig. 3 is the two-divider circuit diagram with calibration orthogonal signalling phase error function.
Embodiment
As shown in Figure 3, a kind of two-divider of quadrature phase error calibration that has of the present invention is on common two-divider basis shown in Figure 2, MI and two tail current sources of MQ are used MI1, MI2 respectively ... MIN and MQ1, MQ2 ... this 2N of MQN nmos pass transistor formed calibration circuit, MI1, MI2 ... this N of MIN transistorized grid is respectively by IB1, IB2 ... this N of IBN control signal is controlled, and is also controlling the size of the bias current of main latch.MQ1, MQ2 ... this N of MQN transistorized grid is respectively by QB1, QB2 ... this N of QBN control signal is controlled, and is also controlling from the size of the bias current of latch.The bias current of I, Q two paths all can be controlled and be regulated by the external control word like this, to eliminate the phase mismatch of two path signal, is described in detail the phase error calibration process below.
The present invention is by utilizing 2N position control word (IB1 ... IBN and QB1 ... QBN) divide the size of the bias current controlling principal and subordinate's latch, thus change the I road or the delay of Q road signal calibrate the phase mismatch of I, Q two-way orthogonal signalling.Concrete derivation is as follows.
If the phase place of I road signal shifts to an earlier date than the phase place of Q road signal, just the signal transmission delay T on I road is less than the signal transmission delay on Q road, and the two-way orthogonal signalling have produced phase mismatch.Begin to reduce the bias current of I branch road (main latch), just reduce control word IBN ... the value of IB1.Like this according to following capacitor charge and discharge equation:
Wherein
Be charging (or discharge) average current of latch state when changing,
Be latch output equivalent load capacitance,
Be the amplitude of oscillation of output signal,
Be the change-over time of latch,
It is the propagation delay time.
By formula (2) as can be known, under the constant prerequisite of the output signal amplitude of oscillation, output equivalent load capacitance, the propagation delay time of latch
With average charge (discharge) electric current
Be inversely proportional to, and
Be approximately equal to the bias current of latch, so, just can increase the time of delay of I path by reducing the bias current value of I path
Relational expression according to phase place and time of delay:
Wherein T is the cycle of output signal, increases by the transmission delay that increases the I path signal like this, just can increase the phase place of I path signal.Also can increase the bias current of Q channel (from latch) in addition, reduce the transmission delay of Q channel signal, reduce the phase error that its phase place is eliminated two path signal.Through careful size of regulating the control word in two passage current sources, can eliminate the phase error of I, Q two-way orthogonal signalling.
If the phase place of Q channel then reduces control word QBN than the phase place on I road in advance ... the value of QB1 reduces the bias current from latch, thereby increases the signal transmission delay of Q channel, increases the phase place of Q channel.Perhaps increase control word IB1 ... the value of IBN increases the bias current of main latch, thereby reduces the transmission delay of I path, reduces the phase place of I path.So also eliminated the phase error of I, Q two quadrature channel signals.
In a word; though the present invention has exemplified above-mentioned preferred implementation, should illustrate, though those skilled in the art can carry out various variations and remodeling; unless such variation and remodeling have departed from scope of the present invention, otherwise all should be included in protection scope of the present invention.
Claims (3)
1. one kind has the two-divider that quadrature phase error is calibrated, comprise the main latch that produces the I path signal and produce the Q channel signal from latch, it is characterized in that: the tail current source of described main latch is by MI1, MI2 ... this N of MIN the calibration circuit that nmos pass transistor is formed, MI1, MI2 ... this N of MIN transistorized grid is respectively by IB1, IB2 ... this N of IBN control signal is controlled, thereby is controlling the size of the bias current of main latch; Described tail current source from latch is by MQ1, MQ2 ... this N of MQN the calibration circuit that nmos pass transistor is formed, MQ1, MQ2 ... this N of MQN transistorized grid is respectively by QB1, QB2 ... this N of QBN control signal is controlled, thereby is controlling from the size of the bias current of latch.
2. according to the described a kind of two-divider that has the quadrature phase error calibration of claim 1, it is characterized in that: by utilizing 2N position control word (IB1 ... IBN and QB1 ... QBN) controlling respectively main latch, from the size of the bias current of latch, thereby change the I road or the delay of Q road signal calibrate the phase mismatch of I, Q two-way orthogonal signalling.
3. according to the described a kind of two-divider that has quadrature phase error calibration of claim 2, it is characterized in that: described control word control main latch, from the size of the bias current of latch concrete derive as follows:
As the phase place of I road signal in advance than the phase place of Q road signal, just the signal transmission delay T on I road is less than the signal transmission delay on Q road, the two-way orthogonal signalling have produced phase mismatch, begin to reduce the bias current of I branch road (main latch), just reduce control word IBN ... the value of IB1, like this according to following capacitor charge and discharge equation:
Wherein
Be charging (or discharge) average current of latch state when changing,
Be latch output equivalent load capacitance,
Be the amplitude of oscillation of output signal,
Be the change-over time of latch,
Be the propagation delay time,
By formula (2) as can be known, under the constant prerequisite of the output signal amplitude of oscillation, output equivalent load capacitance, the propagation delay time of latch
With average charge (discharge) electric current
Be inversely proportional to, and
Be approximately equal to the bias current of latch, so, just can increase the time of delay of I path by reducing the bias current value of I path
, according to the relational expression of phase place and time of delay:
Wherein T is the cycle of output signal, increases by the transmission delay that increases the I path signal like this, just can increase the phase place of I path signal, perhaps increase the bias current of Q channel, reduce the transmission delay of Q channel signal, reduce the phase error that its phase place is eliminated two path signal
Through careful size of regulating the control word in two passage current sources, can eliminate the phase error of I, Q two-way orthogonal signalling;
As the phase place of Q channel in advance than the phase place on I road, then reduce control word QBN ... the value of QB1, reduce bias current from latch, thereby increase the signal transmission delay of Q channel, increase the phase place of Q channel, perhaps increase control word IB1 ... the value of IBN, increase the bias current of main latch, thereby reduce the transmission delay of I path, reduce the phase place of I path, so also eliminated the phase error of I, Q two quadrature channel signals.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208990A (en) * | 2013-01-29 | 2013-07-17 | 嘉兴联星微电子有限公司 | New type high speed prescale circuit |
| CN104320204A (en) * | 2014-11-11 | 2015-01-28 | 中国电子科技集团公司第五十四研究所 | Local oscillator IQ signal phase and amplitude calibration device |
| CN105406843A (en) * | 2015-12-09 | 2016-03-16 | 中国计量学院 | Four-path orthogonal signal generator with accurately-adjustable phase |
| CN106027453A (en) * | 2015-03-24 | 2016-10-12 | 松下知识产权经营株式会社 | Wireless communication device and malfunction determining method |
| CN110504956A (en) * | 2019-07-05 | 2019-11-26 | 加驰（厦门）微电子股份有限公司 | A kind of broadband pre-divider that power consumption is adaptive |
| CN111552343A (en) * | 2020-05-22 | 2020-08-18 | 聚洵半导体科技（上海）有限公司 | Low-voltage low-current bias current circuit |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208990A (en) * | 2013-01-29 | 2013-07-17 | 嘉兴联星微电子有限公司 | New type high speed prescale circuit |
| CN103208990B (en) * | 2013-01-29 | 2016-02-10 | 殷明 | The pre-frequency dividing circuit of a kind of novel high speed |
| CN104320204A (en) * | 2014-11-11 | 2015-01-28 | 中国电子科技集团公司第五十四研究所 | Local oscillator IQ signal phase and amplitude calibration device |
| CN106027453A (en) * | 2015-03-24 | 2016-10-12 | 松下知识产权经营株式会社 | Wireless communication device and malfunction determining method |
| CN105406843A (en) * | 2015-12-09 | 2016-03-16 | 中国计量学院 | Four-path orthogonal signal generator with accurately-adjustable phase |
| CN105406843B (en) * | 2015-12-09 | 2018-01-16 | 中国计量学院 | A kind of accurate adjustable four road orthogonal signal generator of phase |
| CN110504956A (en) * | 2019-07-05 | 2019-11-26 | 加驰（厦门）微电子股份有限公司 | A kind of broadband pre-divider that power consumption is adaptive |
| CN111552343A (en) * | 2020-05-22 | 2020-08-18 | 聚洵半导体科技（上海）有限公司 | Low-voltage low-current bias current circuit |
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Application publication date: 20111228 |