CN102664520A - Phase-locked loop charge pump circuit with low current mismatch - Google Patents

Phase-locked loop charge pump circuit with low current mismatch Download PDF

Info

Publication number
CN102664520A
CN102664520A CN2012101430351A CN201210143035A CN102664520A CN 102664520 A CN102664520 A CN 102664520A CN 2012101430351 A CN2012101430351 A CN 2012101430351A CN 201210143035 A CN201210143035 A CN 201210143035A CN 102664520 A CN102664520 A CN 102664520A
Authority
CN
China
Prior art keywords
fet
grid
connects
drain electrode
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012101430351A
Other languages
Chinese (zh)
Inventor
徐平平
张文华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
Original Assignee
Southeast University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University filed Critical Southeast University
Priority to CN2012101430351A priority Critical patent/CN102664520A/en
Publication of CN102664520A publication Critical patent/CN102664520A/en
Pending legal-status Critical Current

Links

Abstract

The invention discloses a phase-locked loop charge pump circuit with low current mismatch. The phase-locked loop charge pump circuit comprises a current mirror and a charge pump, wherein the charge pump comprises a first input transmission gate and a second input transmission gate; a cascode transistor M41 and a cascode transistor M42 are arranged between the first input transmission gate and an output node vout, so that a first current path is constructed; a cascode transistor M43 and a cascode transistor M44 are arranged between the output node vout and the second input transmission gate, so that a second current path is constructed; the current mirror is coupled to the grids of the cascode transistors M41, M42, M43 and M44, and is used for transmitting offset voltages V1, V2, V3 and V4 to the grids of the cascode transistors M41, M42, M43 and M44 respectively; and the offset voltages V1, V2, V3 and V4 are used for making the cascode transistors M41, M42, M43 and M44 work in a saturated region respectively. Compared with an ordinary charge pump circuit without any cascode structure, the output impedance is increased by one magnitude, and low mismatch current is obtained.

Description

A kind of phase-locked loop charge pump circuit of low current mismatch
Technical field
The present invention relates to a kind of single-ended charge pump; Be a kind of phase-locked loop charge pump circuit of low current mismatch specifically, it can effectively obtain bigger output impedance, wide output voltage swing; Lower gain error again can be with relatively low charge pump current work.
Background technology
Phase-locked loop (Phase locked loop; Be called for short " PLL ") circuit be used for producing one can be with frequency and phase locking electronic system at the another one signal; Phase-locked loop circuit can constitute clock data recovery circuit with other modules, will import data sync to a clock signal.
Typical PLL comprises a frequency discrimination frequency discriminator (Phase Frequency Detector; Abbreviation PFD), charge pump (Charge Pump; Abbreviation CP), loop filter (Low Pass Filter; Be called for short LPF) and voltage controlled oscillator (Voltage Controlled Oscillator is called for short VCO).PLL accepts external reference signal, and carries out bit comparison mutually with the changeable frequency signal of this locality generation.Phase frequency detector PFD produces phase error signal UP and DN through comparison reference signal and local changeable frequency signal, and these two phase error signals are as the input of charge pump CP.Charge pump CP can produce a corresponding electric current and come the response phase error signal.Current will flow into the loop filter LPF and generate a voltage to control the voltage controlled oscillator VCO oscillation frequency to change accordingly.Through the output frequency of control VCO, the frequency of PLL and phase place can match the reference signal of input gradually.
Existing P LL as shown in Figure 1 comprises phase discriminator (PHASE DETCETOR), is used for detecting the phase error of two signals; Charge pump (charge pump) is used for receiving the error signal of phase discriminator and exports a current corresponding Icp; Loop filter (LOOP FILTER); Be used for the dynamic characteristic of Control and Feedback loop (CLOCK SIGNAL), and the high-frequency noise of the electric current that produces of filtering charge pump; Voltage controlled oscillator (VCO) according to loop filter produce output voltage produce variable-frequency clock signal, feedback control loop couples together these elements.System (PLL) accepts a reference signal (Reference Signal), produces the frequency that a clock signal (Clock Signal) is used for mating this reference signal.
The phase discriminator comparison be the phase place of a reference signal and a clock signal.Phase discriminator may comprise an XOR gate, or a four-quadrant multiplier, or a phase frequency detector (PFD).In the reality, phase discriminator produces a corresponding error correction signal with the phase difference of reference signal and clock signal.This error correction signal comprises a rising signals (being designated as " up ") and a dropping signal (being designated as " dn "), and error correction signal comprises two signals that are operated in opposite logic, and one is rising signals, and one is dropping signal.In the reality, error correction signal is directly proportional with the phase error signal of reference signal, clock signal.If the phase place of clock signal seriously lags behind the phase place of reference signal, the up signal (for example, wide positive signal) of a relative broad of phase discriminator output.If the phase place of clock signal is leading a little and in the phase place of reference signal, phase discriminator is exported the dn signal (for example, narrow negative signal) of a relative narrower.
Phase discriminator sends error correction signal to charge pump.The error correction signal that the charge pump response receives produces an electric current .In the reality, the size of up and dn signal pulse width is directly proportional with the average current of charge pump output.A wide up pulse makes charge pump supply with the proportional a large amount of positive current of loop filter, and a narrow dn pulse makes charge pump supply with the proportional a spot of negative current of loop filter.
The output current of charge pump has determined the output voltage ( ) of loop filter.In the reality; The HFS that loop filter is can filtering relevant with the charge pump output current (noise for example; High frequency input jiffer or the like), thus make and well follow the tracks of the reference signal phase change of no High-frequency Interference (or other undesirable interference).In addition, the output impedance meeting of charge pump influences the transfer function of loop filter.Therefore, hope that charge pump has very high output impedance.
The output voltage of loop filter (for example ) is transferred to VCO.VCO is according to clocking (Clock Signal).In the reality, the frequency of the clock signal of control VCO output.The big positive current pulses that charge pump produces can make the proportional rising in loop filter place .Conversely, of increase can make the frequency of VCO clock signal increase again.The little negative current pulse that charge pump produces can make proportional the reducing in loop filter place , reduces frequency of VCO clock signal is reduced.
Because the output current of charge pump can directly influence the frequency of VCO, guarantee needed frequency so just need make VCO be operated in a linear voltage scope of trying one's best wide.
The clock signal that voltage controlled oscillator VCO produces feeds back to phase discriminator, and through top step clock signal and reference signal is carried out synchronously.
Because the frequency of oscillation of voltage controlled oscillator VCO is by loop filter output control voltage decision; And control voltage depends on the electric current that charge pump produces, so the linear working range of charge pump CP is just very important.
The existing charge pump circuit is because the existence of electric charge in gate leakage capacitance, grid source electric capacity and the channel inversion layer of MOS switch parasitism; Will there be nonlinear problems such as leakage current, charging and discharging currents mismatch, charge pump switches time-delay mismatch, clock feedthrough in whole charge pump circuit; And these nonlinear problems can cause the shake of charge pump output voltage, and then cause the shake of VCO output frequency and reduce noiseproof feature.
Summary of the invention
Goal of the invention: the objective of the invention is to overcome the deficiency of prior art, a kind of phase-locked loop charge pump circuit that can satisfy the low current mismatch is provided.
In order to solve the problems of the technologies described above, the present invention has adopted following technical scheme:
A kind of phase-locked loop charge pump circuit of low current mismatch; It comprises current mirror and charge pump; Described charge pump comprises: the first input transmission gate : be used to receive complementary rising signals up, upb; In order to respond rising signals, transmit a corresponding output current to output node vout from power supply ; The second input transmission gate : receive complementary dropping signal dn, dnb; In order to respond dropping signal, from output node vout transmit a corresponding output current to ground gnd; Between first input transmission gate and the output node vout, be provided with cascode transistors M41, M42 has constituted article one current path; The source end of cascode transistors M41 is connected to the first input transmission gate ; Between the output node vout and second input transmission gate , be provided with cascode transistors M43, M44 has constituted the second current path; The source end of cascode transistors M44 is connected to the second input transmission gate ; Current mirror coupled is to the grid of cascode transistors M41, M42, M43, M44, transmission bias voltage V1, V2,, V3, V4 divide the grid that is clipped to cascode transistors M41, M42, M43, M44; Bias voltage V1, V2,, V3, V4 make cascode transistors M41, M42, M43, M44 be operated in the saturation region respectively.
Wherein, cascode transistors M41, M42 are the pMOS transistors; Cascode transistors M43, M44 are the nMOS transistors; Cascode transistors M41, M42, M43, M44 also can be bipolar junction transistor or mos field effect transistor.
Wherein, Described current mirror comprises FET M4a; The source class of FET M4a connects power supply ; The grounded-grid gnd of FET M4a, the drain electrode of FET M4a connects the source electrode of FET M11; The grid of FET M11 connects the drain electrode of FET M12; The drain electrode of FET M11 connects the source electrode of FET M12; The drain electrode of FET M12 connects the drain electrode of FET M5a, the source class ground connection gnd of FET M5a, the grid of FET M5a connect FET M0 grid; The source class of FET M4b connects power supply ; The grounded-grid gnd of FET M4b; The drain electrode of FET M4b connects the source electrode of FET M13; The grid of FET M13 connects the grid of FET M12; The grid of FET M13 links to each other with the drain electrode of oneself; The drain electrode of FET M13 also connects the drain electrode of FET M5b, and the grid of FET M5b connects the grid of FET M5a, the source ground gnd of FET M5a; The source class of FET M4c connects power supply ; The grounded-grid gnd of FET M4c, the drain electrode of FET M4c connects the source electrode of FET M14; The grid of FET M14 connects the grid of FET M11, and the drain electrode of FET M14 connects the source electrode of FET M15, and the grid of FET M15 connects the grid of FET M13, and the drain electrode of FET M15 connects the grid of FET M5c; The drain electrode of FET M16 connects the drain electrode of FET M15, and the grid of FET M16 connects the grid of FET M5d, and the source electrode of FET M16 connects the drain electrode of FET M5c, the source ground gnd of FET M5c; The source class of FET M4d connects power supply ; The grounded-grid gnd of FET M4d; The drain electrode of FET M4d connects the source electrode of FET M17, and the grid of FET M17 connects the grid of FET M14; The drain electrode of FET M17 connects the drain electrode of FET M5d, and the drain electrode of FET M5d is also joined the source class ground connection gnd of FET M5d with himself grid; The source class of FET M4e connects power supply ; The grounded-grid gnd of FET M4e; The drain electrode of FET M4e connects the source electrode of FET M18; The grid of FET M18 connects the drain electrode of FET M19; The drain electrode of FET M18 connects the source electrode of FET M19; The grid of FET M19 connects the grid of FET M15, M21 respectively; The drain electrode of FET M19 also connects the drain electrode of FET M22, and the grid of FET M22 connects the grid of FET M5d, M24 respectively, and the source electrode of FET M22 connects the drain electrode of FET M23; The grid of FET M23 connects the grid of FET M5c, M25 respectively; The source electrode of FET M23 connects the drain electrode of FET M5e, and the grid of FET M5e meets power supply , the source ground gnd of FET M5e; The source class of FET M4f connects power supply ; The grounded-grid gnd of FET M4f; The drain electrode of FET M4f connects the source electrode of FET M20; The grid of FET M20 connects the grid of FET M18; The drain electrode of FET M20 connects the source electrode of FET M21; The grid of FET M21 connects the grid of FET M19; The drain electrode of FET M21 connects the drain electrode of FET M24, and the source electrode of FET M24 connects the drain electrode of FET M25, and the source electrode of FET M25 connects the drain electrode of FET M5f; The grid of FET M5f meets power supply , the source ground gnd of FET M5f; The grid of FET M20 also is connected with the grid of cascode transistors M41; The grid of FET M21 also is connected with the grid of cascode transistors M42; The grid of FET M24 also is connected with the grid of cascode transistors M43, and the grid of FET M25 also is connected with the grid of cascode transistors M44.
Wherein, the FET M4a in the described current mirror, M4b, M4c, M4d, M4e, M4f, M11, M12, M13, M14, M15, M17, M18, M19, M20, M21 are the P-type mos field-effect transistor; FET M0, M5a, M5b, M5c, M5d, M5e, M5f, M16, M22, M23, M24, M25 are N type metal oxide semiconductor field-effect transistor.
Wherein, P-type mos field-effect transistor in the said current mirror and N type metal oxide semiconductor field-effect transistor are provided with according to following formula, so that produce bias voltage V1, V2, V3, V4:
Wherein, represents supply voltage; The threshold voltage of the P-type mos field-effect transistor of representative in current mirror, the threshold voltage of the N type metal oxide semiconductor field-effect transistor of representative in current mirror; represents the grid source overdrive voltage of the P-type mos field-effect transistor in the current mirror, and represents the grid source overdrive voltage of the N type metal oxide semiconductor field-effect transistor in the current mirror.
Wherein, current mirror is connected to bias voltage V1, V2, V3, V4 the grid of cascode transistors M41, M42, M43, M44 respectively through first node N31, second node N32, the 3rd node N33, the 4th node N34.
Operation principle: the charge pump circuit that is operated in the wide range of linearity comprises a current mirror and some cascode transistors, and current mirror is used for cascode transistors is setovered and made it be operated in the saturation region.Charge pump comprises controlled first an input transmission gate and receives the up signal, from the output current of a correspondence of power delivery to output node.Charge pump also comprises the second controlled input transmission gate of another one and receives the dn signal, produces an output current corresponding from the output node to ground.In addition; Charge pump also comprises cascode transistors M1, M2, and these two transistors are on the current path between the first input transmission gate and the output; Cascode transistors M3, M4 are between the output node and the second input transmission gate .Current mirror is respectively the bias voltage V1 that produces, V2, and V3, V4 are coupled on the grid of cascode transistors M1, M2, M3, M4.
Current mirror in the charge pump comprises the P-type mos field-effect transistor (PMOS transistor) and the N type metal oxide semiconductor field-effect transistor (nmos pass transistor) of certain breadth length ratio.The breadth length ratio of PMOS transistor and nmos pass transistor has defined V1, V2, and V3, the bias voltage of V4, and V1, V2, V3, the bias voltage of V4 make cascode transistors M1, M2, M3, M4 be operated in the saturation region again respectively.Through using cascodes can increase the output impedance of charge pump, be that cascode transistors provides the biased electrical pressure energy to make it be operated in the saturation region through a current mirror, in the hope of making charge pump that maximum output voltage swing arranged.
Beneficial effect: the output impedance that (1) cascode transistors M41~M44 of the present invention makes charge pump to obtain one at output node to be approximately equal to makes the scope of output voltage be: .The output impedance of the charge pump circuit of the general cascodes of no use of comparing ; Magnitude that output impedance of the present invention is big, thereby can obtain a less mismatch current.
(2) charge pump current is lower, generally is 20uA-100uA.
(3) the present invention adopts source end switch type charge pump construction, and charge pump switches does not directly link to each other with output, and the cascode transistors M41 ~ M44 of adding is in saturation region or cut-off region all the time, makes charge pump switches receive the influence of effect such as electric charge injection hardly.Because switch is only linked transistorized source end, and the parasitic capacitance of source electrode is less than the parasitic capacitance on the grid, so can effectively reduce nonlinear problem.
Description of drawings
Fig. 1 is the schematic diagram of existing phase-locked loop circuit.
Fig. 2 is the connection sketch map of the phase-locked loop charge pump circuit of low current mismatch of the present invention.
Fig. 3 is a charge pump current matching properties curve.
Embodiment:
Below in conjunction with accompanying drawing the present invention is done explanation further.
As shown in Figure 2, the phase-locked loop charge pump circuit of low current mismatch of the present invention comprises charge pump circuit and current mirroring circuit.
Wherein, Charge pump comprises cascode transistors M41, M42, M43, M44, and the first input transmission gate , second is imported transmission gate .Pump through the first input transmission gate , the second input transfer gate accepts up and dn error correction signal; and output current , corresponds to the output node vout of the error correction signal, for example, an up signal generates a positive , a dn signal generates a Negative .
Switch adopts the transmission gate that is driven by a pair of complementary clock signal to realize: the first input transmission gate , second is imported transmission gate , thereby eliminates or alleviate the clock feed-through effect of charge pump switches.And because switch is connected to the low-impedance node of MOS transistor source end, make metal-oxide-semiconductor in the current mirror only be in by or saturation condition.So this charge pump can be avoided the electric charge injection effect.Simultaneously, when being turned off owing to switch, the output node of charge pump is not unsettled, so, when charge pump switches transfers " opening " to by " pass ", electric charge can not take place between parasitic capacitance in the charge pump and the output node share.And; When the first input transmission gate , when the second input transmission gate carries out the on off state switching; The current spikes that is produced at cascode transistors M41 or M44 source end can not be directly delivered to output node; Because when burr takes place, cascode transistors M42 or M43 also are in cut-off state.Simultaneously, owing to can come the rise and fall time of Control current pulse through the RC time constant of regulating current source transistor M41 or M44 source end, so also smoothly conducting of current source transistor M41~M44.
Current mirror makes cascode transistors M41~M44 be operated in the saturation region for cascode transistors M41-M44 provides bias voltage, and this saturation region covers the maximum output voltage amplitude of oscillation of charge pump as far as possible.When cascode transistors M41~M44 was operated in the saturation region, (for first approximation) electric output stream just can not depend on the output voltage of loop filter.Therefore, M41~M44 is operated in the saturation region when cascode transistors, and the attribute of filter (such as transfer function) just can not receive the influence of charge pump.
As shown in Figure 2; Described current mirror comprises FET M4a; The source class of FET M4a connects power supply ; The grounded-grid gnd of FET M4a, the drain electrode of FET M4a connects the source electrode of FET M11; The grid of FET M11 connects the drain electrode of FET M12; The drain electrode of FET M11 connects the source electrode of FET M12; The drain electrode of FET M12 connects the drain electrode of FET M5a, the source class ground connection gnd of FET M5a, the grid of FET M5a connect FET M0 grid; FET M0 constitutes current-mirror structure with FET M5a and links to each other with current source.
The source class of FET M4b connects power supply ; The grounded-grid gnd of FET M4b; The drain electrode of FET M4b connects the source electrode of FET M13; The grid of FET M13 connects the grid of FET M12; The grid of FET M13 links to each other with the drain electrode of oneself; The drain electrode of FET M13 also connects the drain electrode of FET M5b, and the grid of FET M5b connects the grid of FET M5a, the source ground gnd of FET M5a.
The source class of FET M4c connects power supply ; The grounded-grid gnd of FET M4c, the drain electrode of FET M4c connects the source electrode of FET M14; The grid of FET M14 connects the grid of FET M11, and the drain electrode of FET M14 connects the source electrode of FET M15, and the grid of FET M15 connects the grid of FET M13, and the drain electrode of FET M15 connects the grid of FET M5c; The drain electrode of FET M16 connects the drain electrode of FET M15, and the grid of FET M16 connects the grid of FET M5d, and the source electrode of FET M16 connects the drain electrode of FET M5c, the source ground gnd of FET M5c.
The source class of FET M4d connects power supply ; The grounded-grid gnd of FET M4d; The drain electrode of FET M4d connects the source electrode of FET M17, and the grid of FET M17 connects the grid of FET M14; The drain electrode of FET M17 connects the drain electrode of FET M5d, and the drain electrode of FET M5d is also joined the source class ground connection gnd of FET M5d with himself grid.
The source class of FET M4e connects power supply ; The grounded-grid gnd of FET M4e; The drain electrode of FET M4e connects the source electrode of FET M18; The grid of FET M18 connects the drain electrode of FET M19; The drain electrode of FET M18 connects the source electrode of FET M19; The grid of FET M19 connects the grid of FET M15, M21 respectively; The drain electrode of FET M19 also connects the drain electrode of FET M22, and the grid of FET M22 connects the grid of FET M5d, M24 respectively, and the source electrode of FET M22 connects the drain electrode of FET M23; The grid of FET M23 connects the grid of FET M5c, M25 respectively; The source electrode of FET M23 connects the drain electrode of FET M5e, and the grid of FET M5e meets power supply , the source ground gnd of FET M5e.
The source class of FET M4f connects power supply ; The grounded-grid gnd of FET M4f; The drain electrode of FET M4f connects the source electrode of FET M20; The grid of FET M20 connects the grid of FET M18; The drain electrode of FET M20 connects the source electrode of FET M21; The grid of FET M21 connects the grid of FET M19; The drain electrode of FET M21 connects the drain electrode of FET M24, and the source electrode of FET M24 connects the drain electrode of FET M25, and the source electrode of FET M25 connects the drain electrode of FET M5f; The grid of FET M5f meets power supply , the source ground gnd of FET M5f.
The grid of FET M20 also is connected with the grid of cascode transistors M41; The grid of FET M21 also is connected with the grid of cascode transistors M42; The grid of FET M24 also is connected with the grid of cascode transistors M43, and the grid of FET M25 also is connected with the grid of cascode transistors M44.
Topological structure and element that current mirror is selected make it can produce bias voltage V1~V4; These bias voltages are biased to certain a bit with cascode transistors M41~M44; This point makes that the scope of output voltage is maximum, and the work of charge pump in the scope that very big output impedance is arranged is just as a current source.Current mirror comprises a plurality of P-type mos field-effect transistors (PMOS transistor) and a plurality of N type metal oxide semiconductor field-effect transistors (nmos pass transistor).The size of the field-effect transistor in current mirror is set to suitable value with bias voltage V1~V4, makes cascode transistors M41~M44 be operated in the saturation region, and covers the maximum amplitude of oscillation of output voltage.
The size of bias voltage V1~V4 mainly is by PMOS transistor and nmos pass transistor breadth length ratio decision separately.
Each transistor among cascode transistors M41~M44 can be the transistor of any kind, as long as it is just passable to constitute the cascodes of charge pump.For example; Cascode transistors M41, M42 are the PMOS transistors; Connect first input transmission gate and the output node vout; Cascode transistors M43, M44 are nmos pass transistors, connect second input transmission gate and output node vout.
Cascode transistors M41~M44 also can be a bipolar junction transistor (BJTs), or mos field effect transistor (MOSFETs), or the combination of BJTs and MOSFETs.
FET M4a~M4f in the current mirroring circuit, M11~M15, M17~M21 are the PMOS transistor, FET M0, M5a~M5f, M16, M22~M25 are nmos pass transistor.
PMOS transistor in the current mirror and nmos pass transistor have constituted the branch road that transmits electric current in the current mirror: L5a, L5b, L5c, L5d, L5e and L5f equal the current amplitude of each branch road the current mirror from power supply to the electric current of output node vout.
Each field-effect transistor and power supply in the current mirror provide bias voltage V1~V4 to cascode transistors M41~M44.Field effect transistor M 11~M20 provides bias voltage V1, V2 to node N31, N32 respectively.In addition, field effect transistor M 21~M25 provides bias voltage V3, V4 to node N33, N34 respectively.Conversely, node N31~N34 transmits bias voltage V1~V4 to the grid of cascode transistors M41~M44.
The characteristic of PMOS transistor M4a~M4f simulation first input transmission gate , the characteristic of nmos pass transistor M5a~M5f simulation second input transmission gate .For example; PMOS transistor M4e, M4f and have same pressure drop; Nmos pass transistor M5e, M5f have identical pressure drop with switch transmission gate , so each branch road of current mirror has identical electric current.
For example: PMOS transistor M11, M14, M17 and PMOS transistor M18, M20 breadth length ratio (being designated as 10Wp) are identical, and PMOS transistor M12, M15 and PMOS transistor M19, M21 breadth length ratio (being designated as 30Wp) are identical, and the breadth length ratio of M13 is 2.5Wp; Equally; The breadth length ratio of nmos pass transistor M16, M22, M24 (20Wn) is identical; The breadth length ratio of nmos pass transistor M0, M5a, M5b, M5c (being designated as 5Wn) is identical, and the breadth length ratio (being designated as 10Wn) of nmos pass transistor M23 and M25 is identical, and the breadth length ratio of nmos pass transistor M5d is 2Wn; PMOS transistor M4a~M4f has identical breadth length ratio and guarantees that its pressure drop is identical with the pressure drop of first transmission gate , and the breadth length ratio of nmos pass transistor M5e and M5f is identical and guarantee that its pressure drop is identical with the pressure drop of second transmission gate .
The flow through branch road of current mirror of electric current that transistorized size makes same magnitude is set like this, makes current mirror produce bias voltage V1-V4 as follows:
Wherein, represents supply voltage; represents the transistorized threshold voltage of PMOS, the for example threshold voltage of PMOS transistor M12 first approximation; represents the threshold voltage of nmos pass transistor, for example the first approximation threshold voltage of transistor M19; represents the transistorized grid of PMOS source overdrive voltage in the current mirror, and represents the grid source overdrive voltage of current mirror nmos pass transistor. , can be left in the basket, and needn't be included in the calculating of overdrive voltage.In addition, , are negative values.When transistor M11~M22 is provided with size according to top voltage equality; The electric current that flows through the current mirror branch road so is exactly identical, and charge pump will keep linear voltage power supply scope .It is exactly the amplitude of oscillation maximization that makes charge pump accordingly with increasing V3 that above-mentioned equality reduces V2.
Charge pump can be placed on on the chip piece with cascode transistors M41~M44.Through with current mirror this locality bias voltage V1~V4 being provided, charge pump can be followed the tracks of the variation of process voltage temperature (PVT).Bias voltage V1~V4 can change under the different processes angle, and this can influence the size through charge pump current.The bias voltage (for example V1 and V4) bottom regulating and the bias voltage (for example V1 and V4) at top; According to top given equality; Current mirror can improve the amplitude of oscillation of output voltage ( ) to greatest extent under every kind of PVT situation; Like this; Just can make the frequency range maximization automatically, system (PLL) just well follows the tracks of phase of input signals.
The drain terminal voltage mirror image of the pMOS transistor on current mirror (such as transistor M11) becomes the drain terminal voltage of cascode transistors M41.The drain terminal voltage mirror image of the transistor below the current mirror (such as transistor M5c) becomes the drain terminal voltage of cascode transistors M44.Through the drain terminal voltage of mirrored transistor M11 and the drain terminal voltage of cascode transistors M41; With the drain terminal voltage of mirrored transistor M5c and the drain terminal voltage of cascode transistors M44; Charge pump can reduce or eliminate current error in the current mirror branch road; Because the drain-source voltage of transistor M11 and cascode transistors M41 does not match, and the drain-source voltage of transistor M5c and cascode transistors M44 does not match.For example; Be mirrored onto the drain terminal of cascode transistors M41 when the drain terminal voltage of transistor M11; The electric current of L5a and L5b branch road should be identical or much at one, this electric current is to output node vout (branch road that promptly comprises cascode transistors M41 and M42) from power supply .Equally; Be mirrored onto the drain terminal of cascode transistors M44 when the drain terminal voltage of transistor M5c; The electric current of L5e and L5f branch road should be identical or much at one, this electric current be from output node vout to ground gnd (branch road that promptly comprises cascode transistors M43 and M44).Through reducing or eliminating the electric current difference in the current mirror branch road, the gain error of charge pump will reduce or eliminate.
Like this; The output impedance that cascode transistors M41~M44 makes charge pump to obtain one at output node to be approximately equal to makes the scope of output voltage ( ) be: .
Wherein and represents mutual conductance and the output impedance of cascode transistors M41 and M42; and represents mutual conductance and the output impedance of cascode transistors M43 and M44, and its output voltage scope is .
Fig. 3 is a charge pump current matching properties curve of the present invention, and charging and discharging currents is respectively 106.783uA and 106.419uA, and mismatch is merely 0.364uA.Wherein abscissa is represented voltage range, and ordinate is represented the charging and discharging currents amplitude.
The high output impedance of charge pump, linear working range, low relatively gain error, perhaps both have both at the same time, and make system (PLL) under relatively little charge pump current condition, to work.In specific embodiments, charge pump possibly be used in PLLs and clock and data recovery (CDR) circuit with loop filter on the sheet together.In the reality, charge pump is also used deep-submicron CMOS process design, and this technology makes transistor that lower output impedance and lower supply voltage arranged.

Claims (7)

1. the phase-locked loop charge pump circuit of a low current mismatch, it comprises current mirror and charge pump, it is characterized in that: described charge pump comprises:
The first input transmission gate : be used to receive complementary rising signals up, upb; In order to respond rising signals, transmit a corresponding output current to output node vout from power supply ;
The second input transmission gate : receive complementary dropping signal dn, dnb; In order to respond dropping signal, from output node vout transmit a corresponding output current to ground gnd;
Between first input transmission gate and the output node vout, be provided with cascode transistors M41, M42 has constituted article one current path; The source end of cascode transistors M41 is connected to the first input transmission gate ;
Between the output node vout and second input transmission gate , be provided with cascode transistors M43, M44 has constituted the second current path; The source end of cascode transistors M44 is connected to the second input transmission gate ;
Current mirror coupled is to the grid of cascode transistors M41, M42, M43, M44, transmission bias voltage V1, V2,, V3, V4 divide the grid that is clipped to cascode transistors M41, M42, M43, M44; Bias voltage V1, V2,, V3, V4 make cascode transistors M41, M42, M43, M44 be operated in the saturation region respectively.
2. the phase-locked loop charge pump circuit of a kind of low current mismatch according to claim 1 is characterized in that: cascode transistors M41, M42 are the pMOS transistors; Cascode transistors M43, M44 are the nMOS transistors.
3. the phase-locked loop charge pump circuit of a kind of low current mismatch according to claim 1 is characterized in that: cascode transistors M41, M42, M43, M44 are bipolar junction transistor or mos field effect transistor.
4. according to the phase-locked loop charge pump circuit of claim 1,2 or 3 described a kind of low current mismatches; It is characterized in that: described current mirror comprises FET M4a; The source class of FET M4a connects power supply ; The grounded-grid gnd of FET M4a, the drain electrode of FET M4a connects the source electrode of FET M11; The grid of FET M11 connects the drain electrode of FET M12; The drain electrode of FET M11 connects the source electrode of FET M12; The drain electrode of FET M12 connects the drain electrode of FET M5a, the source class ground connection gnd of FET M5a, the grid of FET M5a connect FET M0 grid;
The source class of FET M4b connects power supply ; The grounded-grid gnd of FET M4b; The drain electrode of FET M4b connects the source electrode of FET M13; The grid of FET M13 connects the grid of FET M12; The grid of FET M13 links to each other with the drain electrode of oneself; The drain electrode of FET M13 also connects the drain electrode of FET M5b, and the grid of FET M5b connects the grid of FET M5a, the source ground gnd of FET M5a;
The source class of FET M4c connects power supply ; The grounded-grid gnd of FET M4c, the drain electrode of FET M4c connects the source electrode of FET M14; The grid of FET M14 connects the grid of FET M11, and the drain electrode of FET M14 connects the source electrode of FET M15, and the grid of FET M15 connects the grid of FET M13, and the drain electrode of FET M15 connects the grid of FET M5c; The drain electrode of FET M16 connects the drain electrode of FET M15, and the grid of FET M16 connects the grid of FET M5d, and the source electrode of FET M16 connects the drain electrode of FET M5c, the source ground gnd of FET M5c;
The source class of FET M4d connects power supply ; The grounded-grid gnd of FET M4d; The drain electrode of FET M4d connects the source electrode of FET M17, and the grid of FET M17 connects the grid of FET M14; The drain electrode of FET M17 connects the drain electrode of FET M5d, and the drain electrode of FET M5d is also joined the source class ground connection gnd of FET M5d with himself grid;
The source class of FET M4e connects power supply ; The grounded-grid gnd of FET M4e; The drain electrode of FET M4e connects the source electrode of FET M18; The grid of FET M18 connects the drain electrode of FET M19; The drain electrode of FET M18 connects the source electrode of FET M19; The grid of FET M19 connects the grid of FET M15, M21 respectively; The drain electrode of FET M19 also connects the drain electrode of FET M22, and the grid of FET M22 connects the grid of FET M5d, M24 respectively, and the source electrode of FET M22 connects the drain electrode of FET M23; The grid of FET M23 connects the grid of FET M5c, M25 respectively; The source electrode of FET M23 connects the drain electrode of FET M5e, and the grid of FET M5e meets power supply , the source ground gnd of FET M5e;
The source class of FET M4f connects power supply ; The grounded-grid gnd of FET M4f; The drain electrode of FET M4f connects the source electrode of FET M20; The grid of FET M20 connects the grid of FET M18; The drain electrode of FET M20 connects the source electrode of FET M21; The grid of FET M21 connects the grid of FET M19; The drain electrode of FET M21 connects the drain electrode of FET M24, and the source electrode of FET M24 connects the drain electrode of FET M25, and the source electrode of FET M25 connects the drain electrode of FET M5f; The grid of FET M5f meets power supply , the source ground gnd of FET M5f;
The grid of FET M20 also is connected with the grid of cascode transistors M41; The grid of FET M21 also is connected with the grid of cascode transistors M42; The grid of FET M24 also is connected with the grid of cascode transistors M43, and the grid of FET M25 also is connected with the grid of cascode transistors M44.
5. the phase-locked loop charge pump circuit of a kind of low current mismatch according to claim 4; It is characterized in that: the FET M4a in the described current mirror, M4b, M4c, M4d, M4e, M4f, M11, M12, M13, M14, M15, M17, M18, M19, M20, M21 are the P-type mos field-effect transistor; FET M0, M5a, M5b, M5c, M5d, M5e, M5f, M16, M22, M23, M24, M25 are N type metal oxide semiconductor field-effect transistor.
6. the phase-locked loop charge pump circuit of a kind of low current mismatch according to claim 5; It is characterized in that: P-type mos field-effect transistor in the said current mirror and N type metal oxide semiconductor field-effect transistor are provided with according to following formula, so that produce bias voltage V1, V2, V3, V4:
Wherein, represents supply voltage; The threshold voltage of the P-type mos field-effect transistor of representative in current mirror, the threshold voltage of the N type metal oxide semiconductor field-effect transistor of representative in current mirror; represents the grid source overdrive voltage of the P-type mos field-effect transistor in the current mirror, and represents the grid source overdrive voltage of the N type metal oxide semiconductor field-effect transistor in the current mirror.
7. the phase-locked loop charge pump circuit of a kind of low current mismatch according to claim 1 is characterized in that: current mirror is connected to bias voltage V1, V2, V3, V4 the grid of cascode transistors M41, M42, M43, M44 respectively through first node N31, second node N32, the 3rd node N33, the 4th node N34.
CN2012101430351A 2012-05-10 2012-05-10 Phase-locked loop charge pump circuit with low current mismatch Pending CN102664520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012101430351A CN102664520A (en) 2012-05-10 2012-05-10 Phase-locked loop charge pump circuit with low current mismatch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012101430351A CN102664520A (en) 2012-05-10 2012-05-10 Phase-locked loop charge pump circuit with low current mismatch

Publications (1)

Publication Number Publication Date
CN102664520A true CN102664520A (en) 2012-09-12

Family

ID=46773958

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012101430351A Pending CN102664520A (en) 2012-05-10 2012-05-10 Phase-locked loop charge pump circuit with low current mismatch

Country Status (1)

Country Link
CN (1) CN102664520A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103490626A (en) * 2013-09-30 2014-01-01 中国科学技术大学 Charge pump based on shunt feedback
CN103986464A (en) * 2014-05-22 2014-08-13 无锡中科微电子工业技术研究院有限责任公司 Self-calibration device and method for loop parameters of phase-locked loop
CN107070205A (en) * 2017-05-10 2017-08-18 湘潭大学 A kind of new charge pump circuit
CN109656305A (en) * 2015-10-01 2019-04-19 意法半导体(鲁塞)公司 Method for the electric current smoothly consumed by integrated circuit and corresponding equipment
CN109951064A (en) * 2017-12-21 2019-06-28 美格纳半导体有限公司 High voltage startup circuit and switched-mode power supply
TWI718679B (en) * 2019-07-05 2021-02-11 台達電子國際(新加坡)私人有限公司 Charge-based charge pump with wide output voltage range

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1212553C (en) * 2002-01-03 2005-07-27 阿尔卡塔尔公司 Electric charge pump with wide output voltage area
CN101222226A (en) * 2007-01-10 2008-07-16 中国科学院微电子研究所 Self-calibration charge pump circuit used for phase-locked loop and its self-calibration feedback loop
CN101237234A (en) * 2007-01-30 2008-08-06 立积电子股份有限公司 Fast turn on and off speed in PLL cascoded charge pump
CN101488710A (en) * 2008-10-22 2009-07-22 成都国腾电子技术股份有限公司 A charge pump circuit
CN202617095U (en) * 2012-05-10 2012-12-19 东南大学 Phase locked loop charge pump circuit with low current mismatch

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1212553C (en) * 2002-01-03 2005-07-27 阿尔卡塔尔公司 Electric charge pump with wide output voltage area
CN101222226A (en) * 2007-01-10 2008-07-16 中国科学院微电子研究所 Self-calibration charge pump circuit used for phase-locked loop and its self-calibration feedback loop
CN101237234A (en) * 2007-01-30 2008-08-06 立积电子股份有限公司 Fast turn on and off speed in PLL cascoded charge pump
CN101488710A (en) * 2008-10-22 2009-07-22 成都国腾电子技术股份有限公司 A charge pump circuit
CN202617095U (en) * 2012-05-10 2012-12-19 东南大学 Phase locked loop charge pump circuit with low current mismatch

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103490626A (en) * 2013-09-30 2014-01-01 中国科学技术大学 Charge pump based on shunt feedback
CN103986464A (en) * 2014-05-22 2014-08-13 无锡中科微电子工业技术研究院有限责任公司 Self-calibration device and method for loop parameters of phase-locked loop
CN103986464B (en) * 2014-05-22 2017-08-29 无锡中科微电子工业技术研究院有限责任公司 A kind of cycle of phase-locked loop parameter self-calibrating device and method
CN109656305A (en) * 2015-10-01 2019-04-19 意法半导体(鲁塞)公司 Method for the electric current smoothly consumed by integrated circuit and corresponding equipment
CN109656305B (en) * 2015-10-01 2020-11-24 意法半导体(鲁塞)公司 Method for smoothing the current consumed by an integrated circuit and corresponding device
CN107070205A (en) * 2017-05-10 2017-08-18 湘潭大学 A kind of new charge pump circuit
CN107070205B (en) * 2017-05-10 2019-09-20 湘潭大学 A kind of new charge pump circuit
CN109951064A (en) * 2017-12-21 2019-06-28 美格纳半导体有限公司 High voltage startup circuit and switched-mode power supply
CN109951064B (en) * 2017-12-21 2021-01-05 美格纳半导体有限公司 High-voltage starting circuit and switch mode power supply
TWI718679B (en) * 2019-07-05 2021-02-11 台達電子國際(新加坡)私人有限公司 Charge-based charge pump with wide output voltage range

Similar Documents

Publication Publication Date Title
CN102664520A (en) Phase-locked loop charge pump circuit with low current mismatch
US9787178B2 (en) Current mirror circuit and charge pump circuit
CN101588178B (en) Self-biased phase-locked loop
US6717478B1 (en) Multi-phase voltage controlled oscillator (VCO) with common mode control
US20080191783A1 (en) Symmetric charge pump replica bias detector
CN103346784B (en) A kind of matching type charge pump circuit for phase-locked loop
US7705640B2 (en) Common-mode feedback method using a current starved replica biasing
CN102843132B (en) A kind of low-voltage voltage controlled oscillator that can suppress power supply noise
CN102710124B (en) Charge pump circuit
CN202617095U (en) Phase locked loop charge pump circuit with low current mismatch
TW201246764A (en) Charge pump circuit
US7816975B2 (en) Circuit and method for bias voltage generation
CN202617065U (en) Low voltage voltage-controlled oscillator capable of restraining power supply noise
US7688122B2 (en) Charge pump with cascode biasing
CN103368381A (en) Circuit, wireless communication unit and current control method
CN104135277B (en) Reference clock produces circuit and method on a kind of piece
US7053684B1 (en) Reduced jitter charge pumps and circuits and systems utilizing the same
US20180115239A1 (en) Differential charge pump with extended output control voltage range
CN103812503A (en) Differential delay unit circuit and ring oscillator
CN104811189A (en) Charge pump circuit in charge pump phase-locked loop
CN104821825A (en) Wide tuning range ring voltage-controlled oscillator
Sai et al. A low-jitter clock generator based on ring oscillator with 1/f noise reduction technique for next-generation mobile wireless terminals
CN204928798U (en) Developments are filled discharge current and are matchd charge pump circuit
CN101425803B (en) Voltage controlled oscillator for loop circuit
CN104242923A (en) Voltage-controlled oscillator

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120912

C02 Deemed withdrawal of patent application after publication (patent law 2001)