CN210724717U - Orthogonal local oscillator signal generating device with duty ratio of 25% - Google Patents

Abstract

The utility model discloses a duty ratio is 25% quadrature local oscillator signal generating device, cascade through adopting two D latches that the structure is the same and form the negative feedback loop, realize that the duty ratio is 25% local oscillator signal's production, the phase difference of still having guaranteed two way local oscillator signals of IQ simultaneously is 90 degrees, it needs at first to produce the duty ratio signal through the duty ratio to have solved prior art, then it is big to lead to wireless receiver's consumption according to the method that phase calibration module carried out calibration to the duty ratio signal, bulky scheduling problem, still can solve the problem that the local oscillator signal leads to the duty ratio grow behind the phase calibration module simultaneously.

Description

Orthogonal local oscillator signal generating device with duty ratio of 25%

Technical Field

The utility model discloses the wireless communication circuit field especially relates to a duty cycle is 25% quadrature local oscillator signal generating device.

Background

The passive mixer has no advantages of direct current power consumption, low noise and good linearity, and is widely applied to modern integrated wireless receivers, especially low intermediate frequency and zero intermediate frequency receivers. The local oscillator signal is a necessary signal of the mixer, the duty ratio of the local oscillator signal has a very important influence on the wireless receiving performance of the passive mixer, the smaller the local oscillator duty ratio is, the larger the gain and the smaller the noise can be obtained by the wireless receiver, but when the local oscillator frequency is higher, the local oscillator with the small duty ratio is difficult to realize, because the local oscillator signal with the duty ratio of 25% is usually adopted.

In addition, the modern wireless receiver can adopt a complex frequency mixing mode to carry out image interference suppression. And IQ two local oscillator signals with a phase difference of 90 degrees need to be generated for realizing complex frequency mixing, if the phase difference of the IQ two local oscillator signals deviates from 90 degrees, the image rejection performance of the wireless receiver is affected, and thus, the phase difference of the IQ two local oscillator signals needs to be calibrated to 90 degrees by some methods.

Generally speaking, the method for generating the IQ two-path local oscillator signals with a duty ratio of 25% is to first generate IQ two-path signals with a duty ratio of 50% by using a first-stage frequency divider, then shape the waveform with a duty ratio of 50% into signals with a duty ratio of 25% by using a waveform shaping circuit, and finally calibrate the phases of the IQ two-path local oscillator signals to 90 degrees by using an IQ phase calibration module; or a first-stage frequency divider is adopted to directly generate IQ two-path signals with 25% duty ratio, and finally the phases of the IQ two-path local oscillation signals are calibrated to 90 degrees through an IQ phase calibration module. In both methods, the frequency divider needs to generate corresponding local oscillator signals first, and then the local oscillator signals pass through the additional phase calibration module to calibrate the phase difference of the two local oscillator signals to 90 degrees, so that the power consumption and the volume of the wireless receiver are increased, and meanwhile, the duty ratio of the local oscillator signals is easily damaged after passing through the final phase calibration module, so that the duty ratio is increased, and the generation of the local oscillator signals is finally influenced.

SUMMERY OF THE UTILITY MODEL

In order to overcome the defects of the prior art, the utility model aims to provide a duty cycle is 25% quadrature local oscillator signal generating device, can solve the big scheduling problem of consumption that local oscillator signal produced among the prior art.

This the utility model discloses an aim at adopts following technical scheme to realize:

an orthogonal local oscillator signal generating device with a duty ratio of 25%, which comprises a first D latch, a second D latch, a differential clock input positive end, a differential clock input negative end, an I local oscillator signal output positive end, an I local oscillator signal output negative end, a Q local oscillator signal output positive end and a Q local oscillator signal output negative end;

the first D latch and the second D latch are respectively provided with a clock signal input end, a data input positive end, a data input negative end, a data output positive end and a data output negative end;

the clock signal input end of the first D latch is connected with the positive end of the differential clock input and used for inputting a first differential clock input signal; the clock signal input end of the second D latch is connected with the negative end of the differential clock input and is used for inputting a second differential clock input signal;

the data input negative end of the first D latch is connected with the data output positive end of the second D latch to serve as a Q-path differential local oscillation signal output positive end and output a Q-path first local oscillation signal;

the positive data input end of the first D latch is connected with the negative data output end of the second D latch, and the positive data input end of the first D latch serves as the negative Q-path differential local oscillation signal output end and outputs Q-path second local oscillation signals;

the positive data output end of the first D latch is connected with the positive data input end of the second D latch to serve as the positive output end of the I-path differential local oscillation signal and output the I-path first local oscillation signal;

and the data output negative end of the first D latch is connected with the data input negative end of the second D latch, and is used as the output negative end of the I-path differential local oscillation signal and outputs the I-path second local oscillation signal.

Furthermore, the first D latch and the second D latch further include controllable switch control ends, the controllable switch control end of the first D latch is used for inputting the I-path local oscillator signal phase calibration signal, and the controllable switch control end of the second D latch is used for inputting the Q-path local oscillator signal phase calibration signal; the local oscillator signal generating device changes the working state of the controllable switch of the first D latch and/or the second D latch by changing the phase calibration signal of the local oscillator signal of the I path and/or the phase calibration signal of the local oscillator signal of the Q path, and further changes the phase of the local oscillator signal of the I path and/or the phase of the local oscillator signal of the Q path, so that the phase calibration of the local oscillator signals of the IQ path is realized.

Further, the first D latch and the second D latch each include: the differential input pair tube, the latch pair tube, the clock pair tube and the controllable switch;

the differential pair transistors comprise a first NMOS transistor and a second NMOS transistor, the latch pair transistors comprise a third NMOS transistor and a fourth NMOS transistor, the clock pair transistors comprise a first PMOS transistor and a second PMOS transistor, and the controllable switches comprise a first controllable switch and a second controllable switch;

the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are used as clock signal input ends, and the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected to a power supply; the drain electrode of the first PMOS tube is connected with the positive end of the first controllable switch, and the drain electrode of the second PMOS tube is connected with the positive end of the second controllable switch;

the drain electrode of the first NMOS tube, the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are connected with the negative end of the first controllable switch and serve as the negative end of data output; the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the third NMOS tube are connected with the negative end of the second controllable switch and used as the positive end of data output;

the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are all grounded; the grid electrode of the first NMOS tube is used as a positive data input end; the grid electrode of the second NMOS tube is used as the negative end of the data output;

the control ends of the first controllable switch and the second controllable switch are connected to serve as the control ends of the controllable switches.

Furthermore, the first controllable switch and the second controllable switch are both composed of N PMOS tubes, wherein N is greater than 1, and N is a natural number; the source electrodes of all PMOS tubes of each controllable switch are connected to serve as the positive end of the corresponding controllable switch, and the drain electrodes of all PMOS tubes are connected to serve as the negative end of the corresponding controllable switch; and the grid electrode of each PMOS tube of the first controllable switch and the grid electrode of each PMOS tube of the second controllable switch are connected with each other to be used as a control end of the controllable switch and used for inputting a local oscillator signal phase calibration signal.

Further, during the operation of each D latch, at least one of the PMOS tubes of each controllable switch is in a conducting state.

Further, the first PMOS transistor and the second PMOS transistor have the same design parameters, the first NMOS transistor and the second NMOS transistor have the same design parameters, and the third NMOS transistor and the fourth NMOS transistor have the same design parameters.

Compared with the prior art, the beneficial effects of the utility model reside in that:

the utility model discloses an adopt two D latches that the structure is the same to cascade and form the negative feedback loop, realize that the duty cycle is 25% local oscillator signal's production, solved prior art and need at first produce the module through the duty cycle and generate the duty cycle signal for the chip consumption is big, bulky scheduling problem.

Drawings

Fig. 1 is a circuit diagram of a local oscillator signal generating device with a duty ratio of 25% according to the present invention;

FIG. 2 is a circuit block diagram of latch D1 and latch D2 of FIG. 1;

FIG. 3 is a circuit block diagram of the first controllable switch and the second controllable switch of FIG. 2;

fig. 4 is a signal waveform diagram of the local oscillator signal generating device with phase calibration according to the present invention;

fig. 5 is a corresponding relationship between the phase calibration signals of the Q local oscillator signals and the I local oscillator signals when N is 4;

fig. 6 is the utility model provides a when N is 4, the corresponding relation between Q way local oscillator signal and Q way local oscillator signal phase calibration signal.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that the embodiments or technical features described below can be arbitrarily combined to form a new embodiment without conflict.

The first embodiment is as follows:

because IQ two-path signals with the duty ratio of 25% are firstly generated in the prior art, and then the IQ two-path signals are subjected to phase calibration by an IQ phase calibration module, the method not only needs an additional phase calibration module, but also increases the power consumption and the volume of the wireless receiver, and the duty ratio of the calibrated signals is easy to change.

As shown in FIG. 1, the utility model provides a duty cycle is 25% quadrature local oscillator signal generating device, including two latches that the structure is the same, difference input clock positive terminal, difference input clock negative terminal and I way difference local oscillator signal output part, Q way difference local oscillator signal output part.

Wherein, the utility model discloses a latch be the D latch, every D latch all includes clock signal input end CLK, the positive terminal DP of data input, data input negative terminal DN, the positive terminal OP of data output and the negative terminal ON of data output.

The Q-path differential local oscillator signal output end comprises a Q-path differential local oscillator signal output positive end and a Q-path differential local oscillator signal output negative end, and the I-path differential local oscillator signal output end comprises an I-path differential local oscillator signal output positive end and an I-path differential local oscillator signal output negative end.

The utility model discloses a cascade two D latches and form the negative feedback loop, produce the orthogonal local oscillator signal that the duty cycle is 25%, its specific connected mode is:

the clock signal input terminal CLK of the first D latch D1 is connected to the positive differential clock input terminal for inputting the first differential clock signal CLKP. The clock signal input terminal CLK of the second D-latch D2 is connected to the differential clock input negative terminal for inputting the second differential clock signal CLKN.

The negative data input terminal DN of the first D-latch D1 is connected to the positive data output terminal OP of the second D-latch D2, and is used as the positive output terminal of the Q-path differential local oscillation signal and outputs a Q-path first local oscillation signal LOQP.

The positive data input terminal DP of the first D-latch D1 is connected to the negative data output terminal ON of the second D-latch D2, and is used as the negative Q-path differential local oscillation signal output terminal, and outputs a Q-path second local oscillation signal LOQN.

The positive data output terminal OP of the first D-latch D1 is connected to the positive data input terminal DP of the second D-latch D2, and is used as the positive output terminal of the I-path differential local oscillation signal and outputs the I-path first local oscillation signal LOIP.

The data output negative terminal ON of the first D latch D1 is connected to the data input negative terminal DN of the second D latch D2, and serves as an I-path differential local oscillation signal output negative terminal, and outputs an I-path second local oscillation signal LOIN.

The function of the D-latch is to make the output signal equal to the input signal, or to keep the output signal in a previous state, or to clear the output signal, under the influence of different specific input clock levels (or edges) and input signals. Therefore, as shown in fig. 1, the present invention forms a negative feedback loop by cascading two D latches, and under the effect that the duty ratio of the input first differential clock signal CLKP and the second differential clock signal CLKP is 50%, an I-way differential local oscillator signal with a duty ratio of 25% is generated: the first local oscillator signal LOIP of I way, I way second local oscillator signal LOIN, Q way difference local oscillator signal: the Q-path first local oscillation signal LOQP and the Q-path second local oscillation signal LOQN.

Further, the utility model discloses not only can realize that the duty cycle is 25% quadrature local oscillator signal's production, it can also realize the phase calibration to two way local oscillator signal of IQ. That is, the phase calibration of the IQ two-path local oscillator signal is realized by inputting corresponding phase control signals through the controllable switch control terminals of the two D latches.

Namely: the controllable switch control end PHACAL of the first D-latch D1 is used as an I-path local oscillator signal phase calibration control end, and an I-path local oscillator signal phase calibration signal PHACAL _ I is input.

The controllable switch control end PHACAL of the second D-latch D2 is used as a Q-path local oscillator signal phase calibration control end, and a Q-path local oscillator signal phase calibration signal PHACAL _ Q is input.

That is to say, the phase calibration of the IQ two local oscillator signals is realized by the I local oscillator signal phase calibration signal PHACAL _ I and the Q local oscillator signal phase calibration signal PHACAL _ Q. For example, when the phases of the IQ two local oscillator signals have errors, the phase calibration of the IQ two local oscillator signals can be realized through the operating states of the controllable switches of the two D latches.

As shown in fig. 2, the D-latch adopted by the present invention mainly comprises a differential input pair transistor, a latch pair transistor, a clock pair transistor and two identical controllable switches.

The differential input pair transistors are used for sampling input signals or clearing output signals. The differential input pair transistor comprises two NMOS transistors, which are respectively marked as NM1 and NM 2.

And the clock pair tube is used for controlling the clock pair tube by an input clock signal, and when the input clock is in a low level, the clock pair tube is conducted to enable current to flow. The pair of clock transistors comprises two PMOS transistors, which are respectively marked as a first PMOS transistor PMOS1 and a second PMOS transistor PMOS 2.

And the latch pair tube is used for latching the output state. The latch pair transistor comprises two NMOS transistors, respectively noted as NM3 and NM 4.

The controllable switches are used for matching with the phase adjustment control signals to adjust the phases of the output signals and are respectively marked as a first controllable switch and a second controllable switch.

The circuit of the D latch is a bilateral symmetry differential structure, and the specific link relation of each device is as follows:

the gates of the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 are connected to serve as a clock signal input end CLK of the D latch, and the sources are connected to a power supply VDD; the drain of the first PMOS transistor PMOS1 is connected to the positive terminal of the first controllable switch 1, and the drain of the second PMOS transistor PMOS2 is connected to the positive terminal of the second controllable switch 2.

The drains of NM1, NM3, and the gate of NM4 are connected to the negative terminal of the first controllable switch 1, which is the negative terminal ON of the D-latch data output.

The drains of NM2, NM4, and the gate of NM3 are connected to the negative terminal of the second controllable switch 2, and are used as the positive data output terminal OP of the D-latch.

The sources of NM1, NM2, NM3, NM4 are all connected to ground VSS.

The gate of NM1 serves as the data input signal positive terminal DP of the D-latch.

The gate of NM2 serves as the data input signal negative terminal DN of the D latch.

The control terminals of the first controllable switch 1 and the second controllable switch 2 are connected to serve as the controllable switch control terminal PHACAL of the D latch.

The design parameters of the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 are the same, the design parameters of NM1 and NM2 are the same, and the design parameters of NM3 and NM4 are the same.

Fig. 3 shows a circuit diagram of the first controllable switch and the second controllable switch of the D-latch.

Each controllable switch is composed of N PMOS transistors, and each PMOS transistor is equivalent to an independent switch, which is denoted as PM1, PM 2. The design parameters of each PMOS tube of the controllable switch can be the same or different.

The source and drain of all the PMOS transistors of each controllable switch are connected in parallel, that is: the source electrodes of all the PMOS tubes of each controllable switch are connected and used as the positive end of the controllable switch of the D latch, and the drain electrode of the PMOS tube of each controllable switch is connected and used as the negative end of the controllable switch of the D latch.

The grid electrode of each PMOS tube of each controllable switch is respectively used as an independent controlled end and is respectively controlled by a control signal PHACAL < n >, namely the grid electrode of the PMOS tube of each controllable switch is connected with the control end of the controllable switch used as a D latch and receives the corresponding control signal.

That is, the conduction of one or more of the controllable switches may be arbitrarily controlled according to the input control signal. Wherein, the design parameters of each PMOS tube of each controllable switch can be the same or different.

Wherein, control signal PHACAL < n >, it is promptly the utility model provides a I way local oscillator signal phase calibration signal PHACAL _ I or Q way local oscillator signal phase calibration signal PHACAL _ Q.

That is, the on state of each PMOS transistor in each controllable switch in the first D latch D1 is controlled by the I-path local oscillator signal phase calibration signal PHACAL _ I, and the on state of each PMOS transistor in each controllable switch in the second D latch D2 is controlled by the Q-path local oscillator signal phase calibration signal PHACAL _ Q.

The larger the number of PMOS transistors provided for each controllable switch, the more phase adjustment it chooses. For example, when 4 PMOS transistors are provided, a maximum of 24-16 phase adjustment options can be generated, for example, corresponding to 0, 1, 2, and 3 … … 15 in fig. 5 and 6. In addition, in the actual working process, each controllable switch at least ensures that one switch, namely the PMOS tube, is in a conducting state during the working period of the D latch.

The utility model discloses the theory of operation that IQ local oscillator signal produced has still been given:

first, the working principle for the D-latch is as follows:

when the input signal of the clock signal input end CLK is low level:

if the positive data input terminal DP is at a high level and the negative data input terminal DN is at a low level, the positive data output terminal OP is at a high level and the negative data output terminal ON is at a low level.

If the positive data input terminal DP is at a low level and the negative data input terminal DN is at a high level, the positive data output terminal OP is at a low level and the negative data output terminal ON is at a high level.

If the positive data input terminal DP and the negative data input terminal DN are at the same low level, the positive data output terminal OP and the negative data output terminal ON both keep the previous state.

When the clock signal input end CLK is input to high level:

if the states of the data input positive terminal DP and the data input negative terminal DN are not changed, the data output positive terminal OP and the data output negative terminal ON are kept in the original states.

If the states of the data input positive terminal DP and the data input negative terminal DN are reversed, the data output positive terminal OP and the data output negative terminal ON output low levels at the same time.

Therefore, based on the theory of operation of D latch, the utility model provides a duty cycle is 25% quadrature local oscillator signal generating device's theory of operation as follows:

firstly, the duty ratios of the first differential clock input signal CLKP and the second differential clock input signal CLKN respectively input to the clock signal input terminals CLK of the first D latch D1 and the second D latch D2 must be 50%, and it is assumed that before the first half cycle of the first cycle comes, the Q-path first local oscillation signal LOQP is low, and the Q-path second local oscillation signal LOQN is high:

step S1, when the first half period of the first cycle comes:

the first differential clock input signal CLKP jumps to a low level, the second differential clock input signal CLKN jumps to a high level, the I-way first local oscillation signal LOIP jumps to a high level, and the I-way second local oscillation signal LOIN jumps to a low level. Since the second differential clock input signal CLKN is at a high level, the Q-path second local oscillation signal LOQN is pulled down to a low level, and the Q-path first local oscillation signal LOQP is kept at a low level.

Therefore, before the second half of the first period comes, the I-path first local oscillation signal LOIP is kept at a high level, the I-path second local oscillation signal LOIN is kept at a low level, the Q-path first local oscillation signal LOQP is kept at a low level, and the Q-path first local oscillation signal LOQN is kept at a low level.

Step S2, when the second half cycle of the first cycle comes:

the first differential clock input signal CLKP jumps to a high level, the second differential clock input signal CLKN jumps to a low level, the Q-path first local oscillation signal LOQP jumps to a high level, and the Q-path second local oscillation signal LOQN remains at a low level. Since the differential clock input signal CLKP is at a high level, the I-path first local oscillation signal LOIP is pulled down to a low level, and the I-path second local oscillation signal LOIN is kept at a low level.

Therefore, before the first half cycle of the second cycle comes, the I-path first local oscillation signal LOIP is kept at a low level, the I-path second local oscillation signal LOIN is kept at a low level, the Q-path first local oscillation signal LOQP is kept at a high level, and the Q-path second local oscillation signal LOQN is kept at a low level.

Step S3, when the first half period of the second period comes:

the first differential clock input signal CLKP jumps to a low level, the second differential clock input signal CLKN jumps to a high level, the I-way first local oscillation signal LOIP remains at a low level, and the I-way second local oscillation signal LOIN jumps to a high level. Since the differential clock input signal CLKN is at a high level, the Q-path first local oscillation signal LOQP is pulled down to a low level, and the Q-path second local oscillation signal LOQN is kept at a low level. Therefore, before the second half of the second period comes, the I-path first local oscillation signal LOIP is kept at a low level, the I-path second local oscillation signal LOIN is kept at a high level, the Q-path first local oscillation signal LOQP is kept at a low level, and the Q-path second local oscillation signal LOQN is kept at a low level.

Step S4, when the second half cycle of the second cycle comes:

the first differential clock input signal CLKP jumps to a high level, the second differential clock input signal CLKN jumps to a low level, the Q-path first local oscillation signal LOQP is maintained at a low level, and the Q-path second local oscillation signal LOQN jumps to a high level. Since the differential clock input signal CLKP is at a high level, the I-path second local oscillation signal LOIN is immediately turned down to a low level, and the I-path first local oscillation signal LOIP is kept at a low level. Therefore, before the first half cycle of the third cycle comes, the I-path first local oscillation signal LOIP is kept at a low level, the I-path second local oscillation signal LOIN is kept at a low level, the Q-path first local oscillation signal LOQP is kept at a low level, and the Q-path second local oscillation signal LOQN is kept at a high level.

Therefore, a signal period is obtained according to the foregoing steps S1, S2, S3 and S4, and then each period is repeated in the following steps, so that when the duty ratios of the first differential clock input signal CLKN and the second differential clock input signal CLKP are ensured to be 50%, IQ two local oscillation signals with a duty ratio of 25% can be generated.

As can be seen from the timing diagram in fig. 4, the output periods of the I-path first local oscillator signal LOIP, the I-path second local oscillator signal LOIN, the Q-path first local oscillator signal LOQP, and the Q-path second local oscillator signal LOQN are twice as long as the period of the first differential clock input signal CLKP or the period of the second differential clock input signal CLKN; in addition, the first differential clock input signal CLKP or the second differential clock input signal CLKN is high only in a half period of one of 2 periods, which corresponds to high only in 1/4 periods. Therefore, as long as the duty ratios of the input first differential clock input signal CLKP and the input second differential clock input signal CLKN are ensured to be 50%, the duty ratios of the output I-path first local oscillator signal LOIP, I-path second local oscillator signal LOIN, Q-path first local oscillator signal LOQP, and Q-path second local oscillator signal LOQN can all be 25%.

Simultaneously, can observe leading Q way first local oscillator signal LOQP 1/4 cycles to I way first local oscillator signal LOIP, leading Q way second local oscillator signal LOQN 1/4 cycles to I way second local oscillator signal LOIN, also be that two way local oscillator signals of IQ differ 90 in the phase place, that is to say, the utility model provides a duty cycle is 25% local oscillator signal generating device, also can realize the quadrature of two way local oscillator signal of IQ according to the time diagram.

Further, when the difference in the phase of two way local oscillator signals of IQ is not 90, the utility model discloses can also calibrate the phase place of two way local oscillator signals of IQ, also be: the I path of first local oscillation signals LOIP lead the Q path of first local oscillation signals LOQP 1/4 periods, and the I path of second local oscillation signals LOIN lead the Q path of second local oscillation signals LOQN 1/4 periods.

The D latches are provided with controllable switches, each controllable switch comprises a plurality of PMOS (P-channel metal oxide semiconductor) tubes, each PMOS tube is equivalent to one switch, and the conduction or the disconnection of each PMOS tube can be controlled through signals. That is, in a D latch, the output voltage can be controlled by different combinations of controllable switches, namely: the method is characterized in that one or more PMOS (P-channel metal oxide semiconductor) tubes of the controllable switch are controlled to be in a conducting state or a disconnecting state, so that the current from a power supply VDD for charging the data output positive end OP and the data output negative end ON node capacitor through the clock pair tube PMOS1 and the second PMOS2 in the conducting period of the clock pair tube PMOS1 and the second PMOS2 connected with the positive end of the controllable switch is controlled, and the high-level establishing process of the data input positive end OP and the data input negative end ON node is further influenced. For example, the first controllable switch and the second controllable switch are only in the on state (i.e. in the active state) when the clock pair transistors first PMOS1 and second PMOS2 are on (i.e. when CLK is at low level), otherwise, the current from the power supply VDD is cut off, so that the controllable switches are in the off state.

The current of the node capacitors of the positive data output terminal OP and the negative data output terminal ON is from the power supply VDD and is under the control of the clock transistor PMOS1 and the second PMOS2 and the controllable switch. Therefore, when the current of the controllable switch is larger, the charging current is larger, and at this time, the establishment time of the node capacitances of the data output positive terminal OP and the data output negative terminal ON from a low level to a high level is shorter, so that the delay of the phases of the output signals of the data output positive terminal OP and the data output negative terminal ON is influenced, and the phase calibration of the IQ two-path local oscillator signals is realized.

Specifically, the utility model discloses an input I way local oscillator signal phase calibration signal PHACAL _ I to the controllable switch control end of first D latch, Q way local oscillator signal phase calibration signal PHACAL _ Q inputs the controllable switch control end of second D latch, and then control first D latch, the ON-state of every PMOS pipe in the controllable switch of second D latch, and then influence the positive terminal OP of data output, the phase place of the output signal of data output negative terminal ON, realize the phase calibration of the two way local oscillator signal of IQ.

Therefore, when the phase of the IQ two local oscillator signals has an error, that is, the I path first local oscillator signal LOIP leads or lags the Q path first local oscillator signal LOQP 1/4 cycles, and the I path second local oscillator signal LOIN leads or lags the Q path second local oscillator signal LOQN 1/4 cycles, the operating state of the controllable switch of the first D latch and/or the controllable switch of the second D latch is controlled by changing the I path local oscillator signal I local oscillator signal phase calibration signal phaal _ I and/or the Q path local oscillator signal phase calibration signal phaal _ Q, so as to control the conducting state of each PMOS transistor in the controllable switch, and further influence the phase of the output signal of the data output positive terminal OP and the data output negative terminal ON.

Therefore, the utility model discloses a change I way local oscillator signal phase alignment signal PHACAL _ I and Q way local oscillator signal phase alignment signal PHACAL _ Q and control the work of the controllable switch of first D latch D1 and second D latch D2 respectively. That is, by changing the control value of the I-path local oscillator signal phase calibration signal PHACAL _ I, the phases (such as leading or lagging) of the I-path first local oscillator signal LOIP and the I-path second local oscillator signal LOIN can be changed; by changing the control value of the Q-path local oscillator signal phase calibration signal PHACAL _ Q, the phases (such as leading or lagging) of the Q-path first local oscillator signal LOQP and the Q-path second local oscillator signal LOQN can be changed. Until the phase difference of local oscillation signals of IQ two paths is 90 DEG

For example, if the I local oscillators (LOIP and LOIN) lead the Q local oscillators 91 °, the phase of the I local oscillators (LOIP and LOIN) may gradually lag behind by decreasing PHACAL _ I, or the phase of the Q local oscillators (LOQP and LOQN) may gradually lead by increasing PHACAL _ Q, and finally the phase difference may be calibrated to 90 ° from 91 °.

That is, when the phases of the IQ two local oscillator signals have errors, the phase calibration of the IQ two local oscillator signals can be achieved by changing the control values of the I local oscillator signal phase calibration signal PHACAL _ I and/or the Q local oscillator signal phase calibration signal PHACAL _ Q.

Preferably, suppose, every controllable switch in the present invention includes 4 PMOS transistors, which are respectively marked as: PM0, PM1, PM2, PM 3. The influence of the I-path local oscillator phase calibration signal PHACAL _ I on the IQ phase can be obtained through simulation, as shown in fig. 5, it can be seen that the phase difference of the IQ two-path local oscillator signals changes from 90 ° to about 95 ° by adjusting the I-path local oscillator phase calibration signal PHACAL _ I from 0 to 15, that is, if the phase difference of the IQ two-path local oscillator signals is less than 90 °, the phase difference of the IQ two-path local oscillator signals can be calibrated by adjusting the I-path local oscillator phase calibration signal PHACAL _ I to reach 90 °.

PHACAL <3 in fig. 5: 0> corresponds to the control sequence of the gate input terminal of each controllable switch in fig. 3, such as PHACAL _ I <3>, PHACAL _ I <2>, PHACAL _ I <1>, PHACAL _ I <0> respectively control the conduction or the disconnection of the corresponding PMOS transistor in the controllable switch.

The same method can simulate the influence of the Q-path local oscillator phase calibration signal PHACAL _ Q on the phase difference of the IQ-path local oscillator signals, as shown in fig. 6, it can be seen that the Q-path local oscillator phase calibration signal PHACAL _ Q is adjusted from 0 to 15, and the phase difference of the IQ-path local oscillator signals changes from 90 ° to 85 °, that is, if the phase difference of the IQ-path local oscillator signals exceeds 90 °, the phase difference of the IQ-path local oscillator signals can be calibrated by adjusting the Q-path local oscillator phase calibration signal PHACAL _ Q to 90 °.

The device can realize the generation of the local oscillation signal with the duty ratio of 25 percent without firstly generating the local oscillation signal through the duty ratio generating circuit and then calibrating through the IQ phase calibration module, namely realizing the generation of the local oscillation signal and the phase calibration in a separated mode, thereby not only saving the power consumption and the area of a chip, but also solving the problem that the duty ratio is damaged in the final calibration in the prior art.

The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention cannot be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are all within the protection scope of the present invention.

Claims (6)

1. An orthogonal local oscillator signal generating device with a duty ratio of 25 percent is characterized by comprising a first D latch, a second D latch, a differential clock input positive end, a differential clock input negative end, an I-path local oscillator signal output positive end, an I-path local oscillator signal output negative end, a Q-path local oscillator signal output positive end and a Q-path local oscillator signal output negative end;

the first D latch and the second D latch are respectively provided with a clock signal input end, a data input positive end, a data input negative end, a data output positive end and a data output negative end;

the clock signal input end of the first D latch is connected with the positive end of the differential clock input and used for inputting a first differential clock input signal; the clock signal input end of the second D latch is connected with the negative end of the differential clock input and is used for inputting a second differential clock input signal;

the data input negative end of the first D latch is connected with the data output positive end of the second D latch to serve as a Q-path differential local oscillation signal output positive end and output a Q-path first local oscillation signal;

the positive data input end of the first D latch is connected with the negative data output end of the second D latch, and the positive data input end of the first D latch serves as the negative Q-path differential local oscillation signal output end and outputs Q-path second local oscillation signals;

the positive data output end of the first D latch is connected with the positive data input end of the second D latch to serve as the positive output end of the I-path differential local oscillation signal and output the I-path first local oscillation signal;

and the data output negative end of the first D latch is connected with the data input negative end of the second D latch, and is used as the output negative end of the I-path differential local oscillation signal and outputs the I-path second local oscillation signal.

2. The apparatus according to claim 1, wherein the duty cycle of the quadrature local oscillator signal generating device is 25%: the first D latch and the second D latch also comprise controllable switch control ends, the controllable switch control end of the first D latch is used for inputting the phase calibration signal of the local oscillator signal of the I path, and the controllable switch control end of the second D latch is used for inputting the phase calibration signal of the local oscillator signal of the Q path; the local oscillator signal generating device changes the working state of the controllable switch of the first D latch and/or the second D latch by changing the phase calibration signal of the local oscillator signal of the I path and/or the phase calibration signal of the local oscillator signal of the Q path, and further changes the phase of the local oscillator signal of the I path and/or the phase of the local oscillator signal of the Q path, so that the phase calibration of the local oscillator signals of the IQ path is realized.

3. The apparatus according to claim 2, wherein the duty cycle of the quadrature local oscillator signal generating device is 25%: the first D latch and the second D latch each comprise: the differential input pair tube, the latch pair tube, the clock pair tube and the controllable switch;

the differential pair transistors comprise a first NMOS transistor and a second NMOS transistor, the latch pair transistors comprise a third NMOS transistor and a fourth NMOS transistor, the clock pair transistors comprise a first PMOS transistor and a second PMOS transistor, and the controllable switches comprise a first controllable switch and a second controllable switch;

the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are used as clock signal input ends, and the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected to a power supply; the drain electrode of the first PMOS tube is connected with the positive end of the first controllable switch, and the drain electrode of the second PMOS tube is connected with the positive end of the second controllable switch;

the drain electrode of the first NMOS tube, the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are connected with the negative end of the first controllable switch and serve as the negative end of data output; the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the third NMOS tube are connected with the negative end of the second controllable switch and used as the positive end of data output;

the source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are all grounded; the grid electrode of the first NMOS tube is used as a positive data input end; the grid electrode of the second NMOS tube is used as the negative end of the data output;

the control ends of the first controllable switch and the second controllable switch are connected to serve as the control ends of the controllable switches.

4. A quadrature local oscillator signal generating device according to claim 3, having a duty cycle of 25%, wherein: the first controllable switch and the second controllable switch are composed of N PMOS tubes, wherein N is greater than 1, and N is a natural number; the source electrodes of all PMOS tubes of each controllable switch are connected to serve as the positive end of the corresponding controllable switch, and the drain electrodes of all PMOS tubes are connected to serve as the negative end of the corresponding controllable switch; and the grid electrode of each PMOS tube of the first controllable switch and the grid electrode of each PMOS tube of the second controllable switch are connected with each other to be used as a control end of the controllable switch and used for inputting a local oscillator signal phase calibration signal.

5. The apparatus according to claim 4, wherein the duty cycle of the quadrature local oscillator signal generating device is 25%: during the operation of each D latch, at least one PMOS tube of each controllable switch is in a conducting state.

6. A quadrature local oscillator signal generating device according to claim 3, having a duty cycle of 25%, wherein: the design parameters of the first PMOS tube and the second PMOS tube are the same, the design parameters of the first NMOS tube and the second NMOS tube are the same, and the design parameters of the third NMOS tube and the fourth NMOS tube are the same.

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