JP2009017528A - Pulse generating circuit and uwb communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a short-pulse generating circuit for generating an accurate differential output or a pair of IQ pulses with phases different by 90° with small power consumption by solving all problems of a conventional pulse generating circuit that, it is difficult to obtain differential output signals or I Q signals with 90° phase differences, a degree of balancing is adverse, and there are many phase errors or noise. <P>SOLUTION: A pulse generating circuit includes a starting circuit 101 which generates a plurality of starting signals (b01, c01) at predetermined time intervals based on a generation starting signal a01, and a plurality of pulse wave generating sub circuits (102, 103) which have the same characteristics and generate predetermined pulse waves (d01, e01) based on the starting signals (b01, c01) of the starting circuit 101. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a pulse generation circuit and a UWB communication apparatus that generate pulses suitable for UWB (Ultra Wide Band) communication.

  UWB communication is a communication method that performs high-speed and large-capacity data communication using a very wide frequency band. In addition to the conventional spread spectrum method and orthogonal frequency division multiplexing (OFDM) method, there are methods that use very short pulses to generate wideband signals, especially impulse radio. This is called (IR: Impulse Radio) communication. In the IR method, modulation / demodulation is possible only by time axis operation not based on conventional modulation, and it is expected that simplification of the circuit and low power consumption can be expected (see Patent Documents 1, 2, and 3).

Here, a pulse waveform used in the IR method will be briefly described. A pulse wave having a pulse width P _D and a period T _P as shown in FIG. 16A is well known, and the frequency spectrum of the pulse wave has an envelope of BW as shown in FIG. = is a sinc function having a first zero point at 1 / P _D.

In the case of such a pulse, since the spectrum spreads from direct current to BW, it is difficult to use, and a pulse having a high frequency at the center of the spectrum as shown in FIG. That is, the pulse waveform is as shown in FIG. 16C, and the frequency spectrum is shifted to the higher side by multiplying the pulse of FIG. 16A by a pulse wave of frequency f ₀ = 1 / 2Pw. The interval of the pulse width P _D includes several pulses of half the carrier wave period Pw (Pw = 1 / (2f 0)). However, this waveform includes a direct current (DC) component as shown by a one-dot chain line 1601 in FIG. 16C, and does not have an ideal spectrum as shown in FIG.

A waveform having such an ideal spectrum is shown in FIG. This waveform is obtained by multiplying the pulse of FIG. 16A by a sine wave having the carrier frequency f ₀ . The FIG. 16 (f) is a pulse waveform obtained by multiplying a square wave of the carrier frequency f ₀ of FIG. 16 (a), the it is easy to occur in the digital circuit. Even if it is a digital circuit, since the pulse width is narrow, such an angular waveform is not generated and the waveform is generally as shown in FIG. Various pulse waveforms ideal for UWB communication have been devised, and are different from the waveforms shown here, but are frequently used because the generation method is simple.

(Conventional Example 1) FIG. 17A shows a conventional circuit example for generating the pulses shown in FIG. 16C (see Non-Patent Document 1). The two inverters 1701 and 1702 and the negative OR circuit (NOR) 1703 constitute a three-stage ring oscillation circuit when the other input C _{i of the} NOR 1703 becomes false (L: low level). That is, as shown in the timing chart of FIG. 17B, oscillation occurs only while C _i is L, and the output NR of the NOR 1703 and the outputs N1 and N2 of the inverters 1701 and 1702 are delayed by time td, respectively, and changes are propagated. Go.

Here, to simplify the description, it is assumed that the rise time and the fall time of the NOR 1703 and the inverters 1701 and 1702 are all equal. Therefore, the pulse width generated in this circuit (P _w in FIG. 16C) is 3td. That is, three times the delay time of the elements constituting the circuit is the shortest pulse width that can be generated, and this is the shortest pulse width that can be generated by this circuit.

  (Conventional example 2) In UWB communication, pulses generated in this way are used not only as a transmitter but also as a template pulse for calculating a correlation with a received signal in a receiver. In the receiver, differential signal processing is often performed, and two signals having inverted phases as shown in FIG. 16G are often required. The differential pulse signal is also effective in driving a balanced antenna in the transmitter. In the receiving circuit, I and Q signals whose in-phase and quadrature phases differ by 90 degrees are often required.

  Non-Patent Document 2 presents a circuit for generating balanced pulses. In this circuit, several stages of differential delay circuits are connected in cascade, and a pulse wave having a pulse width corresponding to the delay amount of one stage of the delay circuit is generated by a logic circuit. In Non-Patent Document 2, it is possible to start a pulse both at the rising edge and the falling edge of a signal input to the delay circuit, thereby enabling low power consumption, and by using the delay circuit every other stage. It is also noted that I and Q signals can be generated.

US Pat. No. 6,421,389 US Patent Application Publication No. 2003 / 0108133A1 US Patent Application Publication No. 2001/0033576 A CMOS IMPULSE RADIO ULTRA-WIDEBAND TRANCEIVER FOR 1Mb / s DATA COMMUNICATION AND ± 2.5cm RANGE FINDINGS T. Terada et.al, 2005 Symposium on VLSI Circuits Digest of Technical Papers, pp.30-33 A Low-Power Template Generator for Coherent Impulse-Radio Ultra Wide-Band Receivers Jose Luis et.al, Proceedings IEEE ICUWB, 2006 pp97-102

The prior art described above, an I a delay circuit generates both complementarily configured always D _i and XD _i, occurrence of Q signals easily. However, this method of obtaining a differential signal by using a P channel MOS transistor and an N channel MOS transistor in a complementary manner provides a good balance of generated signals unless the constants of the P and N channel MOS transistors are balanced. Absent. If there is an unbalanced component with an unbalanced signal, an output error increases particularly when a correlator is configured in the receiver, which is not convenient.

  Furthermore, although it is stated that the pulse can be activated at both the rising and falling edges of the activation start signal and that power can be saved, the generated pulse is the same as the pulse activated at the rising edge. There is a problem that the polarity of the pulse activated at the fall is inverted, and a large restriction is imposed on the modulation operation and the activation timing.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
An activation circuit for generating m (m is an integer of 2 or more) activation signals at predetermined time intervals based on the activation start signal, and n periods (n is a pulse width Pw) based on each of the m activation signals. A pulse generation circuit including m pulse wave generation sub-circuits having the same characteristics for generating a pulse wave of an integer of 1 or more.

  According to this configuration, a differential pulse wave having a stable DC level and good symmetry can be obtained by using a plurality of pulse wave generation sub-circuits having the same characteristics and adjusting the start-up time of each pulse wave generation sub-circuit. Can be generated. If the predetermined time interval of the m activation signals is set equal to the pulse width Pw of the pulse wave, a differential signal having a phase difference of 180 degrees can be obtained, and if it is half of Pw, an I having a phase difference of 90 degrees is obtained. , Q signals can be obtained.

[Application Example 2]
In the pulse generation circuit described above, the pulse wave generation sub-circuit is based on a plurality of inverter delay circuits each having an amount of delay set to the pulse width Pw, and output signals of the plurality of inverter delay circuits. And a pulse wave generation logic circuit for generating the pulse wave.

  According to this configuration, since it can be configured by an inverter delay circuit and a pulse wave generation logic circuit by a normal semiconductor process, high integration is easy.

[Application Example 3]
In the pulse generation circuit described above, the pulse generation circuit includes two pulse wave generation subcircuits, and each of the pulse wave generation subcircuits sets the predetermined time interval to the pulse width Pw. The pulse generation circuit characterized in that the pulse wave is generated based on each of the two activation signals generated by the activation circuit.

  According to this configuration, each pulse wave generation sub-circuit generates a pulse wave at a time interval of the pulse width Pw, so that it is possible to generate two signals that are 180 degrees out of phase with each other. Since the generated pulse wave is generated by a pulse wave generation sub-circuit having the same characteristics, it is possible to generate a differential pulse wave having a stable DC level and good symmetry.

[Application Example 4]
In the pulse generation circuit described above, the pulse generation circuit includes two pulse wave generation subcircuits, and each of the pulse wave generation subcircuits sets the predetermined time interval to the pulse width Pw / 2. A pulse generation circuit characterized in that the pulse wave is generated based on each of the two activation signals generated by the set activation circuit.

  According to this configuration, each pulse wave generation sub-circuit generates a pulse wave having a pulse width Pw at a time interval of Pw / 2, so that it is possible to generate two signals that are 90 degrees out of phase with each other. . Since the generated pulse wave is generated by a pulse wave generation sub-circuit having the same characteristics, a pulse wave (I, Q signal) having a stable DC level and a phase that is 90 degrees different may be generated. It becomes possible.

[Application Example 5]
In the pulse generation circuit described above, the pulse generation circuit includes four pulse wave generation subcircuits, and each of the pulse wave generation subcircuits sets the predetermined time interval to the pulse width Pw / 2. A pulse generation circuit characterized in that the pulse wave is generated based on each of the four start signals generated by the set start circuit.

  According to this configuration, each of the pulse wave generation sub-circuits generates a pulse wave having a pulse width Pw at a time interval of Pw / 2, so that four signals having phases different from each other by 90 degrees, that is, phases differ by 90 degrees. Two sets of differential signals (I and Q differential signals) can be generated. Since the generated pulse wave is generated by a pulse wave generation sub-circuit having the same characteristics, it is possible to generate a differential pulse wave (I, Q signal) having a stable DC level and good symmetry. Become.

[Application Example 6]
In the pulse generation circuit according to Application Example 4 or Application Example 5, the pulse generation circuit further includes an addition / subtraction circuit that adds and subtracts the pulse waves generated by the pulse wave generation subcircuits to each other. A pulse generation circuit characterized by that.

  According to this configuration, the signals generated by the pulse wave generation subcircuits are added and subtracted to generate a new signal, thereby generating I, It is possible to further increase the orthogonality of the Q pulse signal.

[Application Example 7]
In the pulse generation circuit according to any one of the application examples 1 to 3, the start circuit generates a two-phase signal in which rising and falling simultaneously change based on the start start signal, and the two-phase signal generating circuit A pulse generation circuit comprising: the inverter delay circuit connected to one of output signals of the signal generation circuit.

  According to this configuration, the activation circuit can generate a two-phase activation signal at a time interval that matches the delay amount of the inverter delay circuit that constitutes the pulse wave generation subcircuit. Can be exactly matched to the pulse width Pw of the pulse wave generated by the pulse wave generation subcircuit.

[Application Example 8]
In the pulse generation circuits according to Application Examples 1, 2, 4, and 6, the start-up circuit includes a first delay circuit in which a delay amount is set to the pulse width Pw, and a delay amount that is the pulse width Pw × 1. A pulse generation circuit comprising: a second delay circuit set to 5;

  According to this configuration, when generating two pulse waves with a phase difference of 90 degrees, the startup time difference of the pulse wave generation subcircuit must be set to half the pulse width Pw of the pulse wave generated by the pulse wave generation subcircuit. However, when the circuit is operating at a speed as high as the element limit, it is difficult to create a time difference that is half the pulse width Pw. By using the delay time difference between the second delay circuit with a delay amount of pulse width Pw × 1.5 and the first delay circuit with a delay amount of pulse width Pw, it is possible to create a delay time difference that is half of the pulse width Pw. Become.

[Application Example 9]
In the pulse generation circuit described above, the pulse generation circuit switches an output destination of the m activation signals generated by the activation circuit to any one of the m pulse wave generation subcircuits based on data to be transmitted. A pulse generation circuit comprising an activation signal selection circuit.

  According to this configuration, since modulation can be performed based on the value of data to be transmitted, it can be used as a pulse generation circuit suitable for UWB communication.

[Application Example 10]
In the pulse generation circuit described above, the pulse generation circuit includes an output selection circuit that switches an output destination of the pulse wave generated by the m pulse wave generation subcircuits based on data to be transmitted. A pulse generator circuit.

  According to this configuration, since modulation can be performed based on the value of data to be transmitted, it can be used as a pulse generation circuit suitable for UWB communication.

[Application Example 11]
8. The pulse generation circuit according to Application Example 3 or 7, wherein the pulse generation circuit is an output of the inverter delay circuit constituting the pulse wave generation subcircuit in a predetermined set of the m pulse wave generation subcircuits. A pulse generation circuit comprising: a cross-coupled inverter connected between output nodes whose phases are inverted from each other.

  According to this configuration, a slight phase shift caused by a small error in the delay amount of each inverter delay circuit between one set of pulse wave generation subcircuits can be corrected by the cross-coupled inverter, so that more accurate pulse Can be generated.

[Application Example 12]
In the pulse generation circuit described above, the pulse width of the start signal input to the start circuit is not less than the pulse width Pw and less than the pulse width Pw × 4 × n. circuit.

  According to this configuration, it is possible to hide unnecessary pulse waves by making the pulse width of the start signal shorter than the pulse waves of n cycles generated by the pulse generation circuit, so that generation of noise can be suppressed. it can.

[Application Example 13]
The pulse generation circuit according to the above, wherein the period of the activation start signal input to the activation circuit is an even multiple of the pulse width Pw.

  According to this configuration, it is possible to generate a continuous pulse wave by periodically starting the pulse wave generation subcircuit.

[Application Example 14]
The pulse generation circuit according to the above, wherein the inverter delay circuit can control a delay amount of the inverter delay circuit by an external control signal.

  According to this configuration, the delay amount of the inverter delay circuit can be controlled by the external control signal, so that it is possible to correct fluctuations and errors in generated pulses due to manufacturing variations, operating temperatures, and power supply voltage fluctuations.

[Application Example 15]
A UWB communication apparatus comprising the pulse generation circuit described above.

  According to this configuration, an ultra-fine pulse unique to UWB can be easily generated as a differential signal by the pulse generation circuit, and by using these as a template generation circuit for a modulation circuit or a demodulation circuit, these circuits can be used. A differential type stable circuit system can be applied, and a stable, highly reliable, and highly sensitive device can be constructed at low cost. Particularly, the pulse generation circuit according to the present invention can generate a high-frequency differential pulse to the extent of the performance limit of the element, and its usefulness is high.

  The pulse generation circuit can be constituted by a CMOS integrated circuit or the like, and can generate a pulse as narrow as the operation transition time of the element. Furthermore, it is possible to generate a differential or IQ pulse signal with less distortion compared to a conventional pulse generation circuit. In addition, since it can be configured with a logic circuit using a CMOS integrated circuit, it can be configured to operate easily at the maximum speed of the CMOS circuit without an increase in operating power, and a high-frequency broadband pulse that can be used for UWB communication can be easily obtained. Can occur.

  Hereinafter, embodiments of a pulse generation circuit will be described with reference to the drawings.

(First embodiment)
<Pulse configuration>
First, a pulse wave to be generated will be described with reference to FIG. FIG. 20 is a waveform diagram showing a pulse wave to be generated.

  The pulse wave to be generated has a pair of pulse waves whose phases are different from each other by 180 degrees as shown in FIGS. 20 (a) and 20 (b), or a phase which is 90% as shown in FIGS. 20 (d) and 20 (e). Further, as shown in FIGS. 20 (g) to (j), two pairs of pulse waves whose phases are different from each other by 180 degrees are two pairs that are output with phases different from each other by 90 degrees. . 20A and 20B are pulse signals of differential output, and the potential difference between the pulse signal of FIG. 20A and the pulse signal of FIG. 20B is shown in FIG. It becomes such a pulse signal. FIGS. 20D and 20E show single-ended output I and Q signals, and FIGS. 20G to 20J show differential output I and Q signals.

In the present embodiment, a case where the following waveform that can be easily realized using a CMOS (complementary metal oxide semiconductor) process with a minimum line width of 0.18 μm is generated will be described as an example. However, the present embodiment is limited to this case. It is not something. As shown in FIG. 20 (a), when the pulse interval is T _P (arbitrary) and the carrier frequency f ₀ = 4 GHz, half of the carrier period obtained by Pw = 1 / (2f ₀ ) is Pw = 125 psec, and the pulse width P _D is P _D = 2 × n × Pw (n is an arbitrary period). The signal forms are a differential output, a pair of I and Q signals for single-ended output, and a pair of I and Q signals for differential output.

<Configuration of pulse generation circuit>
First, the configuration of the pulse generation circuit according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a configuration diagram illustrating a configuration of a pulse generation circuit according to the first embodiment. FIG. 2 is a timing chart showing the operation of the pulse generation circuit according to the first embodiment.

  As shown in FIG. 1, the pulse generation circuit 1 includes a starter circuit 101 and pulse wave generation subcircuits 102 and 103 having the same characteristics. The activation circuit 101 receives the activation start signal a01 input to the terminal 106, generates m = 2 activation signals b01 and c01 at predetermined time intervals, and outputs them to the terminals 107 and 108. The pulse wave generation subcircuits 102 and 103 generate pulse waves d01 and e01 in response to rising edges of the start signals b01 and c01, respectively, and output them from the terminals 104 and 105, respectively.

  Here, when the time difference td generated by the start signals b01 and c01 is set to the pulse width Pw of the pulse wave generated as shown in FIG. 2, the pulse wave generation subcircuits 102 and 103 cause the pulse wave with the time difference of the pulse width Pw. d01 and e01 are generated. The potential difference between the pulse waves d01 and e01 has a waveform as shown by a signal d01-e01 in FIG. If the generation order of the start signals b01 and c01 is changed, the polarity of the generated pulse wave can be reversed. That is, the activation signal b01 is generated at time t1 in FIG. 2, and a pulse wave d01 is generated accordingly. At the subsequent time t2, the activation signal c01 is generated, and a pulse wave e01 is generated accordingly. Next, at time t4, a start signal c01 is generated, and a pulse wave e01 is generated accordingly. At the subsequent time t5, the activation signal b01 is generated, and a pulse wave d01 is generated accordingly. The polarity of the potential difference between the pulse waves d01 and e01 can be inverted as shown by the signal d01-e01 in FIG.

  The pulse wave generation subcircuits 102 and 103 can generate a pulse wave in response to the fall of the start signals b01 and c01, or can generate them in response to both the fall and rise. .

  During the period in which neither of the pulse wave generation subcircuits 102 and 103 generates the pulse waves d01 and e01, that is, the period of Tb shown in FIG. 2, the voltage output from the pulse wave generation subcircuits 102 and 103 is the same voltage. For example, the signal d01-e01, which is the difference between any voltage values, has a voltage value of 0 in the period Tb.

The pulse waves d01 and e01 generated by the pulse wave generation subcircuits 102 and 103 are different from the voltage values in the period Tb (= Tp−P _D ) unlike the cases shown in FIGS. If the signals of the pulse waves d01 and e01 are used as differential signals as shown in the signal d01-e01, the same pulse wave pair as that shown in FIG. 20C is obtained. As shown in FIG. 16C generated in the prior art, it is difficult to use a signal in which the potential of the period Tb (= Tp−P _D ) is biased, but as a differential signal pair as in the first embodiment. When used, these biases are canceled out and can be used as a user-friendly signal. In the period Tb, the voltage value can be freely set, so that the most convenient voltage value for signal generation can be obtained. Normally, a stable pulse signal can be generated by setting the power supply potential with the lowest impedance.

  In the pulse generation circuit 1, since two pulse wave generation sub-circuits 102 and 103 having the same characteristics generate respective signals of the differential signal pair, signal generation with uniform characteristics and good symmetry and low distortion is generated. It becomes possible.

  20 and FIG. 2 are compared, the signal is rounded in FIG. 20 but has an angular shape in FIG. 2, but this is a result of drawing a simplified diagram, Wave generation subcircuits 102 and 103 can obtain a waveform as shown in FIG. 20 by using a circuit that generates a rounded pulse wave. Since the target pulse wave operates at a high speed close to the performance limit of the elements constituting the circuit, in many cases, even a digital circuit automatically outputs a rounded waveform.

  Next, the configuration and operation of the pulse wave generation subcircuit will be described with reference to FIGS. FIG. 3 is a circuit diagram showing the configuration of the pulse wave generation subcircuit, and FIG. 4 is a timing chart for explaining the operation of the pulse wave generation subcircuit.

  The pulse wave generation subcircuits 102 and 103 are composed of a plurality of inverter delay circuits 301 to 309 and MOS transistors 310 to 325 and 327 and 328 which are pulse wave generation logic circuits.

As shown in FIG. 4, the start signal D ₀ input to the terminal 331 propagates through the inverter delay circuits 301 to 309 while being delayed by time td for each stage and the phase is inverted, and is output from each stage. That is, assuming that the signal applied to the terminal 331 is positive logic, XD _i (negative logic) is output when i is an odd number and D _i (positive logic) is output when i is an even number.

The N-channel MOS transistors 313 and 312 are turned on when the output XD ₁ of the inverter delay circuit 301 and the output D ₂ of the inverter delay circuit 302 are at a high potential, respectively, and connect the pulse output terminal 330 to the first potential level V1. Then, P-channel MOS transistor 310 and 311, the output XD ₃ outputs D ₂ and the inverter delay circuit 303 of each inverter delay circuit 302 is conductive during a low potential, connecting the pulse output terminal 330 to the second potential level V2 To do.

Similarly, the N-channel MOS transistors 316, 317, 320, 321, 324, and 325 respectively output the output XD _i-1 and the i _-th output of the i-1th stage (i is an even number of 2 or more) of the inverter delay circuit. Conduction occurs when D _i is at a high potential, and the pulse output terminal 330 is connected to the first potential level V1. Next, the P-channel MOS transistors 314, 315, 318, 319, 322, and 323 are turned on when the i-th stage output D _i and the i + 1-th stage output XD _{i + 1 of the} inverter delay circuit are at a low potential, respectively. The pulse output terminal 330 is connected to the second potential level V2.

  The pulse waveform PulseOut shown in FIG. 4 is obtained by the operation as described above, and can be operated as the pulse wave generation subcircuits 102 and 103 that generate the pulse waveform as shown by the pulse wave d01 or the pulse wave e01 of FIG. .

PulseOut2 of the waveform of FIG. 4 will be described later in the case you start at the rising edge of the start signal D _0. Here, as the first potential level V1 and the second potential level V2, it is possible to use the negative power supply potential VSS and the positive power supply potential VDD of the integrated circuit constituting the circuit, respectively. Any potential may be set.

N-channel MOS transistors 327 and 328 are turned on when XD ₁ and XD ₉ are simultaneously at a high potential, and connect pulse output terminal 330 to first potential level V1. With this operation, the potential output from the pulse wave generation subcircuit during the period Tb can be set. This potential may be any potential other than V1, but the case where the negative power supply potential VSS is taken as V1 is illustrated. In general, VSS is a ground potential and is the most stable potential. The pulse wave generation subcircuit illustrated in FIG. 3 can fix the signal potential to VSS during the period Tb.

  FIG. 18 is a circuit diagram showing the inside of inverter delay circuits 301-309. The P-channel MOS transistor 1902 and the N-channel MOS transistor 1903 constitute an inverter circuit, and the signal input to the terminal 1908 is inverted and output from the terminal 1910 with the delay time td and becomes the delay circuit input of the next stage. . Further, the output is extracted through a small buffer circuit 1905 so that the delay amount of the delay circuit by the P-channel MOS transistor 1902 and the N-channel MOS transistor 1903 is not increased, and the output 1911 is extracted by the buffer circuit 1906. In this way, the MOS transistors 310 to 325 and 327 and 328 in FIG. 3 are driven. In FIG. 3, the buffer circuits 1905 and 1906 are omitted.

  N-channel MOS transistor 1904 is connected between the source terminal of N-channel MOS transistor 1903 constituting the inverter delay circuit and the negative power supply, and P-channel MOS transistor 1901 is P-channel MOS constituting the inverter delay circuit. The transistor 1902 is connected between the source terminal and the positive power supply VDD 1917.

By controlling the gate-source voltages Vbp and Vbn of these P channel MOS transistor 1901 and N channel MOS transistor 1904, the power supply current flowing into the inverter delay circuit can be controlled. Normally, the gate-source voltages Vbp and Vbn are controlled so that their absolute values are equal in order to maintain the symmetry of the rise and fall of the delay circuit output. With this control, the operation speed of the inverter delay circuit can be controlled, and the delay time td can be controlled. In order to generate a pulse having a target frequency spectrum, the voltages at the gate terminals 1907 and 1909 may be controlled so that P _w = td.

FIG. 1 also shows a specific method for matching the carrier wave frequency f ₀ of the pulse wave generated by controlling the current limiting transistor. The phase locked loop 114 includes a phase comparison circuit 109, a low-pass filter 112, and a voltage controlled oscillation circuit 111. The phase comparison circuit 109 compares the phase of the oscillation frequency of the output signal g01 of the voltage controlled oscillation circuit 111 with the reference frequency of the reference signal h01 applied to the terminal 113, and outputs a comparison result signal i01. The low-pass filter 112 removes the high frequency component of the comparison result signal i01 and then negatively feeds back to the control voltage terminal 115 of the voltage controlled oscillation circuit 111. The phase locked loop 114 operates so that the reference frequency and the oscillation frequency of the voltage controlled oscillation circuit 111 coincide. The phase-locked loop 114 can freely set the oscillation frequency of the voltage-controlled oscillation circuit 111 by arranging an appropriate frequency dividing circuit between the voltage-controlled oscillation circuit 111 and the phase comparison circuit 109 or adjusting the reference frequency. Can do. The voltage controlled oscillation circuit 111 is configured by using an inverter delay circuit having the same characteristics as the inverter delay circuits 301 to 309 constituting the pulse wave generation subcircuits 102 and 103. For example, the voltage control oscillation circuit 111 includes the pulse wave generation subcircuits 102 and 103. The inverter delay circuit can be configured using a ring oscillation circuit configured by connecting the inverter delay circuits in an odd-numbered ring shape. In a state where the phase locked loop 114 is phase locked, the delay amount of the inverter delay circuit exactly matches 1 / oscillation period (twice the number of stages) of the voltage controlled oscillator circuit 111.

As shown in FIG. 1, control voltage terminal 115 of voltage controlled oscillation circuit 111 and delay amount control terminals of inverter delay circuits 301 to 309 constituting pulse wave generation subcircuits 102 and 103 (gate terminals 1907 and 1909 in FIG. 18). By making the voltages applied to the same, the delay amounts of the inverter delay circuits constituting them can be matched. Since the delay amount of the delay circuit included in the voltage controlled oscillation circuit 111 constituting the phase locked loop 114 can be freely set according to the reference frequency, the reference frequency may be set so that this delay amount becomes a necessary delay amount. . The phase-locked loop 114 always operates so as to match a predetermined value determined by this reference frequency even if there is a fluctuation in power supply voltage, temperature change, or manufacturing process variation. It is possible to generate a pulse wave having a constant carrier frequency f ₀ regardless of the condition change.

  Next, the configuration and operation of the startup circuit will be described with reference to FIGS. FIG. 5 is a circuit diagram showing the configuration of the startup circuit, and FIG. 6 is a timing diagram for explaining the operation of the startup circuit.

As shown in FIG. 1 and FIG. 2, the activation circuit 101 has two time differences accurately corresponding to the activation start signal a01 input to the terminal 106, that is, Pw (that is, half the period of the carrier frequency f ₀ ). The start signals b01 and c01 must be generated and input to the pulse wave generation subcircuits 102 and 103. Since Pw coincides with the delay time td of the inverter delay circuits 301 to 309 constituting the pulse wave generation subcircuits 102 and 103, the starter circuit 101 is connected to the pulse wave generation subcircuits 102, 103 as shown in FIG. It may be considered that this can be easily generated by using one inverter delay circuit 520 having the same performance as the inverter delay circuits 301 to 309 constituting 103. In other words, the activation start signal a25 input to the terminal 521 is received, the activation start signal a25 is output as it is as the activation signal b25 from the terminal 522, and the activation start signal a25 is delayed by the time td via the inverter delay circuit 520. By outputting the signal c25 from the terminal 523, a signal of time td can be created. However, the activation signals b25 and c25 created in this way are inverted in logic by the action of the inverter delay circuit 520. Since the pulse wave generation sub-circuits 102 and 103 have the same characteristics, it is necessary to start them with the start signal having the same phase. In the circuit as shown in FIG. The generation circuit cannot be configured.

  In order to overcome the problem of the startup circuit shown in FIG. 5B, the startup circuit 101 having the configuration shown in FIG. 5A is proposed. The starter circuit 101 in FIG. 5A generates two signals e05 and f05 in which the rise and fall of the signal occur at the same time, and one of the signals f05 is converted into inverter delay circuits 301 to 103 constituting the pulse wave generation subcircuits 102 and 103. One inverter delay circuit 504 having the same performance as that of 309 is used to delay by the time td and inverted by the operation of the buffer circuit 505. With such a configuration, the activation signal pairs h05 and i05 having the same phase (polarity) and the time difference exactly time td are generated.

  In order to realize the above operation, the startup circuit 101 in FIG. 5A has the following configuration. The inverter 501 generates a signal b05 obtained by inverting the phase of the activation signal a05 input to the terminal 511. As shown in FIG. 6, the signal b05 is accompanied by a delay time td501 by the inverter 501 with respect to the activation signal a05. A slight time difference td 501 between the two signals due to the delay of the inverter 501 can be corrected by the correction circuit 502. That is, the signals a05 and b05 are buffered and amplified by the inverter circuits 512 and 513, respectively. The inverter circuits 512 and 513 have their outputs connected to each other by cross-coupled inverters 514 and 515, and operate so that the signal changes are emphasized by the positive feedback operation of the cross-coupled inverters 514 and 515 at the time of signal transition. And a slight time lag is corrected. By connecting the correction circuits 502 in several stages, signals e05 and f05 in which the rising and falling edges of the signal change completely simultaneously can be generated. FIG. 5A illustrates the case where two stages of correction circuits 502 and 503 are connected in cascade.

  One signal f05 of the signals e05 and f05, the rise and fall of which are generated at the same time, is further input to the inverter delay circuit 504, delayed by time td and inverted in polarity. The buffer circuits 505 and 506 are circuits that perform buffer amplification with the same characteristics, so that the delay amount of the inverter delay circuit 504 is the same as the delay amounts of the inverter delay circuits 301 to 309 constituting the pulse wave generation subcircuits 102 and 103. In addition, they are connected to adjust the output load to be the same. As shown in FIG. 3, the inverter delay circuits 301 to 309 of the pulse wave generation subcircuits 102 and 103 drive the inverter delay circuit and the MOS transistors 310 to 325 in the next stage as loads in order to input signals to the next stage. For this purpose, a buffer circuit 1905 is connected (the buffer circuit is omitted in FIG. 3). The two-phase signal generation circuit 519 includes an inverter 501, correction circuits 502 and 503, an inverter delay circuit 504, and buffer circuits 505 and 506.

  As detailed in FIG. 18, the inverter delay circuits 301 to 309 are directly connected to the next stage of the inverter delay circuit from the terminal 1910 without a buffer, and the MOS transistors 310 to 325 have a small driving capability. The circuit 1905 is amplified and connected to a desired driving capability via a buffer circuit 1906 having a larger driving capability. If the load connected to the inverter delay circuit 504 is not the same as the input of the next stage inverter delay circuit and the small buffer circuit 1905 for signal extraction, the delay amount of the inverter delay circuit 504 constitutes a pulse wave generation subcircuit. The delay amount of the inverter delay circuit is not the same. Therefore, the input impedance of the buffer circuit 505 is adjusted so as to be equal to the total of those loads. A buffer circuit 505 identical to the buffer circuit 1905 shown in FIG. 18 and a dummy load corresponding to the input impedance of the inverter delay circuit at the next stage may be connected to the output of the inverter delay circuit 504. The buffer circuit 506 is connected to guarantee the delay time of the buffer circuit 505.

  As shown in FIG. 6, signals e05 and f05 whose rise and fall change at the same time are generated by delaying the delay time td506 of the buffer circuit 506, the inverter delay circuit 504 and the buffer circuit 505, respectively. A signal i05 generated by delaying the total delay amount td505 + td is obtained. The signal h05 is the same polarity as the signal f05 because the signal h05 is inverted from the signal e05 while the signal i05 is inverted twice. Since the signal e05 and the signal f05 are signals having opposite polarities that change at the same time, the signal h05 and the signal i05 eventually have the same polarity and the time difference is td505 + td−td506. If the buffer circuits 506 and 505 are used in the same characteristics and environment including their loads, td505 and td506 have the same value, and signals h05 and i05 having the same characteristics with a time difference td are obtained.

  AND-OR select circuits 507 and 508 switch the output destination of signals h05 and i05. Terminals 516 and 517 are output terminals of the activation signal pair and correspond to the terminals 107 and 108 in FIG. When the signal k05 applied to the terminal 510 is true (H: high level), the signal h05 is connected to the terminal 517, and vice versa when it is false (L: low level). By the signal k05 input to the terminal 510, the order of the signals generated by the activation signal pair b01 and c01 can be switched as shown in FIG. 2, and the polarity of the generated signal can be changed as shown by the signal d01-e01 in FIG. Can be changed. If this terminal 510 is used, two-phase phase modulation can be applied to the generated pulse wave, which can be used as a modulator of a UWB transmitter. The activation signal selection circuit 518 includes a buffer circuit 509 and AND-OR selection circuits 507 and 508.

  A circuit for performing the modulation can be placed on the output side of the two pulse wave generation sub-circuits 102 and 103. That is, a switch circuit 529 which is an output selection circuit as shown in FIG. 5C is connected to the terminals 525 and 526 after the terminals 104 and 105 in FIG. 1, and signals are taken out from the terminals 527 and 528. Between the two terminal pairs, the output destination can be switched by the switch circuit 529 including the switches 531 to 534 that can be switched by the electric signal m05 applied to the terminal 530, and the polarity of the signal can be switched. As the switches 531 to 534, complementary MOS analog switches or the like can be used. Compared with the case of switching on the input side described above, since the impedance of the switch is in series on the output side, attention is required for the design of the output side circuit. However, as in the former case, the two pulse wave generation subcircuits 102 and 103 and those Since the activation circuit 101 that activates is directly connected and is not switched, the operation of the activation circuit 101 can be made more stable, and accurate pulse generation is facilitated. A more appropriate method can be selected as required.

  According to the present embodiment described above, the following effects can be obtained.

  (1) According to this configuration, a plurality of pulse wave generation sub-circuits having the same characteristics are used, and the starting time of each pulse wave generation sub-circuit is adjusted to stabilize the DC level and to provide a highly symmetrical differential. It is possible to generate a pulse wave. If the predetermined time interval of the m activation signals is set equal to the pulse width Pw of the pulse wave, a differential signal having a phase difference of 180 degrees can be obtained, and if it is half of Pw, an I having a phase difference of 90 degrees is obtained. , Q signals can be obtained.

  (2) Since the pulse wave generation subcircuits (102, 103) can be constituted by inverter delay circuits 301 to 309 and pulse wave generation logic circuits (MOS transistors 310 to 325 and 327 and 328) by a normal semiconductor process. High integration is easy.

  (3) Since the pulse wave generation subcircuit (102, 103) generates a pulse wave at a time interval of the pulse width Pw, it is possible to generate two signals that are 180 degrees out of phase with each other. Since the generated pulse wave is generated by a pulse wave generation sub-circuit having the same characteristics, it is possible to generate a differential pulse wave having a stable DC level and good symmetry.

  (4) The starting circuit 101 generates a two-phase starting signal at a time interval that matches the delay amount of the inverter delay circuits 301 to 309 constituting the pulse wave generating sub-circuit (102, 103) by the two-phase signal generating circuit 519. Therefore, the time interval of the activation signal for activating the pulse wave generation subcircuit (102, 103) can be exactly matched to the pulse width Pw of the pulse wave generated by the pulse wave generation subcircuit (102, 103). .

  (5) Since the activation circuit 101 can perform modulation based on the phase of the data transmitted by the activation signal selection circuit 518, it can be used as a pulse generation circuit suitable for UWB communication.

  (6) Since the pulse generation circuit 1 can be modulated based on the phase of data to be transmitted by providing the switch circuit 529, it can be used as a pulse generation circuit suitable for UWB communication.

  (7) Since the inverter delay circuits 301 to 309 can control the delay amount of the inverter delay circuit by an external control signal, it is possible to correct fluctuations and errors in generated pulses due to manufacturing variations, operating temperatures, and power supply voltage fluctuations. It becomes possible.

(Second Embodiment)
Next, a second embodiment of the pulse generation circuit will be described. In the first embodiment, the two pulse wave generation subcircuits need to output signals from each stage accurately with a delay of time td. If the time td is not accurately delayed, the output pulse signal will cause an error. Inverter delay circuits constituting these pulse wave generation subcircuits cause errors in fine delay amounts and delay amounts due to noise such as jitter due to manufacturing variations, which are alleviated by the method of the second embodiment. The

  The configuration of the pulse generation circuit according to the second embodiment will be described with reference to FIG. FIG. 7 is a circuit diagram showing a configuration of a pulse generation circuit according to the second embodiment. In FIG. 7, inverter delay circuits 701A-, 701A, 701A + are part of the pulse wave generation subcircuit 102 in FIG. 1, that is, a series of inverter delay circuits 301 to 309 shown in FIG. Of these, three consecutive stages are extracted and shown, and the other stages are omitted. Similarly, the inverter delay circuits 701B-, 701B, and 701B + are part of the pulse wave generation subcircuit 103 in FIG. 1, that is, among the series of inverter delay circuits 301 to 309 shown in FIG. 3 are extracted and shown, and the other steps are omitted. If j is an integer of 2 ≦ j ≦ 8, it corresponds to the inverter delay circuits of the (j−1) th, jth and j + 1th stages from the left in FIG. The buffer circuits 702A-, 702A, 702A +, 702B-, 702B, and 702B + having a small driving capability are circuits for taking out signals by reducing the influence on the delay amount of each inverter delay circuit as much as possible. Circuits 703A−, 703A, 703A +, 703B−, 703B, and 703B + are circuits (drivers) for driving the switches.

  Since the inverter delay circuits 701A-, 701A, 701A + (hereinafter referred to as A column) and 701B-, 701B, 701B + (hereinafter referred to as B column) are activated by the delay time td of these inverter delay circuits, the A column is When activated first, the signal changes simultaneously at the j-th stage of the A column and the (j−1) -th stage of the B column, and the manners of the changes are reversed. Conversely, when column B is activated first, the signal changes at the jth stage of column B and j-1st stage of column A at the same time, and the manner of change is in the opposite direction (inversion).

  Signals that are reversed in opposite directions can be corrected by a cross-coupled inverter even if there is a slight timing shift as described in FIG.

  When the cross-coupled inverters 704A-, 704A, 704A + and 704B-, 704B, 704B + with the enable signal terminal are respectively connected as shown in FIG. 7, when the column A is activated first, the enable signal is supplied to the enable signal terminal 708B. And activates (enables) the cross-coupled inverters 704B-, 704B, and 704B + with the enable signal terminal. A disable signal is input to the enable signal terminal 708A so that the cross-coupled inverters 704A−, 704A, and 704A + with the enable signal terminal are inactivated (disabled). On the other hand, when the row B is activated first, an enable signal is applied to the enable signal terminal 708A, and the cross-coupled inverters 704A-, 704A, and 704A + with the enable signal terminal are activated (enabled). Further, a disable signal is input to the enable signal terminal 708B so that the cross-coupled inverters 704B-, 704B, and 704B + with the enable signal terminal are inactivated (disabled).

  With the connection as described above, the cross-coupled inverter is always connected to a node where signals change simultaneously, a small phase shift is corrected, and the switching timing of the MOS transistors 310 to 325 connected in the subsequent stage is corrected. It is possible to minimize the error of the coincident and generated pulse waveform.

  In FIG. 7, the cross-coupled inverters 704A-, 704A, 704A +, 704B-, 704B, and 704B + with the enable signal terminal are output from the buffer circuits 702A-, 702A, 702A +, 702B-, 702B, and 702B + having a small driving capability, respectively. Although connected in between, they may be connected to the outputs of inverter delay circuits 701A-, 701A, 701A +, 701B-, 701B, 701B +. In this case, the delay amount of the inverter delay circuit increases, and it is difficult to use when a pulse having a pulse width close to the element limit is generated, but an error in the delay amount of the inverter delay circuit can be corrected. Since it is corrected at each stage of the inverter delay circuit, it is possible to prevent the error from propagating to the subsequent stage of the inverter delay circuit array, and more accurate pulse generation is possible.

  When the method of connecting the switch circuit 529 of FIG. 5C of the first embodiment is used as the modulation circuit system of the second embodiment, the enable signal is not a cross-coupled inverter with an enable signal terminal. Cross-coupled inverters without terminals can be used, and either A-row or B-row cross-coupled inverters can be omitted.

  The second embodiment is characterized in that, in a predetermined set of pulse wave generation subcircuits, a cross-coupled inverter is connected between output nodes in which the phases of the outputs of the inverter delay circuits constituting the pulse wave generation subcircuit are mutually inverted. There is.

(Third embodiment)
Next, a third embodiment of the pulse generation circuit will be described.

  The configuration of the pulse generation circuit according to the third embodiment will be described with reference to FIG. FIG. 8 is a circuit diagram and a timing diagram showing the configuration of a circuit that limits the pulse width of the start signal of the pulse generation circuit according to the third embodiment.

FIG. 8A is a circuit for limiting the pulse width of the activation start signal, and an activation start signal with a limited pulse width is output from the output terminal 803. The output terminal 803 is connected to the terminal 106 in FIG. 1 or the terminal 511 in FIG. The delay circuit 801 exemplifies a case where three stages of inverter delay circuits having the same characteristics as the inverter delay circuits 301 to 309 constituting the pulse wave generation subcircuits 102 and 103 are cascade-connected. The NAND circuit 802 performs a NAND operation on the signal a08 input to the terminal 804 and the signal b08 obtained by inverting and delaying the signal a08 by the delay circuit 801, thereby limiting the pulse width to 3 × td. The signal c08 is output from the output terminal 803 (td is the delay time of the inverter delay circuit constituting the pulse wave generation subcircuit). With signal c08 output from the output terminal 803 as a starting signal, a pulse wave generating sub circuits 102 and 103 operates as in FIG. 8 (b), the rise of the start signal D ₀ is first generated It overlaps with the period t2 to t3 of the pulse waveform PulseOut. Note D ₀ in FIG. 8 (b) corresponds to the D ₀ of FIG. 4, XD ₁ in FIG. 8 (b), XD ₉ of equivalent to XD ₁ in FIG. 4, and so FIG. 8 (b) Represents a signal waveform of a node corresponding to XD ₉ in FIG.

When the pulse width of the activation start signal is reduced by the operation as described above, the noise 2001 generated at an unnecessary place shown in FIG. 19C and the target pulse 2002 are overlapped. In FIG. 8 (b), t1~t8 occurrence period of interest pulse, T4～t12 is generation period of the false pulses based on the rise of the start signal D _0. Most of the spurious pulses are hidden behind the target pulse, and noise generation at unnecessary places is reduced.

  The circuit does not operate when the pulse width of the start signal is td or less. The pulse width of the start signal must exceed td and be less than the duration of the target pulse. The duration of the pulse is p times td (p is the number of inverter delay circuits constituting the pulse wave generation subcircuit). The shorter the pulse width, the greater the degree of hiding the false pulse in the target pulse.

  The simple method as described above, that is, the pulse width of the activation start signal input to the activation circuit is set to be larger than the delay amount of the delay circuit constituting the pulse wave generation subcircuit and less than the number of stages of the delay circuit. As a result, the influence of noise generated in an unnecessary place can be reduced.

(Fourth embodiment)
Next, a fourth embodiment of the pulse generation circuit will be described.

  The configuration of the pulse generation circuit according to the fourth embodiment will be described with reference to FIG. FIG. 9 is a circuit diagram showing another method for generating a start signal applied to the start circuit of the pulse generating circuit according to the fourth embodiment.

In FIG. 8B, when the activation signal D ₀ is activated not by a single pulse but by a periodic signal, the pulse generation circuit continuously generates short pulses. The generated pulse frequency can be increased to a frequency as high as the limit of the circuit elements.

  In UWB, it is thought that intermittent pulse generation is sufficient, but if continuous pulses can be used, operations such as synchronous acquisition can be performed at high speed, and it is convenient if continuous / intermittent pulse generation can be performed as necessary. good.

  From a simple consideration, it can be seen that the period of the activation start signal needs to be an even multiple of td and not more than n. At longer periods, the generated pulses are not continuous. In the case of an odd multiple instead of an even multiple, the P channel MOS transistors 310, 311, 314, 315, 318, 319, 322, 323 and the N channel MOS transistors 312, 313, 316, 317, 320, 321 in FIG. , 324, 325 are simultaneously turned on, and there is a timing at which the potentials V1 and V2 are short-circuited.

  The period of the start signal must be exactly an even multiple of td. In order to generate this accurate periodic pulse, a ring oscillation circuit is configured as shown in FIG. The ring oscillation circuit forms an oscillation circuit by connecting inverter delay circuits 901, 902, and 903 having the same characteristics as the inverter delay circuits 301 to 309 constituting the pulse wave generation subcircuits 102 and 103 in a ring shape. FIG. 9A illustrates a case where three stages of inverter delay circuits are used. When the inverter delay circuit has three stages, the oscillation period is 6 × td. To be precise, the delay time of the inverter delay circuit differs between the rise and fall, but in order to construct the pulse wave generation subcircuits 102 and 103, the delay time of the inverter delay circuit is required to be equal between the rise and fall. Is done. Therefore, in the above cycle calculation, it is assumed that td is equal at the rise and fall. In the CMOS circuit, the symmetry of rising and falling can be adjusted by the size of the P and N channel transistors.

  In FIG. 9A, the ring oscillation circuit oscillates freely and cannot be synchronized by an external trigger. FIG. 9B shows a ring oscillation circuit that is synchronized by external activation.

  The ring oscillation circuit shown in FIG. 9B is composed of inverter delay circuits 905 and 906 and a NAND gate 907. Since the NAND gate 907 always outputs true (H) when the start terminal 909 is false (L), the circuit operation stops. The NAND gate 907 operates as an inverter when the start terminal 909 is set to H, and starts oscillating in synchronization with the rise of the start terminal.

  In the ring oscillation circuit shown in FIG. 9B, since the ring oscillation circuit includes a NAND gate, it is difficult to accurately set the oscillation period to an even multiple of td. FIG. 9C shows one method for solving this problem.

  The ring oscillation circuit shown in FIG. 9C includes NAND gates 910, 911, and 912 instead of the inverter delay circuits 905 and 906 shown in FIG. 9B. The NAND gates 910, 911, and 912 have the same configuration, and the internal structure will be described as a representative of the NAND gate 912. P-channel MOS transistors 922 and 923 and N-channel MOS transistors 924 and 925 constitute a NAND gate. In order to limit the current, a P-channel MOS transistor 920 is connected between the sources of the P-channel MOS transistors 922 and 923 and the power supply VDD 914, and an N-channel MOS transistor 921 is connected between the source of the N-channel MOS transistor 924 and the ground potential. Connect. A voltage is externally applied to the gates of the P-channel MOS transistor 920 and the N-channel MOS transistor 921 through terminals 915 and 916, respectively, and the operation speed of the NAND gates 910 to 912 is controlled. The buffer circuits 917, 918, and 919 are connected to take out a signal to the outside.

  In the ring oscillation circuit shown in FIG. 9C, NAND gates 910 and 911 operate as inverter delay circuits by connecting one input terminal to the power supply VDD 914 so that it is always H. For the inverter delay circuit constituting the pulse wave generation subcircuit, td can be accurately matched by replacing it with an inverter delay circuit using a NAND gate.

  In the ring oscillation circuit shown in FIG. 9C, the same operation can be performed by replacing the P-channel MOS transistor and the N-channel MOS transistor and using the NOR gate instead of the NAND gate.

  Each of the ring oscillation circuits shown in FIG. 9C has an advantage that it can be configured with only a logic circuit, but requires a slightly larger number of transistors. FIG. 9D shows one method for solving this problem.

  The ring oscillation circuit shown in FIG. 9D can be synchronized using inverter delay circuits 930, 931, and 932. Inverter delay circuits 930, 931, and 932 have the same characteristics as inverter delay circuits 301 to 309 constituting pulse wave generation subcircuits 102 and 103. In order to avoid duplication, description of the internal structure will be made on behalf of the inverter delay circuit 931. In inverter delay circuit 931, P-channel MOS transistor 934 and N-channel MOS transistor 935 constitute an inverter. In order to limit the current, a P-channel MOS transistor 933 is connected between the source of the P-channel MOS transistor 934 and the power supply VDD 941, and an N-channel MOS transistor 936 is connected between the source of the N-channel MOS transistor 935 and the ground potential. To do. A voltage is externally applied to the gates of P channel MOS transistor 933 and N channel MOS transistor 936 through terminals 942 and 943, respectively, to control the operation speed of inverter delay circuits 930, 931, and 932. The buffer circuits 937, 938, and 939 are connected to extract a signal to the outside.

  The ring oscillation circuit shown in FIG. 9D switches the control voltage applied to the current limiting transistor (at least one of the P and N channel MOS transistors) of any one of the inverter delay circuits by a switch 944. FIG. 9D illustrates a case where the control voltage applied to the gate of the current limiting N-channel MOS transistor 940 of the inverter delay circuit 930 is switched by the switch 944. Since the voltage applied to the gate of the N channel MOS transistor 940 is turned off when the potential of the terminal 943 is switched to the ground potential by the switch 944, the output of the inverter delay circuit 930 becomes H. At this time, the output of the inverter delay circuit 931 becomes L and the output of the inverter delay circuit 932 becomes H and stops. When the switch 944 is switched and the potential of the terminal 943 is applied to the gate of the N-channel MOS transistor 940, the circuit forms a ring oscillation circuit and starts oscillation in synchronization therewith.

  However, the ring oscillation circuit illustrated in FIG. 9D requires attention to the timing for switching the switch 944. It has been described that the inverter delay circuits 930, 931, and 932 output H, L, and H, respectively, when the N-channel MOS transistor 940 is off. However, when the output of the inverter delay circuit 932 is H, the transistor 945 is also turned off, so that the inverter delay circuit 930 enters a floating state. If the inverter delay circuit 930 is not switched at the timing when the output is surely set to H, the input potentials of the inverter delay circuits 931 and 932 and the buffer circuits 937, 938 and 939 are not determined, causing current leakage. When the transistor 940 is turned off at the timing when the output of the inverter delay circuit 930 is surely H, the transistor 945 is turned off after the delay time of the inverter delay circuits 931 and 932, during which the inverter delay circuit 930 is turned off. The charge is stored in a small capacity interposed between the output node of the output node and the input node of the buffer circuit 937 and the inverter delay circuit 931, and the node is held at H to determine the input potential of the subsequent circuit. Such timing control is achieved by switching the switch 944 when the output of the buffer circuit 937 becomes H.

  When the start signal is generated by the circuit configuration as described above and the pulse generation circuit is started, the start signal input to the start circuit is a period whose cycle is an even multiple of the delay amount of the delay circuit constituting the pulse wave generation subcircuit. It can be a signal, and an extremely high-speed pulse wave can be continuously transmitted. In the fourth embodiment, continuous / intermittent pulses can be switched and generated as necessary, and if a continuous pulse is used in synchronous acquisition or the like in a UWB transceiver, the capturing operation can be performed at high speed. It is highly useful.

(Fifth embodiment)
Next, a fifth embodiment of the pulse generation circuit will be described. In the pulse wave generation subcircuit of FIG. 3 described in the first embodiment, when i is an even number, (1) when the logical product of XD _i-1 and D _i is true, N-channel MOS transistors connected in series Is turned on and connected to the potential V1. (2) When the logical product of XD _i and D _{i + 1} is true, the P-channel MOS transistor connected in series is turned on and connected to the potential V2, thereby starting signal D _A series of pulse waves were generated in response to the falling of ₀ .

Further, the switching logic of the switch is slightly changed. (3) When the logical product of D _i-1 and XD _i is true, the P-channel MOS transistor connected in series is turned on and connected to the potential V2, and (4 ) When the logical product of D _i and XD _{i + 1} is true, changing the wiring so that the N-channel MOS transistor connected in series is connected to the potential V1 in response to the rise of the start signal D ₀ A pulse is generated (see PulseOut2 in FIG. 4).

  In this way, not only can the noise 2001 generated in unnecessary places shown in FIG. 19C be suppressed, but also a pulse can be generated at both poles of the changing point where current is consumed in the inverter delay circuit. As a result, power consumption is saved. That is, in FIG. 4, in the pulse wave generation subcircuit of the first embodiment, the pulse is generated only between t1 and t9 at t'1 to t'9 and t1 to t9 where the inverter delay circuit array consumes power. do not do. According to the above method, since pulses are generated at both t′1 to t′9 and t1 to t9, power consumption per pulse can be saved.

  The configuration of the pulse generation circuit according to the fifth embodiment will be described with reference to FIG. FIG. 10 is a circuit diagram showing a pulse wave generation subcircuit of the pulse generation circuit according to the fifth embodiment.

The terminal 1001 is an input terminal for the start signal D ₀ , and the inverter delay circuit array 1002 is an output XD _i−1 , D _i (i is 2 ≦ ≤) in which D ₀ is delayed by td and inverted in logic by the inverter delay circuit. i ≦ 10). These signals are output via a buffer.

  The transistors in the alternate long and short dash line 1011 are switching arrays in which two P-channel MOS transistors are connected in series, and when the gate potentials of the two P-channel MOS transistors simultaneously become L (the above (2) or (3) And the pulse output terminal 1014 is connected to the potential V2 connected to the terminal 1013. The transistors in the alternate long and short dash line 1012 are switching arrays in which two N-channel MOS transistors are connected in series, and when the gate potentials of the two N-channel MOS transistors simultaneously become H (the above (1) or (4) And the pulse output terminal 1014 is connected to the potential V1 connected to the terminal 1015.

Switching array in two-dot chain line 1016 is operative to generate a pulse at the falling edge of the start signal D _0. Switching array in two-dot chain line 1017 is operative to generate a pulse at the rising edge of the start signal D _0.

A dotted line 1003 or a dotted line 1004 is a NAND gate bank, and each output of the inverter delay circuit array 1002 is connected to one input terminal. The output terminal of the NAND gate is a gate of each transistor of the switching arrays 1011 and 1012. Connected to. Similarly, a dotted line 1005 or a dotted line 1006 is a NOR gate bank, and each output of the inverter delay circuit array 1002 is connected to one input terminal. The output terminal of the NOR gate is connected to each transistor of the switching arrays 1011 and 1012. Connected to the gate. By applying a predetermined potential to the control terminals 1007, 1008, 1009, and 1010 of these gates, transmission from each output of the inverter delay circuit array 1002 to the switching arrays 1016 and 1017 is controlled. That is, when the control terminals 1007 and 1010 are set to H and the control terminals 1008 and 1009 are set to L, the signal of the inverter delay circuit array 1002 is transmitted only to the switching array 1016, and the switching array 1017 is controlled to be turned off. _A pulse wave is generated at the falling edge of _zero . Conversely, if the control terminals 1007 and 1010 are set to L and the control terminals 1008 and 1009 are set to H, the signal of the inverter delay circuit array 1002 is transmitted only to the switching array 1017, and the switching array 1016 is all controlled to be turned off. _A pulse wave is generated at the rising edge of _zero . The control terminal 1007, 1008 H, the control terminals 1009 and 1010 is L, the signal of the inverter delay circuit array 1002 to the switching array 1016 and 1017 is transmitted, the pulse wave is generated at the falling and rising of the both edges of the D ₀ Is done.

Advantages of switching the one-edge activation or both-edge activation of D ₀ using the gate bank will be described below. In the inverter delay circuit, there may be a slight difference between the delay time from the rise of the input signal to the fall of the output signal and the delay time from the fall of the input signal to the rise of the output signal. If there is such a difference, an imbalance such as a difference in amplitude value occurs between a pulse generated at the rising edge of D ₀ and a pulse generated at the falling edge. This effect becomes more pronounced when trying to generate thin pulses. By switching between single-edge activation or double-edge activation with such a gate bank, select double-edge activation when you want to prioritize power consumption, and select single-edge activation when you want to generate an accurate pulse. It becomes possible.

Turning now again better 4, when starting the pulse at the rising edge of the D ₀ is that the pulse output is generated in the td delay from the rising edge of D _0, the falling of D ₀ When starting, a pulse output is generated with a delay of 2 td from the falling edge of D ₀ . When the difference in time from the start edge to the generation of the pulse becomes a problem, it can be adjusted to be equal. For this purpose, it delayed by td the rise of D _0. In this method, the circuit shown in FIG. 8A can be used. However, the delay circuit 801 may be composed of two stages, and the delay time of each stage may be set to td / 2, that is, the total delay time of the two stages may be equal to td. A method of making a delay circuit whose delay time is exactly td / 2 will be described later.

In FIG. 10, there are two NAND gates or NOR gates connected to XD ₁ and XD ₉ whose output signals are open (not connected anywhere). These are connected as dummy loads in order to align the loads of the buffers of the outputs XD ₁ and XD ₉ of the inverter delay circuit array 1002 with other output signals. Thereby, the pulse waveform error before and after the generated pulse wave can be reduced. For this reason, a pulse wave having a longer period is generated at the leading edge of the generated pulse, and a shorter pulse wave is generated at the trailing edge. In FIG. 10, the pulse output terminal 1014 is not connected anywhere during the period from t′9 to t1 and the period from t9 to t′1 in which no pulse wave is generated in the timing chart of FIG. In order to solve this problem, it is possible to fix this period to a predetermined potential (for example, V1) by adding a switch circuit and a simple logic circuit as in the first embodiment of FIG. In this case, the output signal of the above unused gate can be used. Since the implementation is easy, the following description is omitted.

  With the configuration as in the fifth embodiment, it is possible to reduce power consumption per pulse in pulse generation.

(Sixth embodiment)
Next, a sixth embodiment of the pulse generation circuit will be described. In the fifth embodiment, the case where the predetermined amount of the start time difference between the two pulse wave generation sub-circuits is Pw (= td) has been described. In the sixth embodiment, a case where Pw / 2 (= td / 2) is described.

  The configuration of the pulse generation circuit according to the sixth embodiment will be described with reference to FIG. FIG. 11 is a circuit diagram showing a pulse generation circuit according to the sixth embodiment.

  FIG. 11A is a block diagram illustrating a pulse generation circuit that generates a set of pulse signals that are 90 degrees out of phase with each other, and FIG. 11B is a timing diagram illustrating the operation of the pulse generation circuit. .

  The activation circuit 1101 receives the activation start signal a11 input to the terminal 1109, generates two activation signals b11 and c11 having a time difference Pw / 2 (Pw is half of the pulse carrier cycle), and outputs the signals to the terminals 1110 and 1108. To do.

  The pulse wave generation subcircuits 1102 and 1103 exemplify a case where the pulse wave generation subcircuits 102 and 103 shown in FIG. 3 are used. The delay amount td per stage of the inverter delay circuit constituting the pulse wave generation subcircuits 1102 and 1103 is adjusted to be equal to Pw, and the pulse wave generation subcircuits 1102 and 1103 have a time difference td / 2 = Pw / 2, that is, pulse waves d11 and e11 having a quarter of the pulse carrier period are generated (see FIG. 11B). The time difference of Pw / 2 means that the phase difference is 90 degrees. According to the above method, a pulse pair (I, Q signal pair) having a phase difference of 90 degrees necessary for synchronous detection of the receiver can be generated.

  The pulse waves d11 and e11 of the pulse wave generation subcircuits 1102 and 1103 are input to the orthogonalization circuit 1106, which is an addition / subtraction circuit, to correct slight errors in the activation signals b11 and c11 generated by the activation circuit 1101. In other words, the time difference between the activation signal pairs needs to be exactly td / 2, but an inverter delay circuit with a delay amount td constituting the pulse wave generation subcircuit cannot be used for the signal generation. In the sixth embodiment, a method of correcting an error on the time difference td / 2 of the activation signal pair will be described.

  The orthogonalization circuit 1106 is a matrix circuit that outputs vector differences and sums. If the outputs of the orthogonalizing circuit 1106 are f11 and g11, then f11 = d11−e11 and g11 = d11 + e11.

  The fact that the signals f11 = d11−e11 and g11 = d11 + e11 are orthogonal is shown by the following. That is, the inner product of the sum and difference of the vectors d11 and e11 is <d11 + e11, d11−e11> = <d11, d11> + <e11, d11> − <d11, e11> − <e11, e11> = <d11, d11>. − <E11, e11> If the absolute values of d11 and e11 (the peak values in the case of signals) are equal, <d11, d11> and <e11, e11> are equal, and the inner product <d11 + e11, d11-e11> is zero. That is, the signals f11 = d11−e11 and g11 = d11 + e11 are orthogonal to each other. For the calculation of the sum and difference, an analog addition / subtraction amplifier circuit can be used. <A, b> represents an inner product of the vectors a and b.

  Since the pulse waves d11 and e11 are generated from the pulse wave generation sub-circuits 1102 and 1103 having the same characteristics, the peak values are naturally equal, and if the orthogonalization circuit 1106 creates the sum and difference of the pulse waves d11 and e11, The output signals are orthogonal. In FIG. 11 (b), a digital angular signal waveform is used for easy understanding. Actually, the signal waveform is rounded and an analog signal due to high-speed operation, but the same explanation is possible. The signals d11 and e11 have the same peak value (amplitude value), but the signals f11 and g11 that are the sum and difference are not necessarily equal. In particular, the difference between the crest values of f11 and g11 increases as the pulse waves d11 and e11 deviate from orthogonality. The amplitude limiting circuit 1107 outputs the signals f11 and g11 from the output terminals 1104 and 1105 with the same amplitude.

  The activation circuit 1101 of the sixth embodiment generates activation signals b11 and c11 having a time difference corresponding to half of the pulse width Pw of the generated pulse, and the pulse wave generation subcircuits 1102 and 1103 generate activation signals b11 and c11. Since it is configured to include two circuits having the same characteristics that generate predetermined pulse waves in response, it is possible to generate two pulse waves d11 and e11 that are 90 degrees out of phase with each other. Since the generated pulses are generated by the pulse wave generation sub-circuits 1102 and 1103 having the same characteristics, pulse waves (I and Q signals) having a stable DC level and a phase difference of 90 degrees are generated. It becomes possible to do. In the sixth embodiment, a circuit example for generating single-ended I and Q signals has been described.

  The sixth embodiment further includes an orthogonalizing circuit 1106 that adds and subtracts the pulse waves d11 and e11 of the pulse wave generation subcircuits 1102 and 1103, so that the pulse wave generation subcircuits 1102 and 1103 include the pulse wave generation subcircuits 1102 and 1103. It is possible to further increase the orthogonality of the generated I and Q signals.

(Seventh embodiment)
Next, a seventh embodiment of the pulse generation circuit will be described. In the seventh embodiment, a configuration example of the activation circuit 1101 in FIG. In particular, in the pulse wave generation subcircuit, in order to generate a pulse wave at a high speed close to the performance limit of the element, the delay amount of the inverter delay circuit constituting the pulse wave generation subcircuit is often extremely short, and the delay amount td Even if the delay circuit can be realized, a delay circuit having a delay amount of td / 2 may not be configured. The seventh embodiment shows a method for accurately generating a time difference of td / 2 even with such an extremely short delay amount td.

  FIG. 12 is a block diagram showing a startup circuit according to the seventh embodiment, and FIG. 13 is a timing chart for explaining the operation of the startup circuit.

  In FIG. 12, a terminal 1201 is a terminal for inputting a start start signal a12. The activation start signal a12 input here is input to the four-stage inverter delay circuit array 1204 and the six-stage inverter delay circuit array 1203 via the NOR gate 1224 and the buffer circuit 1202. When the delay amount is adjusted so that the timings of the signals c12 and d12 of the inverter delay circuit trains 1203 and 1204 activated simultaneously by the start signal a12 coincide, the ratio of the delay amount per stage of the inverter delay circuit trains 1203 and 1204 is 1: 1.5. Therefore, if the output signal is taken out from the inverter delay circuit at the first stage of each of the inverter delay circuit trains 1204 and 1203 and used as the start signals 1222 and 1223 of the pulse wave generation sub-circuits 1102 and 1103, the start time difference is Pw / 2 (= td / 2). By the method as described above, a start signal pair having a time difference shorter than td can be created without using an inverter delay circuit having a delay amount shorter than td.

  A method for matching the delay amounts of the six-stage inverter delay circuit array 1203 and the four-stage inverter delay circuit array 1204 will be described below with reference to FIGS.

  When the activation start signal a12 is input to the terminal 1201, the signal b12 is input to the two inverter delay circuit arrays 1203 and 1204 with a delay by the NOR gate 1224 and the buffer circuit 1202. The buffer circuit 1202 and the buffer circuits 1206 and 1207 provided on the output side of the inverter delay circuit arrays 1203 and 1204 are provided to make the input / output conditions of the two inverter delay circuit arrays 1203 and 1204 the same. The delay time of one stage of the inverter delay circuit constituting the inverter delay circuit array 1203 is adjusted to be equal to td by the voltage applied to the delay control terminal 1205.

  The inverter delay circuit array 1203 outputs a signal c12 with a delay of 6 td from the signal b12. The output signal of the four-stage inverter delay circuit array 1204 is d12. The two buffer circuits 1208 and 1209 input the signal c12 via the buffer circuit 1206 and output signals e12 and f12. The output of the buffer circuit 1208 is connected to a load capacitor 1212 that is adjusted so that the signal e12 is output with a delay of Δt from the signal f12. Similarly, the two buffer circuits 1210 and 1211 input the signal d12 via the buffer circuit 1207 and output the signals g12 and h12. The output of the buffer circuit 1210 is connected to a load capacitor 1213 that is adjusted so that the signal g12 is output with a delay of Δt from the signal h12. The buffer circuits 1206 and 1207 are set to the same characteristics, the buffer circuits 1208 and 1210 are set to the same characteristics, the buffer circuits 1209 and 1211 are set to the same characteristics, and the load capacitors 1212 and 1213 are set to the same characteristics. Then, the delay time from the signal c12 to the signal e12 is equal to the delay time from the signal d12 to the signal g12. Further, the delay times of the signals c12 → f12 and d12 → h12 can be made equal.

  In the RS flip-flop circuits 1214 and 1215 using two NAND gates, when the two input terminals change from L and L to H and H with different delay times, the output terminal on the side changed with delay is H. Is output and held. In the seventh embodiment, the RS flip-flop circuits 1214 and 1215 are used to detect which of the signals e12 and h12 and f12 and g12 have changed with a delay. FIG. 13 illustrates the case where the signal d12 is delayed by Δt or more than the signal c12.

  The two output signals i12 and j12 of the RS flip-flop circuit 1214 detect the later rising edge of the input signals e12 and h12. Since the signal h12 rises later, the corresponding output signal j12 holds H, and the signal i12 becomes L.

  Similarly, the two signals k12 and l12 of the RS flip-flop circuit 1215 detect the later rising edge of the input signals f12 and g12. Since the signal g12 rises later, the corresponding output signal l12 holds H, and the signal k12 becomes L.

  Now, when both the signal i12 and the signal k12 are L, the signal c12 rises more than Δt than the signal d12, and when both the signal j12 and the signal l12 are L, the signal d12 Indicates that it rises at least Δt earlier than the signal c12. At other times, the time difference between the rising edges of the signal c12 and the signal d12 is within Δt.

  The NOR gate 1216 outputs H when both the signal i12 and the signal k12 are L, and controls the charge pump 1220 to inject charges into the low-pass filter 1221. Further, the NOR gate 1217 outputs H when both the signal j12 and the signal 112 are L, and controls the charge pump 1220 to extract the charge from the low-pass filter 1221. Thus, when both the signal i12 and the signal k12 are L, that is, when the signal c12 is earlier than the signal d12 by Δt or more, the delay amount control terminal of the inverter delay circuit row 1204 is set so that the rising of the signal d12 is advanced. Increase the voltage of 1225. Conversely, when both the signal j12 and the signal l12 are L, that is, when the signal c12 is delayed by Δt or more than the signal d12, the delay amount control of the inverter delay circuit array 1204 is delayed so that the rising of the signal d12 is delayed. The voltage at the terminal 1225 is lowered. At other times, the charge pump 1220 is inactivated, and the low-pass filter 1221 holds the voltage of the delay amount control terminal 1225 of the inverter delay circuit array 1204.

  If Δt is set to be within 4 times the allowable error of 1.5 × td, the delay amount per stage of the inverter delay circuit array 1204 is always within the range of 1.5 × td ± allowable error. The control voltage is corrected.

  The NOR gate 1218 detects a case where the control voltage of the inverter delay circuit array 1204 needs to be corrected. At this time, the NOR gate 1219 feeds back the output of the inverter delay circuit array 1203 to the inverter delay circuit array 1203 via the NOR gate 1224 to form a ring oscillation circuit. The ring oscillation circuit thus formed continues to oscillate until the voltage at the delay amount control terminal 1225 of the inverter delay circuit row 1204 is corrected and the difference in delay amount falls within Δt, and the charge pump 1220 is operated to supply the low-pass filter 1221 to the low-pass filter 1221. Continue charging and discharging.

  The startup circuit 1101 in the seventh embodiment includes an inverter delay circuit having the same delay amount as the delay amount of the inverter delay circuit constituting the pulse wave generation sub circuit, and an inverter delay having a delay amount of 1.5 times the delay amount. It is characterized by including a circuit.

  According to the seventh embodiment, it is possible to generate an activation signal having a time difference shorter than td, that is, td / 2 without requiring an inverter delay circuit having a delay amount shorter than td. This is effective when high-speed operation is required to the limit of device performance.

(Eighth embodiment)
Next, an eighth embodiment of the pulse generating circuit will be described. FIG. 14 is a block diagram showing a pulse generation circuit according to the eighth embodiment.

  The pulse generation circuit shown in FIG. 14 is an example using four pulse wave generation subcircuits. The activation circuit 1401 generates four activation signals a14, b14, c14, d14 having a time difference of Pw / 2 in response to the activation start signal input to the terminal 1408, and outputs them from the terminals 1409, 1410, 1411, 1412, respectively. To do. The four pulse wave generation sub-circuits 1402, 1403, 1404, and 1405 having the same characteristics receive the start signals a14, b14, c14, and d14, generate pulse waves e14, f14, g14, and h14 having a pulse width Pw, and a terminal 1413. , 1414, 1415, 1416. The specific configurations of the pulse wave generation subcircuits 1402, 1403, 1404, and 1405 are the same as those in FIG. 3 or FIG. 10, and the delay amount per stage of the inverter delay circuit configuring these pulse wave generation subcircuits is td. If td = Pw is set, the phases of the pulse waves e14, f14, g14, and h14 can be shifted by 90 degrees. If the pulse waves e14, g14 and f14, h14 are set as one set, they can be regarded as differential signals having a phase difference of 90 degrees, that is, I, Q signals.

  These pulse waves e14, g14 and f14, h14 are input to the orthogonalizing circuit 1406, and after correcting the phase error caused by a slight error in td, the amplitude is adjusted by the amplitude limiting circuit 1407 via the terminals 1417-1420. , Output from terminals 1421 to 1424. The configuration of the orthogonalizing circuit 1406 has been described in the sixth embodiment. Taking the sum and difference is easier than in the sixth embodiment because a differential signal pair is obtained. That is, when four differential amplifier circuits having the same characteristics are used and pulse waves e14 and h14, g14 and f14, e14 and g14, and f14 and h14 are input to each differential amplifier circuit, the output of the differential amplifier circuit is e14-h14, g14-f14 and e14-g14, f14-h14 are amplified, and these signals are differential signals representing the sum and difference of the vectors described in the sixth embodiment.

  FIG. 14B shows a specific configuration example of the activation circuit 1401. The four inverter delay circuits 1432, 1434, 1436, and 1438 are inverter delay circuits whose delay amount is td / 2. These inverter delay circuits 1432, 1434, 1436, and 1438 are half of the delay amount td of the inverter delay circuits constituting the pulse wave generation subcircuits 1402 to 1405, and therefore the same circuit cannot be used. Since the error can be corrected, accuracy is not so required.

  In the inverter delay circuit having a delay amount of td / 2, the ratio of the drain capacitance of the MOS transistors 1902 and 1903 in FIG. 18 to the total of the parasitic capacitance parasitic to the input capacitance and wiring of the buffer circuit 1905 is 1: 2. In addition, by adjusting the size of the buffer circuit 1905, an inverter delay circuit having a delay amount of 1: 2 can be realized. In this method, since the error factor is determined only by mask accuracy in the manufacturing process of the semiconductor integrated circuit, there is little variation in the ratio of delay amounts, and the ratio of delay amounts can be stably obtained with respect to temperature and power supply voltage fluctuations. .

  The start-up circuit 1401 cannot be used when high-speed operation is required to the extent of device performance. FIG. 14C shows a circuit example of the activation circuit 1401 when such high-speed operation is required. The delay circuits 1444, 1446, 1448 with the delay amount td and the delay circuit 1442 with the delay amount 1.5td are connected as shown in FIG. 14C, and the activation signals a14, b14, c14, d14 of the pulse wave generation subcircuit are connected to the terminals. If they are extracted from 1447, 1443, 1449, 1445, the activation signals a14, b14, c14, d14 become signals with a time difference of td / 2.

  In the eighth embodiment, the activation circuit 1401 generates four activation signals a14, b14, c14, d14 having a time difference corresponding to half of the pulse width Pw of the generated pulse, and the activation signals a14, b14, c14, d14. It is characterized by including four pulse wave generation sub-circuits 1402, 1403, 1404, and 1405 having the same characteristics for generating a predetermined pulse wave in response to each of them.

  With this configuration, it is possible to generate four signals that are 90 degrees out of phase, that is, two sets of differential signals (I and Q differential signals) that are 90 degrees out of phase.

(Ninth embodiment)
Next, a ninth embodiment of the pulse generating circuit will be described.

  FIG. 15 is a diagram for explaining a UWB communication apparatus using the pulse generation circuits of the first to eighth embodiments, and shows an example of application to a UWB transceiver.

  The pulse generation circuit 1501 includes the activation circuit 101 in FIG. 5A and the switch circuit 529 in FIG. 5C, and the UWB transmission circuit 1550 is configured by using these. That is, the terminal 1503 is a terminal for inputting an activation start signal, and corresponds to the terminal 519 in FIG. A terminal 1504 is an input terminal for data to be transmitted, and corresponds to the terminal 510 in FIG. 5A or the terminal 530 in FIG. When an activation start signal is input to terminal 1503, pulse generation circuit 1501 generates one pulse, but the polarity of the output pulse is switched and modulated in accordance with the value of transmission data input to terminal 1504. This modulation method can be regarded as two-phase modulation (BPM) of a pulse. There are two balanced antennas 1502 of the pulse generation circuit 1501 in FIG. 15, and generate differential pulse signals. Therefore, a transmitter using this pulse generation circuit 1501 can drive a balanced antenna 1502. As a result, a large output can be obtained even at a low voltage.

  In addition to this, the transmitter can also perform pulse position modulation in which a delay circuit is connected to the activation signal and the delay time is switched according to the transmission data. These methods can also be used for pulse position modulation (PPM).

  Furthermore, if a four-phase pulse oscillation circuit shown in FIG. 14A is used, pulse modulation of IQ orthogonal modulation becomes possible. That is, as the activation circuit 1401 in FIG. 14A, the activation signals a14 and c14 of the pulse wave generation subcircuits 1402 and 1404 are paired, and the activation signals b14 and d14 of the pulse wave generation subcircuits 1403 and 1405 are paired. By using two start-up circuits shown in FIG. 5A, each of the I and Q signals is modulated (QPM: Quadrature Phase Modulation), and terminals 1421 and 1422 and terminals 1423 and 1424 are connected. This can be realized by adding the signals and feeding the balanced antenna 1502 as two signals. For the modulation, the switch circuit shown in FIG. 5C may be inserted into the terminal on the output side.

  A circuit including the reception antenna 1505 shows the configuration of the reception circuit 1551. That is, the UWB pulse signal received by the receiving antenna 1505 is amplified by the low noise amplifier circuit 1506 and input to the I and Q mixer circuits 1507 and 1508. Mixer circuits 1507 and 1508 perform multiplication with the template pulse generated by template pulse generation circuit 1509 and send the result to integration circuits 1510 and 1511. The integrating circuits 1510 and 1511 remove the high frequency components of the signals mixed (multiplied) by the mixer circuits 1507 and 1508 and perform demodulation. The circuit 1512 determines the transmitted bit by looking at the strength of each signal, and restores the original transmission data.

  Here, the pulse generation circuit of FIG. 14A can be used as the template pulse generation circuit 1509. The pulse generation circuit of FIG. 14A can oscillate an IQ two-phase differential signal, and a differential circuit such as a low noise amplifier circuit 1506 or mixer circuits 1507 and 1508 can be used. To do. The differential circuit is suitable for canceling common-mode noise and low-voltage operation, and is convenient for a low-power low-noise device configuration. Further, when the IQ template pulse generation circuit 1509 using the pulse generation circuit shown in FIG. 14A is used, efficient reception is possible not only in QPM but also in BPM and PPM. That is, when modulating BPM or PPM, it is possible to use a method in which the I channel is used for data demodulation and the Q channel is used for tracking. This is because if the template generation timing is adjusted so that the Q channel output is always 0, the output amplitude value is maximized in the I channel, so that synchronous detection can be tracked by such control.

  It is of course possible to use other circuits as the template pulse generation circuit 1509, that is, the circuits of FIGS.

  This pulse generation circuit can generate a plurality of pulse signals having a predetermined phase difference with a simple circuit. If a signal pair with a phase difference of 180 degrees is generated, a balanced pulse signal is obtained, and if four signals are generated with a phase difference of 90 degrees, differential I and Q signals can be obtained. The pulse signal generated by the pulse generation circuit can accurately control the phase difference, and can generate a signal with little variation in amplitude and the like with good balance and low distortion. Therefore, the pulse generation circuit has all the required specifications such as differential signal generation, generation of I and Q signals, and low distortion necessary for improving the performance of the UWB transceiver. Therefore, if this pulse generation circuit is applied to a UWB transceiver, a high-performance device can be realized.

  Further, if this pulse generation circuit is realized by a CMOS integrated circuit, power is consumed only during the transition time at the time of pulse generation and there is no standby current. When applied to a communication device, it is possible to always operate with minimum power consumption according to the amount of information (bit rate) to be transmitted.

  In particular, UWB communication is suitable for high-speed communication over a short distance, and a transmission amount of Gbps (gigabit / second) or more, which is impossible with conventional wireless communication, can be expected. Such a transmission amount is a value that could not be realized in any of the conventional wireless communication systems, and various difficulties are involved depending on the wired transmission path. The operation of the circuit performing UWB communication (IR) by pulses is intermittent, and it is sufficient that the circuit is powered only when the pulses are active. This greatly saves the power consumed by the circuit. Furthermore, since the operation is intermittent, there is little interference with the operation of the device in which this system is incorporated, and the interference received by the system from the device. When UWB communication using a pulse generation circuit is used for data transmission, it is possible to obtain lower power, higher speed and lower external interference, and higher interference resistance than conventional connection using a copper wire (wired line). Therefore, when the UWB communication apparatus is used for large-capacity data transmission in the very short distance in the same housing, a very useful system can be constructed.

  As mentioned above, although the case where the predetermined amount of the activation time difference is td, td / 2 has been described in the embodiment, it is not limited to such an embodiment. For example, if 2td / 3, a three-phase pulse signal set having a phase difference of 120 degrees is obtained. A signal having an arbitrary phase difference can be obtained by adjusting a predetermined amount of the start-up time as necessary.

  The effect is particularly great when used for UWB communication using short pulses.

The block diagram which shows the structure of the pulse generation circuit which concerns on 1st Embodiment. FIG. 3 is a timing chart showing the operation of the pulse generation circuit according to the first embodiment. The circuit diagram which shows the structure of a pulse wave generation subcircuit. The timing diagram explaining operation | movement of a pulse wave generation subcircuit. The circuit diagram which shows the structure of a starting circuit. The timing diagram explaining operation | movement of a starting circuit. The circuit diagram which shows the structure of the pulse generation circuit which concerns on 2nd Embodiment. The circuit diagram and timing diagram which show the structure of the circuit which restrict | limits the pulse width of the starting signal of the pulse generation circuit which concerns on 3rd Embodiment. The circuit diagram which shows the other method of generating the starting signal given to the starting circuit of the pulse generation circuit which concerns on 4th Embodiment. The circuit diagram which shows the pulse wave generation subcircuit of the pulse generation circuit which concerns on 5th Embodiment. A circuit diagram showing a pulse generation circuit concerning a 6th embodiment. The block diagram which shows the starting circuit of 7th Embodiment. The timing diagram explaining operation | movement of a starting circuit. The block diagram which shows the pulse generation circuit of 8th Embodiment. The figure explaining the UWB communication apparatus electronic device using the pulse generation circuit of 1st Embodiment-8th Embodiment. Explanatory drawing explaining the pulse used by UWB. The figure of a conventional pulse generation circuit, and an operation timing diagram. The circuit diagram which shows the inside of an inverter delay circuit. The figure explaining the subject of the conventional pulse generation circuit. Explanatory drawing explaining the pulse which is going to generate | occur | produce.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Startup circuit, 102, 103 ... Pulse wave generation subcircuit, 301-309 ... Inverter delay circuit, 310-325, 327, 328 ... MOS transistor

Claims (15)

An activation circuit for generating m (m is an integer of 2 or more) activation signals at predetermined time intervals based on the activation start signal;
M pulse wave generation sub-circuits having the same characteristics for generating a pulse wave of n periods (n is an integer of 1 or more) of the pulse width Pw based on each of the m activation signals;
including,
A pulse generation circuit characterized by that. The pulse generation circuit according to claim 1,
The pulse wave generation sub-circuit generates a plurality of inverter delay circuits each having a delay amount set to the pulse width Pw, and generates a pulse wave based on the output signals of the plurality of inverter delay circuits. Including logic circuit,
A pulse generation circuit characterized by that. The pulse generation circuit according to claim 1 or 2,
The pulse generation circuit includes two pulse wave generation sub-circuits,
Each of the pulse wave generation subcircuits generates the pulse wave based on each of the two activation signals generated by the activation circuit in which the predetermined time interval is set to the pulse width Pw.
A pulse generation circuit characterized by that. The pulse generation circuit according to claim 1 or 2,
The pulse generation circuit includes two pulse wave generation sub-circuits,
Each of the pulse wave generation subcircuits generates the pulse wave based on each of the two activation signals generated by the activation circuit in which the predetermined time interval is set to the pulse width Pw / 2.
A pulse generation circuit characterized by that. The pulse generation circuit according to claim 1 or 2,
The pulse generation circuit includes four pulse wave generation sub-circuits,
Each of the pulse wave generation subcircuits generates the pulse wave based on each of the four activation signals generated by the activation circuit in which the predetermined time interval is set to the pulse width Pw / 2.
A pulse generation circuit characterized by that. The pulse generation circuit according to claim 4 or 5,
The pulse generation circuit further includes an addition / subtraction circuit for adding and subtracting the pulse waves generated by each of the pulse wave generation subcircuits to each other.
A pulse generation circuit characterized by that. In the pulse generation circuit according to any one of claims 1 to 3,
The start circuit includes: a two-phase signal generation circuit that generates a two-phase signal whose rising and falling simultaneously change based on the start-up signal; and the inverter connected to one of the output signals of the two-phase signal generation circuit Including a delay circuit,
A pulse generation circuit characterized by that. The pulse generation circuit according to any one of claims 1, 2, 4, and 6,
The activation circuit includes a first delay circuit whose delay amount is set to the pulse width Pw, and a second delay circuit whose delay amount is set to the pulse width Pw × 1.5.
A pulse generation circuit characterized by that. The pulse generation circuit according to any one of claims 1 to 8,
The pulse generation circuit includes an activation signal selection circuit that switches an output destination of the m activation signals generated by the activation circuit to any one of the m pulse wave generation subcircuits based on data to be transmitted.
A pulse generation circuit characterized by that. The pulse generation circuit according to any one of claims 1 to 8,
The pulse generation circuit includes an output selection circuit that switches an output destination of the pulse wave generated by the m pulse wave generation subcircuits based on data to be transmitted.
A pulse generation circuit characterized by that. The pulse generation circuit according to claim 3 or 7,
The pulse generation circuit includes a cross couple connected between output nodes in which phases of outputs of the inverter delay circuits constituting the pulse wave generation subcircuit are inverted with each other in a predetermined set of the m pulse wave generation subcircuits. Including inverter,
A pulse generation circuit characterized by that. In the pulse generation circuit according to any one of claims 2 to 11,
The pulse width of the start signal input to the start circuit is not less than the pulse width Pw and less than the pulse width Pw × 4 × n.
A pulse generation circuit characterized by that. In the pulse generation circuit according to any one of claims 2 to 11,
The period of the activation start signal input to the activation circuit is an even multiple of the pulse width Pw.
A pulse generation circuit characterized by that. In the pulse generation circuit according to any one of claims 1 to 13,
The inverter delay circuit can control the delay amount of the inverter delay circuit by an external control signal.
A pulse generation circuit characterized by that. Including the pulse generation circuit according to claim 1,
A UWB communication apparatus characterized by the above.

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