JP4049511B2 - Phase synthesis circuit and timing signal generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase synthesis circuit and a timing signal generation circuit, and more particularly to a timing signal generation circuit for performing high-speed signal transmission between a plurality of LSI chips or between a plurality of elements and circuit blocks in one chip.
In recent years, the performance of components constituting computers and other information processing devices has been greatly improved. For example, the performance improvement of semiconductor storage devices such as DRAM (Dynamic Random Access Memory) and processors is remarkable. As the performance of the semiconductor memory device, processor, etc. is improved, the performance of the system cannot be improved unless the signal transmission speed between components or elements is improved. Specifically, for example, a gap in signal transmission speed between a DRAM and a processor (logic circuit) tends to increase. In recent years, this speed gap has been hindering improvement in computer performance. This is a major factor that limits not only the signal transmission between chips (LSI chips) but also the performance of the chip in terms of signal transmission speed between elements and circuit blocks in one chip as the chip becomes larger. It has become. Therefore, it is desired to provide a highly accurate timing signal generation circuit with a small number of input phases (number of phases of input signals).
[0002]
[Prior art]
In order to increase the speed of signal transmission between LSI chips, it is necessary for a circuit that receives a signal to operate at an accurate timing with respect to the signal. As a technique for generating such accurate timing, it is proposed to provide a phase variable timing signal generation circuit using a phase interpolator in a feedback loop such as DLL (Delay Locked Loop) and PLL (Phase Locked Loop). ing.
[0003]
Specifically, in US Pat. No. 5,485,490 (issued on January 16, 1996), for example, a first phase (signal) and a second phase (signal) are selected from 12 different phase clocks, and these are selected. The two selected signals are supplied to a phase interpolator circuit and designated by a control code, thereby generating a signal (clock: timing signal) having a phase between these two signals. That is, the phase interpolator circuit is an amplifier circuit for a weighted sum of two input phases (input signals), and the weight is changed from the first phase (signal) to the second phase (signal) according to the control signal. By shifting, a clock having a phase between two phases is generated.
[0004]
In the PLL of US Pat. No. 5,485,490, the clock generated by the phase interpolator circuit is compared with the reference clock, and is fed back to the control signal so that the phase is equal, so that it is locked to the reference clock. It has become.
[0005]
[Problems to be solved by the invention]
In the conventional timing signal generation circuit, the output accuracy of the PLL (or DLL) is determined by the accuracy of the phase interpolator. Therefore, the accuracy of the timing signal (clock) is defined by the linearity and quantization error of the output phase with respect to the control signal (control code) given as a digital signal, random phase fluctuation (jitter), and the like.
[0006]
The conventional phase interpolator described above increases, for example, the number of phases of the input signal to 12 phases in order to obtain high time resolution. Increasing the number of phases of the input signal is the simplest method for improving linearity because the interval of interpolation can be reduced.
However, when a large number of interpolators are used in multi-channel signal transmission or the like, it is difficult to distribute a multi-phase clock (for example, a 12-phase clock) while maintaining the mutual phase relationship in the chip. In addition, it is difficult to realize a circuit that selects two specific signals (phases) from a large number of input signals having different phases, with a small phase error. Furthermore, supplying a clock (input signal) input to the phase interpolator via a selection circuit or a switching circuit is another factor that degrades the accuracy of the output signal.
[0007]
By the way, the phase interpolator is generally an amplifier circuit for the weighted sum of the phases of the input signal, and the signal (clock) input to this circuit is a complete periodic waveform unless the input phase is switched. It is. However, when the phase (input signal) is switched, a deviation from complete periodicity occurs. When the input signal is switched, even if the weight for the phase of the input signal is zero, there is an influence on the weighted sum of the phase synthesis circuit due to capacitive coupling, etc. There is a problem that the timing error (jitter) becomes large at the boundary where the phase is switched due to the influence. This jitter can be a fatal problem for a timing signal generation circuit for high-speed signal transmission that always requires an accurate timing signal.
[0008]
An object of the present invention is to provide a highly accurate timing signal generation circuit with a simple configuration with a small number of input phases (number of phases of an input signal) in view of the problems of the above-described conventional timing signal generation circuit. Another object of the present invention is to provide a timing signal generation circuit that eliminates the need for a phase selector circuit (input signal selection circuit) that causes phase errors and jitter.
[0009]
[Means for Solving the Problems]
  According to a first aspect of the present invention, there is provided a phase synthesis circuit that synthesizes a periodic timing waveform controlled based on a control signal based on input signals having different phases, the input having the different phases. An input signal processing circuit that selects a plurality of input signals from the signal, generates an intermediate phase signal of the selected plurality of input signals, a weight signal generation circuit that generates a weight according to the control signal, and the intermediate A weighting circuit that gives the weight of positive or negative polarity to a phase signal, and a synthesis circuit that synthesizes each of the weighted intermediate phase signals.The plurality of input signals are two adjacent input signals in the input signals having different phases.A phase synthesizing circuit is provided.
  According to the first aspect of the present invention, there is provided a phase synthesis circuit for synthesizing a periodic timing waveform controlled based on a control signal based on input signals having different phases, wherein the different phase An input signal processing circuit that selects a plurality of input signals from the input signals, generates an intermediate phase signal of the selected input signals, a weight signal generation circuit that generates a weight according to the control signal, A weighting circuit that gives the weight of positive or negative polarity to the intermediate phase signal; and a synthesis circuit that synthesizes each of the weighted intermediate phase signals, and the plurality of input signals are: There is also provided a phase synthesizing circuit characterized by three adjacent input signals in the different phase input signals.
  Furthermore, according to the first aspect of the present invention, there is provided a phase synthesis circuit for synthesizing a periodic timing waveform controlled based on a control signal based on input signals having different phases, wherein the different phase An input signal processing circuit that selects a plurality of input signals from the input signals, generates an intermediate phase signal of the selected input signals, a weight signal generation circuit that generates a weight according to the control signal, A weighting circuit that gives the weight of positive or negative polarity to the intermediate phase signal; and a synthesis circuit that synthesizes each of the weighted intermediate phase signals, and the plurality of input signals are: There is also provided a phase synthesizing circuit characterized by two input signals every predetermined number of the input signals of different phases.
[0010]
  In addition, according to the second aspect of the present invention, control is performed based on a control signal based on a phase signal generation circuit that generates signals having different phases and input signals having different phases from the phase signal generation circuit. A phase synthesis circuit that synthesizes a periodic timing waveform that is generated, and a control signal generation circuit that generates the control signal, wherein the phase synthesis circuit selects a plurality of input signals from the input signals of different phases An input signal processing circuit that generates an intermediate phase signal of the selected plurality of input signals, a weight signal generation circuit that generates a weight corresponding to the control signal, and positive or negative with respect to the intermediate phase signal A weighting circuit that gives the weight of negative polarity, and a combining circuit that combines the weighted signals of the intermediate phase.The plurality of input signals are two adjacent input signals in the input signals having different phases.A timing signal generating circuit is provided.
  Furthermore, according to the second aspect of the present invention, control is performed based on a control signal based on a phase signal generation circuit that generates a signal having a different phase and an input signal having a different phase from the phase signal generation circuit. A phase synthesis circuit that synthesizes a periodic timing waveform that is generated, and a control signal generation circuit that generates the control signal, wherein the phase synthesis circuit selects a plurality of input signals from the input signals of different phases An input signal processing circuit that generates an intermediate phase signal of the selected input signals, a weight signal generation circuit that generates a weight according to the control signal, and a positive or negative signal with respect to the intermediate phase signal. A weighting circuit that gives the weight of negative polarity, and a combining circuit that synthesizes each of the weighted signals of the intermediate phase, and the plurality of input signals are the input signals of the different phases. That the timing signal generating circuit, which is a neighboring three input signals that are also provided.
  Then, according to the second aspect of the present invention, control is performed based on the control signal based on the phase signal generation circuit that generates signals of different phases and the input signals of different phases from the phase signal generation circuit. A phase synthesis circuit that synthesizes a periodic timing waveform that is generated, and a control signal generation circuit that generates the control signal, wherein the phase synthesis circuit selects a plurality of input signals from the input signals of different phases An input signal processing circuit that generates an intermediate phase signal of the selected plurality of input signals, a weight signal generation circuit that generates a weight corresponding to the control signal, and positive or negative with respect to the intermediate phase signal A weighting circuit that gives the weight of negative polarity, and a combining circuit that synthesizes each of the weighted signals of the intermediate phase, and the plurality of input signals are the input signals of the different phases. Timing signal generating circuit, characterized in that that a two input signals of every predetermined number is also provided.
[0014]
1 and 2 are diagrams for explaining the principle of a phase synthesis circuit (weighting circuit) according to the present invention. Here, FIG. 1A shows an example of input signals (input phases: φ1 to φ4) used in the phase synthesis circuit, and FIGS. 1B and 1C show weights (positive) for each input signal. Weights: W1 to W4). In FIG. 2, reference numerals 211 to 214 denote multipliers, and 202 denotes an adder.
[0015]
The phase synthesis circuit of the present invention is applied to, for example, a timing signal generation circuit, and directly supplies three or more input phases (three or more input signals having different phases) to the phase synthesis circuit without going through a selection circuit. Thus, a weighted sum is generated.
That is, the phase synthesis circuit (timing signal generation circuit) of the present invention uses, for example, four input phases φ1, φ2, φ3, and φ4 that are 90 degrees out of phase as shown in FIG. Further, as shown in FIG. 1B and FIG. 2, the multipliers 211 to 214 give weights W1, W2, W3, and W4 to the respective input phases. Further, the adder 202 calculates the sum of the weighted input phases (weighted phases: W1, φ1, W2, φ2, W3, φ3, W4, φ4) and outputs (phase synthesized signal) TS (= W1 · φ1 + W2 · φ2 + W3 · φ3 + W4 · φ4). As a result, it is possible to generate a highly accurate timing signal without introducing a phase jump (jump) or error associated with the switching of the input phase. Since the timing signal generation circuit of the present invention has three or more input phases, the output phase range of 0 to 360 degrees can be covered only by weight control without switching the input phase.
[0016]
The phase synthesis circuit (timing signal generation circuit) of the present invention can be implemented with either a single-ended clock or a differential clock. In the case of differential, a complementary clock is considered as one differential phase, or two differential phases that are 180 degrees out of phase with each other, or a single phase that is 180 degrees out of phase. There is a difference in how to count the number of phases depending on whether it is considered as two phases at the end. Therefore, in this specification, the number of input phases (input signals) is counted by the number of weighting circuits that can be given different weights. Specifically, for example, the three phases differ from each other in the phase synthesis circuit. It means that there are three phases that can be weighted.
[0017]
The effect that an output phase range of 0 to 360 degrees can be obtained by using inputs of three phases or more can also be obtained by making a sum by assigning weights that change in positive and negative ranges to phase inputs of two phases or more. Can do.
FIG. 3 is a diagram for explaining a modification of the principle of the phase synthesis circuit shown in FIG. 1. FIG. 3A shows an example of phases (signals φ1, φ2) used for phase synthesis, and FIG. ) Indicates the weights for each phase (weights with positive and negative signs: W1, W2).
[0018]
As shown in FIG. 3, when the weighting circuit adds a code to the weights W1 and W2, all phases (0 to 360 degrees) are used without using a selection circuit (selector) for selecting a phase outside the phase synthesis circuit. ) Can be covered. Here, in order to reduce the number of input phases, it is desirable to use a circuit in which the phase difference between the input phases is as wide as possible. Therefore, the present invention uses a phase synthesis circuit that is not limited to a conventional phase interpolator.
[0019]
By the way, the conventional phase interpolator obtains an output by interpolating two selected input phases. The interpolator is an amplifying circuit for the weighted sum of the input phases, and the phase of the phase is changed by continuously changing the weight from 100% to the first phase to 100% to the second phase. Interpolation is performed. If the amplifier circuit operates sufficiently fast, the output phase is an interpolation between the two input phases.
[0020]
Since the phase synthesis circuit of the present invention can cover the output phase from 0 to 360 degrees, the fact that the output phase of the phase synthesis circuit does not need to fall between the two input phases can be used as an interpolator. A non-limiting phase synthesis circuit can be used.
FIG. 4 is a diagram for explaining a modification of the principle of the phase synthesis circuit shown in FIG. In FIG. 4, reference numerals 211 to 214 denote multipliers, 202 denotes an adder, and 203 denotes an integration circuit.
[0021]
As shown in FIG. 4, the phase synthesis circuit (timing signal generation circuit) of the present invention is configured as an integration type phase synthesis circuit in which the integration circuit 3 is used as a part that was an amplification circuit in the conventional phase interpolator. Can do. In this integration type phase synthesis circuit, weights W1 to W4 are respectively given to input phases (input signals) φ1 to φ4 by multipliers 211 to 214, and the weighted input phases (W1, φ1, W2, φ2, W3,. φ3, W4 · φ4) are added by the adder 202, and this weighted sum (W1 · φ1 + W2 · φ2 + W3 · φ3 + W4 · φ4) is integrated by the integrating circuit 203 to perform phase synthesis to obtain an output TS. Yes. Actually, a weighted integration sum may be obtained by a multi-input integration circuit capable of giving different weights to individual input phases.
[0022]
The advantage of this principle of phase synthesis is that if the input is a square wave, the corresponding integrated waveform is a triangular wave, so that a linear phase change can be obtained by linear weighting with respect to the input phase. Furthermore, high linearity can be obtained even if the phase difference between the input phases is wide.
As described above, the timing signal generation method of the present invention has an advantage that the entire phase range of 0 to 360 degrees can be obtained from an input with a small number of phases. Therefore, it is not necessary to distribute a large number of clocks (for example, 12 phases) to each circuit (interpolator) while maintaining the mutual phase relationship, and further, a circuit for selecting an input phase is unnecessary, and the selection circuit Can be avoided.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a phase synthesis circuit and a timing signal generation circuit according to the present invention will be described in detail with reference to the drawings.
FIG. 5 is a block diagram showing a first embodiment of the timing signal generating circuit according to the present invention. In FIG. 5, reference numeral 1 is a four-phase clock generation circuit, 2 is a PLL circuit, 3 is a receiver, 4 is a control signal generation circuit, and 5 is a phase synthesis circuit (weighting circuit). Further, reference numeral 11 is a phase detector, 12 is a charge pump, 131 to 135 are delay stages, 141 and 142 are inverters, and 151 and 152 are differential buffers. Here, the first embodiment is a circuit for generating a clock for the signal receiving circuit (receiver 3), for driving the receiver in synchronization with the clock (data clock) transmitted to the receiver 3 together with the data. It is a timing signal generation circuit for generating a clock (timing signal) CK.
[0024]
As shown in FIG. 5, the timing signal generation circuit according to the first embodiment includes a four-phase clock generation circuit 1 that receives a reference clock clk synchronized with a clock supplied from the outside of the chip via a PLL circuit 2, and a control signal. A generation circuit 4 and a phase synthesis circuit 5 are provided.
The output signal (timing signal) CK of the phase synthesis circuit 5 is supplied to, for example, the receiver 3 and receives the transmitted data. Here, the receiver 3 performs phase comparison between an externally supplied data clock and an internal clock (output of the timing signal generation circuit) CK, and sends a signal corresponding to the phase comparison result via the control signal generation circuit 4. Feedback is made to the phase synthesis circuit 5. As described above, the receiver 3 (signal reception circuit) is merely an example, and the timing signal generation circuit of this embodiment is also applicable to other various circuits (for example, driver: signal transmission circuit). can do. In the first embodiment, the output of the PLL circuit 3 (reference clock clk) is a single-phase signal, but may be configured as a differential (complementary) signal.
[0025]
The four-phase clock generation circuit 1 uses a DLL and includes delay stages 131 to 135, a phase detector 11, a charge pump 12, inverters 141 and 142, and differential buffers 151 and 152. In the phase detector 11, the phase difference between the signal / Sa obtained by inverting the output signal Sa of the delay stage 132 by the inverter 141 and the signal / Sb obtained by inverting the output signal Sb of the delay stage 134 by the inverter 142 is 180 degrees (π). That is, a control signal (up signal UP and down signal DOWN) corresponding to the phase difference between the signal / Sa (Sa) and the signal / Sb (Sb) is output to the charge pump 12, and the phase difference is 180. It is for the degree.
[0026]
The charge pump 12 generates a control voltage Vc corresponding to the up signal UP and the down signal DOWN from the phase detector 11 and applies the control voltage Vc to each of the delay stages 131 to 135, and calculates the phase difference between the signal Sa and the signal Sb. Control to be exactly 180 degrees. Thereby, the phase difference between the output signal Sa of the delay stage 132 and the output signal Sc of the delay stage 133 can be accurately set to 90 degrees. Here, the delay stages 131 and 132 are for performing waveform shaping of the reference clock clk, and the delay stage 135 is for applying an appropriate load to the output of the delay stage 134.
[0027]
FIG. 6 is a circuit diagram showing an example of the phase detector 11 in the four-phase clock generation circuit 1 of the timing signal generation circuit shown in FIG.
As shown in FIG. 6, the phase detector 11 includes two latches 111 and 112, and the inverted output / Sa of the delay stage 132 is captured by the latch 111 triggered by the inverted output / Sb of the delay stage 134, Further, the inverted output / Sb of the delay stage 134 is captured by the latch 112 triggered by the inverted output / Sa of the delay stage 132. A down signal DOWN and an up signal UP are generated as outputs of the latches 111 and 112 and supplied to the charge pump 12.
[0028]
FIG. 7 is a circuit diagram showing an example of the charge pump 12 in the four-phase clock generation circuit 1 of the timing signal generation circuit shown in FIG.
As shown in FIG. 7, the charge pump 12 includes p-channel MOS transistors (pMOS transistors) 121 and 122, n-channel MOS transistors (nMOS transistors) 123 to 126, a resistor 127, and a capacitor 128. An up signal UP and a down signal DOWN, which are outputs of the detector 11, are received by a differential pair of transistors 123 and 124, and a control voltage Vc is output. The control voltage Vc is applied to all the delay stages 131 to 135 to control the delay amount of each delay stage.
[0029]
FIG. 8 is a circuit diagram showing an example of the delay stage 130 (131 to 135) in the four-phase clock generation circuit 1 of the timing signal generation circuit shown in FIG.
As shown in FIG. 8, the delay stage 130 includes pMOS transistors pMOS transistors 1301 to 1306, nMOS transistors 1307 to 1311, a differential amplifier 1312, and a load 1313. The control voltage Vc is applied to the negative input of the differential amplifier 1312 and to the gate of the transistor 1302. The positive input of the differential amplifier 1312 is the gate and drain of a transistor 1301 provided in parallel with the transistor 1302. Connected to the common connection node. Here, the reference symbol Vcn is the bias voltage of the transistors 1310 and 1311, V + (V−) is the input signal (output of the previous delay stage (PLL circuit)), and out + (out−) is the output signal (back). Of the delay stage).
[0030]
As described above, signals Sa and Sc having a phase difference of exactly 90 degrees are supplied to differential buffers 151 and 152, respectively, and four-phase clocks φ1 to φ4 having a phase difference of 90 degrees are output from each other. .
FIG. 9 is a circuit diagram showing an example of the differential buffer 150 (151 and 152) in the four-phase clock generation circuit 1 of the timing signal generation circuit shown in FIG.
[0031]
As shown in FIG. 9, the differential buffer 151 (152) includes pMOS transistors 1501 to 1506 and nMOS transistors 1507 to 1512, respectively, and a signal φ1 having a phase difference of 180 degrees from the signal Sa (Sc). , Φ3 (φ2, φ4).
In this way, the four-phase clocks φ1 to φ4 having a phase difference of 90 degrees generated by the four-phase clock generation circuit 1 are supplied to the phase synthesis circuit 5.
[0032]
FIG. 10 is a circuit diagram showing an example of the receiver 3 in the timing signal generation circuit shown in FIG. 5, in which data input (in +, in−) is determined at the rising edge of the clock (internal clock CK). Here, the receiver 3 has a phase comparator similar to that for receiving (determining) data, determines the phase relationship between the internal clock CK and the data clock, and, as will be described later, the control signal generating circuit (4 ) And the phase synthesizing circuit (5) for feedback control of the internal clock CK.
[0033]
As shown in FIG. 10, the receiver 3 includes pMOS transistors 301 to 304, nMOS transistors 305 to 309, and NAND gates 310 and 311. The transmitted data (differential signals in +, in−) is supplied to the differential input (gates of the transistors 307 and 308), driven (determined) by the internal clock (output of the timing signal generation circuit) CK, Data (OUT +, OUT-) is output via the latch circuit (NAND gates 310, 311). When the internal clock CK is at a low level “L”, the transistors 301 and 304 are turned on and the transistor 309 is turned off, so that precharging is performed.
[0034]
FIG. 11 is a circuit diagram showing an example of the phase synthesis circuit 5 in the timing signal generation circuit shown in FIG.
As shown in FIG. 11, the phase synthesis circuit 5 includes differential pair transistors 501, 502, 504, and 505 supplied with clocks (input phases) φ1, φ3, φ2, φ4, φ3, φ1, φ4, and φ2, respectively. , 507, 508, 510, 511, transistors 503, 506, 509, 512 having weights (weight signals) W 1, W 2, W 3, W 4 supplied to the gates, and a weight signal generation circuit for generating weight signals W 1 to W 4 51 and a load device 12 commonly connected to each differential pair transistor.
[0035]
That is, the phase control code from the control signal generation circuit 4 is supplied to the weight signal generation circuit 51, and the weight signal generation circuit 51 generates weight signals W1 to W4 corresponding to the phase control code. These weight signals W1, W2, W3, and W4 are supplied to the gates of the transistors 503, 506, 509, and 512, and a current proportional to the weight signal flows.
[0036]
FIG. 12 is a diagram for explaining how weights are given in the control signal generation circuit shown in FIG. FIG. 12 shows the transistor 503 and the differential pair transistors 501 and 502 that supply the weight W1 to the gate, but the other weights W2, W3, and W4 are given in the same manner.
By the way, the weight W1 (W1 to W4) is given as, for example, an output current of a D / A converter that converts a control code from digital to analog, and this current (weight) W1 is supplied to a diode-connected transistor 503 ′. The same gate voltage as that of the transistor 503 ′ is applied to the transistor 503 to give a weight (current W1 flows). Here, FIG. 12A shows a state in which the transistor 503 ′ is provided in the weight signal generation circuit 51. For example, the weight signal generation circuit 51 and the transistors 503 (506, 509, and 512) that give weights are shown. And the ground voltage (Vss) is different, the transistor 503 ′ may be provided adjacent to the transistor 503 as shown in FIG.
[0037]
FIG. 13 is a circuit diagram showing an example of the load device 52 in the phase synthesis circuit 5 shown in FIG.
As shown in FIG. 13, the load device 52 in the phase synthesis circuit 5 includes capacitors (MOS capacitors) 521 and 522 and pMOS transistors 523 to 526, and a cross-coupled pMOS load (differential impedance becomes high resistance) 523 to 526) is added with an integration capacitor (521, 522). Here, since the cross-coupled pMOS load causes a constant current (I1 + I2) to flow through each of the differential pair transistors, it exhibits a high impedance for the differential signal but a low impedance for the in-phase signal. Therefore, it is possible to prevent the common mode voltage from drifting to a high level or a low level without providing a common mode feedback circuit. Only one load device (integration load device) may be provided for four input differential pairs (differential pair transistors) in terms of an equivalent circuit. Two load devices of the same size may be connected in parallel.
[0038]
FIG. 14 is a block circuit diagram showing an example of the control signal generation circuit 4 in the timing signal generation circuit shown in FIG. In FIG. 14, reference numeral 41 is an up / down signal generating circuit, 42 is an up / down counter, and 430 to 437 are registers. Reference numeral 530 indicates the weight signal generation circuit 51 (D / A converter) in the phase synthesis circuit 5.
[0039]
The timing signal generation circuit of this embodiment generates a receiver driving clock (internal clock CK) synchronized with the data clock transmitted to the receiver 3 together with the data. The data clock is phase-shifted by the internal clock CK and the phase comparator. A comparison is made. The same phase comparator as that used for receiving (determining) data is used, and the phase relationship between the internal clock CK and the data clock (lead / lag: DD) is driven by driving the determination circuit with the internal clock CK. Is determined.
[0040]
The advance / delay DD is sequentially stored in, for example, eight registers 430 to 437, and determination results DD 0 to DD 7 for eight cycle clocks are taken into the up / down signal generation circuit 41. In the up / down signal generation circuit 41, each of the determination results DD0 to DD7 generates an up signal (UP) and a down signal DOWN) from the difference in the number of “1” and “0”.
[0041]
That is, when the difference in the number of advance / delay determinations is 2 or less, the up signal UP and the down signal DOWN are not issued, and when there are many determinations that the internal phase has advanced 3 or more, the phase of the internal clock CK Up signal UP is issued (here, delaying is defined as phase increase). On the contrary, when there are many determinations that the data clock has advanced more than the internal clock CK by 3 or more, the down signal DOWN is issued. Specifically, the up / down signal generation circuit 41 outputs an up signal UP when [number of “1”] − [number of “0”] is 8, 6 or 4, and [0] Number]-[number of “1”] is 8, 6 or 4, the down signal DOWN is output. When the difference between [number of “1”] and [number of “0”] is 2, 0, neither the up signal UP nor the down signal DOWN is output.
[0042]
The up signal UP and the down signal DOWN are supplied to the up / down counter 42 and converted into a control code (for example, 6 bits), and the control code from the up / down counter 42 is used as a weight signal generation circuit of the phase synthesis circuit 5. 51 (D / A converter 530). The D / A converter 530 may be configured as a look-up table such as a ROM, for example, and output weight signals (W1 to W4) corresponding to the supplied control codes.
[0043]
FIG. 15 is a block circuit diagram showing an example of the up / down counter 42 in the control signal generating circuit shown in FIG. In FIG. 15, reference numeral 421 indicates a shift register, and 422 and 423 indicate inverters.
The up / down counter 42 shown in FIG. 15 is configured as a Johnson counter that is shift-controlled by the clock clk ′. For example, among the 16-bit data b1 to b16, half of the 8 bits (b1 to b8) in the initial state. Is set to “1” (high level “H”), and the remaining half 8 bits (b9 to b16) are set to “0” (low level “L”). When the up signal UP from the up / down signal generation circuit 41 is input, the data of the bit b16 is right-shifted so as to be inverted by the inverter 422 and written to the bit b1, and conversely, the down signal DOWN is When input, the bit b1 data is inverted by the inverter 423 and left-shifted so as to be written into the bit b16. Specifically, the example of FIG. 15 shows a case where bits b1 to b5 are “1” and bits b6 to b16 are “0”.
[0044]
FIG. 16 is a circuit diagram showing an example of the clock generation circuit 4210 supplied to the shift register 421 in the up / down counter shown in FIG.
As shown in FIG. 16, the clock clk ′ used in the shift register 421 is controlled by a switch 4211 controlled by an up signal UP, a switch 4212 controlled by a down signal DOWN, and an inverted up signal / UP. Switch 4213, a switch 4214 controlled by the inverted down signal / DOWN, and inverters 4215 and 4216.
[0045]
FIG. 17 is a circuit diagram showing a configuration example of the switch 4211 in the clock generation circuit shown in FIG.
As shown in FIG. 17, the switch 4211 includes a transfer gate including a pMOS transistor 42111, an nMOS transistor 42112, and an inverter 42113, and is turned on when the up signal UP is at a high level “H”. It has become. The other switches 4212 to 4214 have the same configuration.
[0046]
FIG. 18 is a circuit diagram showing an example of the D / A converter in FIG.
As shown in FIG. 18, the D / A converter 530 (51) converts the complementary control codes b1, / b1 to b16, / b16 from analog to digital and outputs four weights (currents) W1 to W4. It is like that. That is, for example, the control codes b1 and / b1 are supplied to the gates of the pMOS transistors 5312 and 5313, and the other control codes b2, / b2 to b16, / b16 are also supplied to the gates of similar transistors and flow through the transistors. The currents are added and output as weights (currents) W1 to W4 via the transistors 5331 to 5334.
[0047]
The bias voltage Vcp is applied to the gate of the transistor 5311 (the same applies to other corresponding transistors), and the bias voltage Vcp ′ is also applied to the gates of the transistors 5321 to 5324. Here, the transistors 5321 to 5324 add a predetermined bias current to the weights W1 to W4 to ensure the operation of the circuit that gives the weights. The transistors 5331 to 5334 that control the currents by the control codes b1, / b1 to b16, / b16 and output the weights W1 to W4 are controlled by further control codes (weight selection control signals) b0 and / b0. It is like that.
[0048]
FIG. 19 is a circuit diagram showing an example of a circuit for generating a weight selection control signal used in the D / A converter shown in FIG.
As shown in FIG. 19, a circuit 5000 for generating a weight selection control signal b0 (/ b0) includes NAND gates 5001 to 5004, inverters 5005 to 5007, and a flip-flop 5008, and has a control code b16. , The up signal UP, the down signal DOWN, and the clock clk, the weight selection control signal b0 is generated.
[0049]
FIG. 20 is a block circuit diagram showing an example of a phase synthesis circuit as a second embodiment of the timing signal generation circuit according to the present invention. In FIG. 20, reference numeral 530 is a D / A converter, 541 to 544 are weight processing circuits, 550 is a pre-driver, and 560 is a mixer and an output buffer.
As shown in FIG. 20, the phase synthesis circuit (5) includes a D / A converter 530, weight processing circuits 541 to 544, a pre-driver 550, a mixer and output buffer 560, and inverters 571 and 572. ing.
[0050]
The D / A converter 530 has a reference current Ir and a plurality of control codes (for example, complementary 18-bit control codes: CD0, / CD0 to CD8, / CD8 and CD10, / CD10 to CD18, / CD18). The four weights (currents) W1 to W4 corresponding to these control codes are output. The reference symbol TES is a test signal used when testing a circuit. Here, the weight processing circuits 541 to 544 receive the weights W1 to W4, the outputs for the pre-driver 550 (W11 to W41) linked to the weights W1 to W4, and the outputs for the mixer and output buffer 560 (W12). To W42).
[0051]
The pre-driver 550 receives different input phases (for example, four-phase input signals having a phase difference of 90 degrees from each other) φ1 to φ4 and pre-driver weight signals W11 to W41, and adjusts the adjusted input phases (different Phase input signal) φW1, / φW1 to φW4, / φW4 are output. Mixer and output buffer 560 receives mixer and output buffer weight signals W12 to W42 and adjusted input phases φW1, / φW1 to φW4, / φW4 from pre-driver 550, and passes inverters 571 and 572. Internal clocks (timing signals) CK and / CK are output.
[0052]
21 is a circuit diagram showing an example of the D / A converter 530 in the phase synthesis circuit shown in FIG.
As shown in FIG. 21, the D / A converter 530 has a pMOS transistor 5300 through which a reference current Ir flows, a pMOS transistor 5301 connected to the transistor 5300 in a current mirror, and a control code (CD0, / CD0) as a gate. The switching pMOS transistors 5302 and 5303 supplied to are provided. Here, the transistors 5301 to 5303 are provided for each complementary control code (CD0, / CD0; CD1, / CD1;... CD8, / CD8 and CD10, / CD10; CD11, / CD11;... CD18, / CD18). Is provided. In FIG. 21, a pMOS transistor 5304 connected to the transistor 5300 in a current mirror is for giving a bias current to the weight (current) W1.
[0053]
In this way, the D / A converter 530 generates weights (currents) W1 to W4 obtained by digital-analog conversion of the control codes CD0, / CD0 to CD8, / CD8 and CD10, / CD10 to CD18, / CD18. .
FIG. 22 is a block circuit diagram showing an example of the pre-driver 550 in the phase synthesis circuit shown in FIG.
[0054]
As shown in FIG. 22, the pre-driver 550 receives the pre-driver weight signal W11 and the phase signals φ1 and φ3, and outputs the adjusted input phases (input signals having different phases) φW1 and φW3. 551, pre-driver unit 552 that receives weight signal W21 and phase signals φ1, φ3 and outputs adjusted input phases / φW1, / φW3, and input that receives weight signal W31 and phase signals φ2, φ4 and adjusted A pre-driver unit 553 that outputs the phases φW2 and φW4, and a pre-driver unit 554 that receives the weight signal W41 and the phase signals φ2 and φ4 and outputs the adjusted input phases / φW2 and / φW4. .
[0055]
FIG. 23 is a circuit diagram showing an example of a pre-driver unit (551) in the pre-driver shown in FIG.
As shown in FIG. 23, the pre-driver unit 551 includes a pMOS transistor 5511 and nMOS transistors 5512 to 5517. The pre-driver weight signal W11 is supplied to the gate of the transistor 5511, and the phase signals φ1 and φ3 are supplied to the gates of the transistors 5514 and 5515 and the gates of the transistors 5516 and 5517. The adjusted input phase φW1 is taken out from the common source of the transistors 5514 and 5517, and the adjusted input phase φW3 is taken out from the common source of the transistors 5515 and 5516. That is, the adjusted input phases φW1 and φW3 are output with their amplitude and DC level adjusted so as to be suitable for a mixer section (561) in a mixer and output buffer described later. The other pre-driver units 552 to 554 have the same configuration as the pre-driver unit 551 except for input and output signals.
[0056]
FIG. 24 is a block circuit diagram showing an example of the mixer and output buffer 560 in the phase synthesis circuit shown in FIG.
As shown in FIG. 24, the mixer and output buffer 560 includes a mixer unit 561, an output buffer unit 562, and inverters 563 and 564. The mixer unit 561 receives the adjusted input phases φW1, / φW1 to φW4, / φW4 from the pre-driver 550, and the weight signals W12 to W42 for the mixer and output buffer from the weight processing circuits 541 to 544, and outputs them. The signals trclk and / trclk are supplied to the output buffer unit 562. Here, the mixer unit 561 performs addition (multiplication) of the weight signals W12 to W42 to the input phases φW1, / φW1 to φW4, / φW4, addition thereof, integration processing, and the like.
[0057]
FIG. 25 is a circuit diagram showing an example of the mixer section 561 in the mixer and output buffer shown in FIG.
As shown in FIG. 25, the mixer unit 561 includes a load device 5610, differential pair transistors 611 and 612 having the adjusted input phases φW1 and φW3 from the pre-driver 550 supplied to the gate, and a weight processing circuit 541. And a transistor 613 whose output buffer weight signal W12 is supplied to the gate. Note that the gate and the drain of the transistor 614 and one end of the MOS capacitor 615 are connected to the gate (weight signal W12) of the transistor 613. Here, the configuration of transistors 611 to 615 for input phases φW1 and φW3 and weight signal W12 includes other input phases / φW3 and / φW1 and weight signal W22, input phases φW2 and φW4 and weight signal W32, and input phase / The same is provided for φW4, / φW2 and the weight signal W42. The load device 5610 has the same configuration as the load device 52 of FIG. 13 described above, and includes MOS capacitors 5611 and 5612 and pMOS transistors 5613 to 5616.
[0058]
FIG. 26 is a circuit diagram showing an example of the output buffer unit 562 in the mixer and output buffer shown in FIG. 24, which is called a supply insensitive buffer circuit in which the delay hardly depends on the power supply voltage. It is.
As shown in FIG. 26, the output buffer unit 562 includes pMOS transistors 5621 to 5628, nMOS transistors 5651 to 5660, and an inverter 5661. The small-amplitude input signal (trclk, / trclk) is amplified to produce a large amplitude (Full CMOS amplitude) output signal. Reference numeral RST is a reset signal, and the reset signal RST is set to a low level “L” when the circuit is reset.
[0059]
FIG. 27 is a circuit diagram showing an example of the weight processing circuit 541 in the phase synthesis circuit shown in FIG.
As shown in FIG. 27, the weight processing circuit 541 includes pMOS transistors 5411 and 5412 and nMOS transistors 5413 and 5414, processes the weight (current) W1 from the D / A converter 530, and performs pre-processing. Weighting signal W11 (voltage) suitable for driver unit 550 (gate input of pMOS transistor 5511 in FIG. 23) and mixer unit 561 of the mixer and output buffer (common connection node of transistors 613, 614 and capacitor 615 in FIG. 25) Is a weight signal W12 (current) suitable for.
[0060]
FIG. 28 is a circuit diagram showing another example of the four-phase clock generation circuit (reference numeral 1 in FIG. 5) in the timing signal generation circuit according to the present invention.
As shown in FIG. 28, the four-phase clock generation circuit 1 for driving the phase synthesis circuit 5 includes a load device composed of integration capacitors 101 and 102 and cross-coupled pMOS loads 103 to 106, a differential pair transistor 107, 108, the nMOS transistor 109 having the bias voltage Vcn applied to the gate, the cross-coupled pMOS loads 161 to 164, the differential pair transistors 165 and 166, the nMOS transistor 167 having the bias voltage Vcn applied to the gate, the clock buffer 171, 172.
[0061]
That is, the four-phase clock generation circuit 1 shown in FIG. 28 has four signals having a phase difference of 90 degrees from the differential reference clock (clk, / clk) supplied from the PLL circuit 2 by the four-quadrant clock generation circuit. (Phase) φ1, φ2, φ3, and φ4 are generated. The four-quadrant clock generation circuit (1) uses a 90-degree phase shifter using an integration circuit as an input phase (0 degrees and its complementary 180 degrees). To generate signals φ2 and φ4 having phases of 90 degrees and 270 degrees. Here, these phases (φ1, φ2, φ3, φ4) are regarded as differential four-phase signals, and an increase in the phase number is defined as a direction in which the delay increases. The four-phase clock can be directly supplied from the PLL circuit.
[0062]
By the way, the above-described phase synthesis circuit (see the phase synthesis circuit 5 shown in FIG. 11 (see the pre-driver unit 551 shown in FIG. 23 and the mixer unit 561 shown in FIG. 25)) has four input phases (φ1 to φ4). Differential pairs or the like (transistors 501 to 503; 611 to 615) and currents (W1 to W4; W11 to W41) for supplying tail currents of the respective phase signals from the D / A converter (51; 530). , W12 to W42).
[0063]
FIG. 29 is a diagram showing an example of a change in weight in the timing signal generation circuit of the present invention, and FIG. 30 is a diagram showing another example of a change in weight in the timing signal generation circuit of the present invention. FIGS. 29A and 30A show the weights W1 and W3, and FIGS. 29B and 30B show the weights W2 and W4.
The weights W1 to W4 (weight signal generation circuit 51: output current of the D / A converter 530) in the phase synthesis circuit 5 change as shown in FIGS. 29 (a) and 29 (b), for example. Here, the vertical axis I indicates the current, the horizontal axis θ indicates the output phase of the phase synthesis circuit, and the output phase when the weight W1 takes the maximum value Wmax is the origin of the phase.
[0064]
As shown in FIGS. 29A and 29B, each of the weights Wn (W1 to W4) takes a maximum value Wmax and a minimum value Wmin, and a non-zero value ( A predetermined bias current is included). That is, as described with reference to FIG. 18, the weights (currents) W1 to W4 generated by the D / A converter 530 include transistors for ensuring the operation of the transistors to which the weights are given. A predetermined (Wmin) bias current according to 5321 to 5324 is included.
[0065]
In the example of FIG. 29, the weights W1 and W3 are triangular waves whose phases are reversed (shifted by 180 degrees), and the weights W2 and W4 are waveforms obtained by delaying the weights W1 and W3 by 90 degrees, respectively. .
As shown in FIGS. 30A and 30B, each of the weights Wn (W1 to W4) can be a triangular wave with the lower half clamped.
[0066]
FIG. 31 is a block circuit diagram showing an example of a phase synthesis circuit as a third embodiment of the timing signal generation circuit according to the present invention, and shows a modification of the phase synthesis circuit shown in FIG. In the third embodiment, the load device 52 is the same as that in FIG. 11, and the differential pairs 5801 to 5804 correspond to the transistors 501, 502 to 510, and 511 in FIG. 11, respectively.
[0067]
As shown in FIG. 31, the phase synthesis circuit 5 of this embodiment is provided with an output buffer composed of pMOS transistors 5811 to 5814 and nMOS transistors 5815 to 5818 with respect to the phase synthesis circuit of FIG. This output buffer is a supply insensitive buffer circuit whose delay is less dependent on the power supply voltage (Vdd), and amplifies a small amplitude signal and outputs it as a large amplitude signal. This corresponds to the output buffer unit 562 of FIG.
[0068]
FIG. 32 is a circuit diagram showing an example of a phase synthesis circuit as a fourth embodiment of the timing signal generating circuit according to the present invention.
As shown in FIG. 32, the phase synthesizing circuit 7100 of the fourth embodiment uses two input phases φ1 and φ2, and includes pMOS transistors 7101 to 7104, nMOS transistors 7105 to 7116, and a comparator (difference). Dynamic amplifier) 7117. Transistors 7105, 7106, 7108, 7109, 7111, 7112, 7114, and 7115 constitute differential pairs, respectively, giving a weight W 1 to the gate of the transistor 7107, giving a weight W 2 to the gate of the transistor 7116, and transistors 7110 and 7113. A fixed weight W0 is given to the gates.
[0069]
That is, the phase synthesis circuit 7100 of the fourth embodiment is not input of four phases (φ1 to φ4: φ1, / φ1 to φ4, / φ4) as in the phase synthesis circuit 5 shown in FIG. Phases (φ1, φ2: φ1, / φ1, φ2, / φ2) are input and weighted with both positive and negative polarities, so that an output covering the entire phase range of 0 to 360 degrees can be obtained. ing. In the phase synthesis circuit 5 shown in FIG. 11, depending on the viewpoint, two phases of φ1 and φ2 are given, and it can be considered that all the phases are covered by adding weights with signs, but the phase synthesis of FIG. In the circuit, since it is possible to apply different weights to the four phases, it is regarded as four phases. That is, in the phase synthesis circuit of the fourth embodiment, since there are only two weights to be controlled, it is interpreted as two phases. Here, the phase signals φ1 and φ2 preferably have a phase difference of 90 degrees, but can be used if they are out of phase.
[0070]
As shown in FIG. 32, in the phase synthesis circuit 7100 of the fourth embodiment, a differential pair (transistors 7108 and 7109; 7111 and 7112) to which a fixed weight W0 is supplied and weights W1 and W1 controlled from the outside. And a differential pair (transistors 7105 and 7106; 7114 and 7115) to which W2 is supplied. Here, since the output lines of the fixed weight differential pair and the variable weight differential pair are reversed, the fixed weight differential pair has a polarity opposite to that of the variable weight differential pair. Will contribute. If the variable weight Wi (W1, W2) is smaller than the fixed weight W0, the effective weight Wi-W0 takes a negative value, and if the variable weight weight Wi is larger than the fixed weight W0, The effective weight takes a positive value. Further, the output (OUT) is given as the output of the comparator 7117.
[0071]
FIG. 33 is a circuit diagram showing an example of a phase synthesis circuit as a fifth embodiment of the timing signal generating circuit according to the present invention.
As shown in FIG. 33, the phase synthesis circuit 7200 of the fifth embodiment uses two input phases φ1 and φ2 as in the fourth embodiment described above, and includes pMOS transistors 7201-7204, nMOS Transistors 7205 to 7207 and 7211 to 7213, polarity switches 7208 and 7209; 7214 and 7215, and a differential amplifier 7210 are included. The transistors 7205, 7206 and 7211, 7112 constitute a differential pair, respectively, and the polarity of the differential pair weighted by the polarity switches 7208, 7209 and 7214, 7215 is inverted.
[0072]
Here, for example, when the control code is 6 bits, the polarity switches 7208, 7209 and 7214, 7215 are controlled by the upper 2 bits, and the weight is controlled by the D / A converter (530) by the other 4 bits. You may do it. In other words, the polarity switch represents a digital value for controlling the weight as a signed binary value, and controls it using the sign bit. Note that the output (OUT) is given as the output of the differential amplifier 7210.
[0073]
The phase synthesis circuit 7200 of the fifth embodiment is different from that using a phase selection circuit as in the conventional example, and the clock signals (input phases φ1, / φ1; φ2, / φ2) input to the differential pair are always Since there is only one type of phase, the operation of the differential pair is not disturbed during phase selection. Further, when the phase synthesizing circuit is used in the clock synchronization circuit, the phase value changes step by step by the UP signal and the DOWN signal. Therefore, whenever the weight polarity changes in the phase synthesizing circuit, the weight value is always changed. Since it is zero, the influence of polarity reversal on the internal operation of the phase synthesis circuit is extremely small.
[0074]
FIG. 34 is a circuit diagram showing an example of a phase synthesis circuit as a sixth embodiment of the timing signal generation circuit according to the present invention, and FIG. 35 is a diagram showing an example of a change in weight in the phase synthesis circuit shown in FIG. is there.
As shown in FIG. 34, the phase synthesis circuit according to the sixth embodiment includes a plurality (four) of phase synthesis units 7301 to 7304 and a selector 7310. The four phase synthesizing units 7301, 7302, 7303, and 7304 have two input phases (φ1, φ2: φ1, / φ1; φ2, / φ2), (φ2, φ3), (φ3) based on the weights W1 and W2, respectively. , Φ4), (φ4, φ1), the outputs of these four phase synthesis units 7301 to 7304 are output via a selector 7310. The weights W1, W2 change as shown in FIG. 35, for example.
[0075]
That is, one output of the phase synthesis units 7301 to 7304 is selected and output according to the range of the control code. Since the phase synthesis units 7301 and 7303 and the phase synthesis units 7302 and 7304 operate with signals having completely opposite phases, the same unit is reused by exchanging the polarity of the output. It is also possible to configure the whole with two phase synthesis units.
[0076]
In the phase synthesis circuit 7300 of the sixth embodiment, the input phase is supplied to each of the phase synthesis units 7301 to 7304 without passing through a changeover switch, a selection circuit, etc. This is a completely periodic signal, and there will be no disturbance of operation associated with phase selection.
FIG. 36 is a circuit diagram showing an example of a pre-driver in the phase synthesis circuit as the seventh embodiment of the timing signal generating circuit according to the present invention. 502, 503) shows an example of a pre-driver that gives signals (input phases φ1, φ3 and weight W1).
[0077]
By the way, in the weighting circuit (phase synthesis circuit), the clock signals (for example, input phases φ1 and φ3) for driving the differential pair for weighting have a constant amplitude regardless of whether the amplitude is small or large. That is, the input phase (φ1, φ3) supplied to the gates of the differential pair transistors has a constant amplitude regardless of the value of the weight (for example, W1), so that the current waveform that appears at the output of the weighting circuit is There is a problem of not scaling in proportion to the weight. Further, when an input larger than an input voltage sufficient to appropriately perform current steering of the differential pair is input, a dead time in which the output current of the differential pair does not change with respect to the input change occurs. During this dead time, the differential pair operates as a switching device away from the linear operating region, so the time variation of the source voltage of the differential pair transistor occurs, and the current waveform input to the phase synthesis circuit is ideal. It is no longer a typical thing. Furthermore, since the dead time varies depending on the weight value, the current waveform used for phase synthesis does not scale with the weight value, and the linearity of the control code versus phase characteristic is also impaired.
[0078]
The pre-driver 7400 of the seventh embodiment processes and supplies signals (input phases φ1, φ3 and weight W1) to be given to the transistors 501, 502, 503 in the phase synthesis circuit shown in FIG. Is for. As shown in FIG. 36, the pre-driver 7400 includes pMOS transistors 7401-7404 and nMOS transistors 7405-7409. Here, the transistors 7401 to 7409 are used, for example, to process signals (input phases φ1, φ3 and weight W1) to be given to the transistors 501, 502, and 503 in the phase synthesis circuit of FIG. Four similar configurations are provided for the differential pair (four weights).
[0079]
In the pre-driver 7400, the input clock signal (input phase φ1, φ3) is first converted into a level conversion circuit (pre-driver) having a tail current pMOS differential pair (transistors 7403, 7404) proportional to the weight (W1). ). The load devices of this level conversion circuit are two diode-connected nMOS transistors 7405 and 7406 and a diode-connected nMOS transistor 7407 connected to the source side of these transistors. The transistor size of the differential pair of the pre-driver nMOS load and the phase synthesis circuit (current conversion circuit: transistors 501 and 502) is such that a voltage slightly larger than that of the differential pair that can just switch the current is generated. Is selected. The differential pair transistors 501 and 502 are supplied with phase signals φW1 and φW3 processed by the weight W1. Further, the weight (current) W1 from the D / A converter (530) is supplied to the transistor 7408, and the weight W12 processed through the transistor 7409 is supplied to the gate of the transistor 503.
[0080]
Thus, according to the pre-driver 7400 of the seventh embodiment, the weighted differential current waveform integrated by the phase synthesis circuit is scaled so as to be more proportional to the weight, and the phase versus control code characteristic Linearity is improved. Even if the power supply voltage Vdd varies, the voltage level input to the differential pair of the phase synthesis circuit and its common mode voltage hardly vary, and a circuit with little timing variation with respect to the power supply voltage Vdd can be obtained. Furthermore, since the input signal is small for a phase having a small weight, the noise due to capacitive coupling is also reduced at a constant ratio, and there is no problem that the capacitive coupling noise appears relatively large with respect to the small weight. This also improves the phase versus control code characteristics.
[0081]
FIG. 37 is a circuit diagram showing an example of a weight signal generation circuit in a phase synthesis circuit as an eighth embodiment of the timing signal generation circuit according to the present invention, in which the phase is designated by a 6-bit digital control signal. Is shown.
As shown in FIG. 37, the weight signal generation circuit 7500 of the eighth embodiment includes 16 constant current sources including pMOS transistors 7501 to 7503 and an inverter 7504, and the lower 4 of the 6-bit control signal. Bits (CB0 to CB3) are converted into 16 control codes (thermometer codes) b1 to b16, and the currents of the respective constant current sources are switched to generate complementary control currents. The upper 2 bits CB4 and CB5 of the control signal control pMOS transistors 7521, 7522 and 7531, 7532 directly and via inverters 7523 and 7533, respectively, and obtain weights (currents) W1 to W4 from complementary control currents. It is supposed to occur. Note that the pMOS transistors 7511 to 7514 are for applying a bias current independent of the control code (for example, corresponding to Wmin in FIGS. 29A and 29B) to the weights W1 to W4.
[0082]
38 is a circuit diagram showing a modification of the differential pair applied to the phase synthesis circuit of the present invention. For example, a modification of the differential pair or the like (transistors 501 to 503) shown in FIG. 11 is shown.
As shown in FIG. 38, in this modification, the weight W1 is supplied to the gate of the transistor 503 via the resistor 7602 as well as flowing to the nMOS transistor 7601 whose gate and drain are connected in common (diode connection). . Here, the gate of the transistor 503 is connected to the low potential power supply Vss through the capacitor 7603. In other words, the gate voltage of the tail current limiting transistor 503 of the differential pair is generated by a diode-connected 7601, and a filter circuit including a resistor 7602 and a capacitor 7603, so that even if the control code changes, the difference occurs. For example, the weight current of the moving pair is not changed instantaneously, but is changed, for example, in the time of about the clock cycle. In other words, the time constants of the resistor 7602 (R) and the capacitor 7603 (Cg) of the filter circuit are set so that the time is about the clock cycle. The same configuration is applied to the differential pairs for the other weights W2 to W4.
[0083]
According to the modification shown in FIG. 38, even when the control signal (control code) changes asynchronously with the clock of the phase synthesis circuit, the change may cause a large phase error in the output of the timing generation circuit. There is also an advantage that the output of the phase synthesis circuit and the control signal can be made asynchronous.
As described above, for example, in order to speed up signal transmission between LSIs, it is necessary that a circuit that receives a signal operates at an accurate timing with respect to the signal. As a method for generating such an accurate timing, there is a method of providing a phase variable timing signal generation circuit using a phase interpolator in a feedback loop such as DLL or PLL as described above.
[0084]
By the way, the phase difference of the differential clock signal can be almost exactly π (180 degrees). For example, two differential clock signals (φ1, φ3; φ2, φ4) When used as a four-phase input signal, the phase difference between each pair of differential clock signals, specifically between the signals φ1 and φ2 and between the signals φ3 and φ4 is π / 2 (90 Degree). That is, there may be a shift in the input signal itself.
[0085]
FIG. 39 is a diagram for explaining a problem when the phase of the input signal used in the phase synthesis circuit is shifted. FIG. 39A shows two sets of differential clock signals (φ1, φ3; φ2, φ4). ) As a four-phase input signal, the phase between the differential clock signals (between the signals φ1, φ3 and the signals φ2, φ4) is shifted from a predetermined value, as shown in FIG. ) Shows the relationship between the phase control code at that time and the actual output phase.
[0086]
For example, in the phase synthesis circuit shown in FIG. 11 described above, two sets of differential clock signals (φ1, φ3; φ2, φ4) are used as the four-phase input signals of the phase synthesis circuit, and a phase interpolator circuit (phase synthesis circuit). ), A clock having a phase corresponding to the weight values (W1 to W4) is generated by integrating and comparing the weighted sum of these inputs. In other words, the phase interpolator generates a clock having an intermediate phase between two phases by shifting the weight from the first phase to the second phase. The output accuracy of such a phase interpolator is limited by the accuracy of the reference phase (phase of the input signals φ1 to φ4) given to the input.
[0087]
Therefore, for example, as shown in FIG. 39A, when the phase difference of the differential signals (φ1, φ3; φ2, φ4) used as the input is shifted from 90 degrees, as shown in FIG. The phase vs. control code characteristic (the phase characteristic of the actually output signal with respect to the control code) deviates from the straight line.
Specifically, when the signal transmission speed is as high as several Gbps, for example, 2.5 Gbps, the error of the reception timing generation circuit (timing signal generation circuit) needs to be an extremely small value of 10 ps to 20 ps (pico second). There is. Therefore, the deviation from the ideal value (90 degrees) of the phase difference of the differential signal used for the reference clock (input signal of the phase synthesis circuit) must be suppressed to a small value of 10 to 20 ps in terms of time.
[0088]
Therefore, the four-phase input signals (two sets of differential signals) used as the reference clock are not only generated so that the phase difference between them is exactly 90 degrees, but also the generated signals are converted to the phase difference. It is necessary to transmit to the phase interpolator while maintaining However, in a multi-channel signal transmission circuit, since the reference clock drives a large number of transmission / reception circuits, there is a delay due to the input capacity of the clock input circuit, and the delay differs for each wiring (each reference clock). For example, it is very difficult to transmit while maintaining a phase difference of 10 to 20 ps in terms of time.
[0089]
Therefore, in the second embodiment of the present invention described below, in order to realize a phase synthesizing circuit with high accuracy, a reference clock having an accurate phase difference regardless of a phase error during generation and transmission of an input clock is used. This is for generating accurate phase interpolation.
FIG. 40 is a diagram for explaining the principle of the timing signal generating circuit according to the second embodiment of the present invention, and FIG. 41 is a block diagram schematically showing the timing signal generating circuit shown in FIG. In FIG. 41, reference numeral 801 indicates an input signal processing circuit, and 802 indicates a phase synthesis circuit (phase interpolator).
[0090]
As shown in FIG. 40, the phases of n signals are f1, f2,..., Fn, and the phase differences between adjacent signals are d1, d2,. Therefore, d1 = f2-f1, d2 = f3-f2, d3 = f4-f3,... Dn = f1-fn + 2π.
As shown in FIG. 41, the second embodiment of the present invention processes n input signals (f1 to fn) by an input signal processing circuit 801 to generate n signals (F1 to Fn), The processed signals (F1 to Fn) are supplied to the phase synthesis circuit 802.
[0091]
That is, in the principle of the second embodiment of the present invention, for example, a set of f1 and f2, f2 and f3,... Therefore, a combination of a phase of (f1 + f2) / 2, (f2 + f3) / 2,... With a constant phase shift is synthesized. Here, if the errors di are independent of each other, since the intermediate phase is an average of the two phases, the error variance is 2^-0.5As a result, the error is reduced by about 30%. Further, according to the principle of the second embodiment of the present invention, for example, when the pairs of f1 to f3, f2 to f4,... Are combined and the respective intermediate phases are similarly formed, (f1 + f2 + f3) / 3, A phase obtained by adding a certain phase shift to the phases 3,... Is synthesized, and the error can be further reduced.
[0092]
In the above, the generation of the intermediate phase is not limited to two adjacent signals (f1, f2, f2, f3,...) Or three signals (f1, f2, f3, f2, f3, f4,...) For example, two signals (f1, f3, f2, f4,...) Every predetermined number or three signals (f1, f3, f5, f2, f4, f6,...), And further limited to two or three. Alternatively, intermediate phases (signals F1, F2,...) Can be combined by combining arbitrary k signals.
[0093]
Here, when there is a specific relationship between the phases of the signals, a more remarkable error reduction effect can be obtained.
FIG. 42 is a diagram for explaining one operating principle of the timing signal generating circuit as the second mode of the present invention, and FIG. 43 is a ninth embodiment of the timing signal generating circuit to which the operating principle shown in FIG. 42 is applied. FIG. 43, reference numeral 801 indicates an input signal processing circuit having four input signal processing units 811 to 814, and 802 indicates a phase synthesis circuit. Here, each of the input signal processing units 811 to 814 can be configured as a two-input equal weight interpolator.
[0094]
As shown in FIGS. 42 and 43, the timing signal generating circuit of the ninth embodiment inputs two sets of differential signals (f1, f3; f2, f4) having a phase difference of about 90 degrees. Use as a signal. These signals f1 to f4 may be considered as four-phase signals, but since they are differential, every other phase is a phase difference of 180 degrees. That is, the signal f1 and the signal f3 are different in phase by 180 degrees, and the signal f2 and the signal f4 are different in phase by 180 degrees. Here, as shown in FIG. 42, when the phase difference between one set of differential signals (input signals) f1 (f3) and the other set of differential signals f2 (f4) is smaller than 90 degrees. think of. The signals f1 to f4 correspond to the signals φ1 to φ4 shown in FIGS. 5 and 9, for example.
[0095]
As shown in FIG. 43, the input signals f1 to f4 are respectively supplied to the input signal processing units 811 to 814 of the input signal processing circuit 801, and are output as reference signals (new input signals) F1 to F4. It is supplied to the synthesis circuit 802.
That is, when the signals f1 and f3 and the signals f2 and f4 are differential signals (complementary signals), the differential signal pairs (f1, f3) and (f2, f4) are synthesized with equal weights to obtain a new differential signal. The pair (F1, F3) is output. Further, a differential signal pair (F2, F4) obtained by synthesizing (f2, f4), (f3, f1) with one weight of the original differential signal pair replaced with equal weight is also output. . That is, F1 to F4 are considered by the input signal processing units 811 to 814, except for a fixed offset phase by phase synthesis.
F1 = (f1 + f2) / 2
F2 = (f2 + f3) / 2
F3 = (f3 + f4) / 2
F4 = (f4 + f1-2π) / 2
To be processed. However, the phase angle is defined so that 0 <f1 <f2 <f3 <f4 <2π.
[0096]
By the way, when the difference between adjacent phases is calculated for Fi, Fi + 1−Fi = (fi + 2−fi) / 2 = 90 degrees. This is because fi and fi + 2 have a phase difference of 180 degrees (π) due to the differential pair. Specifically, F2-F1 = (f2 + f3) / 2- (f1 + f2) / 2 = (f3-f1) / 2 = 90 degrees, and F3-F2 = (f3 + f4) / 2- (f2 + f3) / 2 = (F4-f3) / 2 = 90 degrees.
[0097]
Therefore, even if the phase difference between the differential signals (for example, the phase difference between the signal f1 and the signal f2) is not exactly 90 degrees, the phase difference between the combined signals (for example, the phase difference between the signals F1 and F2). Is 90 degrees, and it can be seen that it is not affected by timing errors due to clock generation or distribution. In the ninth embodiment, signals F1 to F4 having a phase difference of exactly 90 degrees are supplied to the phase synthesis circuit 802 to obtain an output signal with a predetermined phase control.
[0098]
44 is a circuit diagram showing an example of a phase synthesis circuit in the timing signal generation circuit shown in FIG. 43, and corresponds to the phase synthesis circuit 5 in FIG. 11 described above. FIG. 45 is a diagram showing an example of a change in weight in the phase synthesis circuit shown in FIG.
As shown in FIG. 44, the phase synthesis circuit (variable weight interpolator) 802 is supplied with signals (input phases) F1 to F4 processed by the input signal processing units 811 to 814, respectively. The phase synthesis circuit 802 includes differential pair transistors 821, 822, 824, 825, 827, 828, 830, and 831 to which signals F1, F3, F2, F4, F3, F1, F4, and F2 are supplied, and weights ( Weighting signals) W1, W2, W3, W4 are provided with transistors 823, 826, 829, 832 supplied to the gates, a load device 833 commonly connected to each differential pair transistor, and an output buffer 834. Here, the output buffer 834 is for converting the signal level of small amplitude at both ends of the load device 833 into an output signal of large amplitude (Full CMOS amplitude). In the circuit of FIG. 44, the delay depends on the power supply voltage. It is configured as a supply insensitive buffer circuit (see FIG. 31) that is difficult to perform. In FIG. 44, the configuration of the weight signal generation circuit and the like is omitted.
[0099]
The operation of the phase synthesis circuit 802 is the same as, for example, the phase synthesis circuit 5 shown in FIG. 11 described above, and the weight signals W1, W2, W3, and W4 are supplied to the gates of the transistors 823, 826, 829, and 832 respectively. By changing as shown in FIG. 45, for example, a total phase accuracy of 6 bits is obtained. As described above, in this circuit, the input signal has two pairs of differential signals and a small number of signal lines, but the input signal of the variable weight interpolator (phase synthesis circuit) 802 has high relative phase accuracy, and Since the linearity of the variable weight interpolator 802 is excellent, a highly accurate timing signal can be generated.
[0100]
46 is a block circuit diagram schematically showing a tenth embodiment of the timing signal generating circuit to which the operation principle shown in FIG. 42 is applied, and FIG. 47 is an example of a phase synthesis circuit in the timing signal generating circuit shown in FIG. FIG. In FIG. 46, reference numerals 841 to 844 denote weight processing units.
As shown in FIG. 46, the phase synthesizing circuit 802 in the timing signal generating circuit of the tenth embodiment has four weights to which the respective weights (W1 to W4) and all the input phases (signals F1 to F4) are supplied. The processing units 841 to 844 are provided.
[0101]
As shown in FIG. 47, each weight processing unit (841) includes pMOS transistors 8401 to 8404 and nMOS transistors 8405 to 8413 constituting a load. Transistors 8405, 8406 and 8408, 8409 constitute differential pairs, respectively, are weighted (W1) by signals F1 to F4, and are connected to load device 833 via transistors 8411 and 8412. Here, four weight processing units are provided for the four weights W1 to W4 (841 to 844), are connected to the load device 833, respectively, and output a timing signal via the output buffer 834. . In the tenth embodiment shown in FIG. 46 as well, the supply insensitive buffer circuit 834 is used as an output buffer as in the circuit of FIG.
[0102]
As described above, in the tenth embodiment, the output of the fixed weight interpolator (weight processing units 841 to 844) is directly input to the variable weight interpolator 802, so that the conversion to the CMOS full amplitude level is performed by the comparator. Omitted, it is intended to further increase the speed and power consumption.
As described above, the differential signal (differential clock signal) can maintain a phase difference of 180 degrees almost accurately due to the complementary change of the signal and the coupling of wiring for transmitting the differential signal. Therefore, for example, even if the phase is shifted between two sets of differential signals (for example, f1, f2), the signals processed as described above (for example, F1 = (f1 + f2) / 2, F2 = (f2 + f3) / 2), the phase difference can be set to a predetermined value (for example, 90 degrees: 180 degrees / 2). This is the same for not only two sets of differential signals but also three sets of differential signals (f1, f4; f2, f5; f3, f6), for example, and as will be described later, F1 = (f1 + f2 + f3). ) / 3, F2 = (f2 + f3 + f4) / 3, F3 = (f3 + f4 + f5) / 3, the phase difference between the signals F1 and F2, the phase difference between the signals F2 and F3, etc. It can be precisely 60 degrees (180 degrees / 3).
[0103]
FIG. 48 is a diagram for explaining another operation principle of the timing signal generation circuit according to the second embodiment of the present invention, and FIG. 49 is an eleventh embodiment of the timing signal generation circuit to which the operation principle shown in FIG. 48 is applied. It is a block circuit diagram showing an example roughly. 49, reference numeral 901 indicates an input signal processing circuit having six input signal processing units 911 to 916, and 902 indicates a phase synthesis circuit. Here, each of the input signal processing units 911 to 916 can be configured as a three-input equal weight interpolator.
[0104]
As shown in FIG. 48 and FIG. 49, the timing signal generating circuit of the eleventh embodiment has three sets of differential signals (f1, f4; f2, f5; f3, the phase difference of which is around 60 degrees). f6) is used as the input signal. These signals f1 to f6 may be considered as six-phase signals, but since they are differential, every second phase is a phase difference of 180 degrees. That is, the signal f1 and the signal f4 are different in phase by 180 degrees, the signal f2 and the signal f5 are different in phase by 180 degrees, and the signal f3 and the signal f6 are only 180 degrees in phase. Is different.
[0105]
Here, as shown in FIG. 49, three sets of differential signals (f1, f4; f2, f5; f3, f6) are signals synchronized with a clock clk supplied from the outside of the chip by the PLL circuit 903, for example. Are divided into phases using the DLL units 961 to 963, the phase detector 904, and the charge pump 905, and three sets of differential signals whose phases are different by 120 degrees through the buffers 971 to 973. (F1, f4; f2, f5; f3, f6) are supplied to the input signal processing circuit 901.
[0106]
By the way, the input signals (three sets of differential signals f1, f4; f2, f5; f3, f6) are also used for driving various other circuits, for example. Due to delays due to wiring capacitance or the like, the phase difference between them may not be exactly 120 degrees. Note that the phase difference of each differential signal (differential clock signal) can be maintained at 180 degrees almost accurately due to complementary changes in the signal and coupling of wiring for transmitting the differential signal.
[0107]
Therefore, in the eleventh embodiment, as in the case of the two sets of differential signals (f1, f3; f2, f4) described with reference to FIG. F6 is generated, and a timing signal is generated using these signals F1 to F6.
That is, as shown in FIG. 49, F1 to F6 are considered by the input signal processing units 911 to 916, except for a fixed offset phase by phase synthesis.
F1 = (f1 + f2 + f3) / 3
F2 = (f2 + f3 + f4) / 3
F3 = (f3 + f4 + f5) / 3
F4 = (f4 + f5 + f6) / 3
F5 = (f5 + f6 + f1 + 2π) / 3
F6 = (f6 + f1 + f2 + 4π) / 3
Thus, the phase difference between the signals F1 and F2, the phase difference between the signals F2 and F3, and the phase difference between the signals F3 and F4 are each accurately 60 degrees (180 degrees / 3). ). The second embodiment of the present invention is not limited to two sets of differential signals (f1, f3; f2, f4) and three sets of differential signals (f1, f4; f2, f5; f3, f6). Further, the same processing can be performed for a large number of sets of differential signals. Further, as described above, even if there is no specific relationship between the phases of the signals, for example, a pair of f1 and f2, f2 and f3,... = (F1 + f2) / 2, F2 = (f2 + f3) / 2, ...), it is possible to reduce the error of each signal.
[0108]
FIG. 50 is a circuit diagram showing an example of a phase synthesis circuit in the timing signal generation circuit shown in FIG. 49, and FIG. 51 is a diagram showing an example of a change in weight in the phase synthesis circuit shown in FIG.
As shown in FIG. 50, signals (input phases) F1 to F6 processed by the input signal processing units 911 to 916 are supplied to the phase synthesis circuit (variable weight interpolator) 902, respectively. The phase synthesis circuit 902 includes switches 921, 922, and 923 that invert signals F1, F4, F2, F5, F3, and F6, and differential pair transistors 9201, 9202, and 9204 to which outputs of these switches 921 to 923 are supplied. , 9205, 9207, 9208, transistors 9203, 9206, 9209 having weights (weight signals) W 1, W 2, W 3 supplied to their gates, a load device 9210 commonly connected to each differential pair transistor, and an output buffer 9211 And.
[0109]
Here, the weights W1 to W3 (current: see FIG. 12A) are obtained, for example, as outputs of weight signal generation circuits (D / A converters: 51, 530) that generate weights from the phase control code. For example, it is generated by a phase control code comprising a 2-bit polarity control signal and a 4-bit weight control signal. That is, as shown in FIG. 51, for example, the weight W1 is inverted in the range of 90 to 270 degrees, the weight W2 is inverted in the range of 150 to 330 degrees, and the weight W3 is the phase. Is inverted in the range of 210 degrees to 390 (30) degrees. In addition, the signals F1, F4, F2, F5, F3, and F6 are configured to switch the polarities of the differential signals input to the respective differential pairs by the switches 921, 922, and 923.
[0110]
Then, the current of the differential pair (9201, 9202, 9204, 9205, 9207, 9208) whose tail current is controlled by the weights W1 to W3 is integrated by the load device 9210, and the obtained differential signal The output is obtained by detecting the zero cross. Note that the load device 9210 of the phase synthesis circuit 902 is obtained by adding an integration capacitor to a cross-coupled pMOS load having a high differential impedance, for example. As described above, this cross-coupled pMOS load has a high impedance for differential signals but a low impedance for in-phase signals. In particular, the common mode voltage is high without providing a common mode feedback circuit. There is no drift to the level or low level. An output buffer (comparator) 9211 is connected to the load device 9210 to convert a small amplitude signal into a large amplitude (Full CMOS amplitude) output signal. In the circuit of FIG. 50, for the output buffer 9211, for example, a supply insensitive buffer circuit whose delay hardly depends on the power supply voltage is used. As described above, the phase synthesis circuit shown in FIG. 50 can configure a highly accurate timing signal generation circuit with a simple configuration with a small number of input phases.
[0111]
FIG. 52 is a circuit diagram showing another example of the phase synthesis circuit in the timing signal generation circuit shown in FIG. 49, and FIG. 53 is a diagram showing an example of a change in weight in the phase synthesis circuit shown in FIG.
As shown in FIG. 52, the phase synthesis circuit (variable weight interpolator) 902 includes differential pair transistors 9301, 9302, 9304, and 9305 to which signals F1, F4, F2, F5,. ,..., 9316, 9317, transistors 9303, 9306,..., 9318 supplied with weights (weight signals) W1, W2,..., W6, and a load device 9210 commonly connected to each differential pair transistor And an output buffer 9211. That is, the phase synthesis circuit shown in FIG. 52 is provided with the switches 921 to 923 in the phase synthesis circuit of FIG. 50 to control each signal without controlling the polarities of the signals F1, F4, F2, F5, F3, and F6. The differential pair is supplied. Each of the weights W1 to W6 changes as shown in FIG.
[0112]
That is, the phase synthesis circuit shown in FIG. 52 has 6 phase inputs instead of 3 phase inputs. For example, by giving weights W1 to W6 that change as shown in FIG. The polarity inversion of the input signal to the pair is unnecessary. The phase synthesis circuit shown in FIG. 52 has a larger number of input phases than the phase synthesis circuit shown in FIG. 50. However, since the disturbance of the input signal due to the polarity inversion is eliminated, a more accurate timing signal can be generated. It becomes possible.
[0113]
As described above, according to the second aspect of the present invention, it is possible to generate a highly accurate timing signal without being affected by the phase error when generating and delivering the reference signal.
Additional Notes The present invention has the following features.
(Appendix 1) A phase synthesis circuit that synthesizes a periodic timing waveform that is phase-controlled with a control signal based on input signals of three or more different phases,
Weight signal generating means for generating a weight according to the control signal;
And a weighting means for giving the weight of one of the positive and negative polarities to each of the input signals. (Claim 1)
(Appendix 2) A phase synthesis circuit that synthesizes a periodic timing waveform that is phase-controlled with a control signal based on input signals of two or more different phases,
Weight signal generating means for generating a weight according to the control signal;
A phase synthesizing circuit comprising weighting means for giving the weights capable of taking both positive and negative polarities for each input signal. (Claim 2)
(Supplementary note 3) In the phase synthesis circuit according to supplementary note 2, the weighting means includes means for giving a variable weight of one of positive and negative polarity to each input signal, and the weighting means after the weighting. A phase synthesizing circuit comprising means for inverting the polarity. (Claim 3)
(Supplementary Note 4) In the phase synthesis circuit according to Supplementary Note 1 or 2, the phase synthesis circuit further includes an integration unit that integrates the sum of the weighted input signals. .
(Supplementary Note 5) In the phase synthesis circuit according to Supplementary Note 1 or 2, the control signal is supplied as a digital control code, and the weight signal generating means converts the control code from digital to analog and outputs a weight signal. A phase synthesizing circuit generated.
(Supplementary note 6) The phase synthesis circuit according to supplementary note 5, wherein the weight signal is a current signal.
(Additional remark 7) The phase synthetic | combination circuit of Additional remark 1 or 2 WHEREIN: The input signal of the said different phase is supplied to the said weighting means directly, The phase synthetic circuit characterized by the above-mentioned.
(Supplementary Note 8) In the phase synthesis circuit according to Supplementary Note 1 or 2, the weighting unit includes a pre-driver having an output amplitude that increases and decreases with the weight, and a weighted signal generation circuit driven by the pre-driver. A phase synthesis circuit characterized by comprising:
(Supplementary Note 9) In the phase synthesis circuit according to Supplementary Note 1 or 2, when the control signal changes, the time required for the weight generated corresponding to the control signal to change is determined as the input of the phase synthesis circuit. A phase synthesizing circuit characterized by having the same period as the signal cycle.
(Supplementary note 10) In the phase synthesis circuit according to supplementary note 1, the phase synthesis circuit selects one of a plurality of phase synthesis units supplied with two different phase signals and an output of the plurality of phase synthesis units. A phase synthesis circuit comprising a selector.
(Supplementary Note 11) In the phase synthesis circuit according to Supplementary Note 1 or 2, the input signal is a plurality of first input signals obtained by synthesizing the first input signal from a set of first input signals having a plurality of phases. A phase synthesizing circuit configured as a set of second input signals having a phase. (Claim 4)
(Supplementary note 12) In the phase synthesis circuit according to supplementary note 11, the first set of input signals is configured by a set of differential signals, and the second set of input signals is divided into the plurality of phases. A phase synthesizing circuit comprising synthesizing by equal weighting synthesis of the first input signals. (Claim 5)
(Supplementary note 13) In the phase synthesis circuit according to supplementary note 12, the set of the first input signals is subjected to equal weighting synthesis of a plurality of adjacent signals so as to synthesize the second set of input signals. A phase synthesis circuit characterized by the above.
(Supplementary note 14) In the phase synthesizing circuit according to supplementary note 12, the set of the first input signals is two sets of differential signals having a phase difference of about 90 degrees, and the two sets of differential signals Are combined with equal weights to generate the second set of input signals which are two sets of differential signals.
(Supplementary note 15) In the phase synthesizing circuit according to supplementary note 12, the set of the first input signals includes three sets of differential signals having a phase difference of about 60 degrees, and the three sets of differential signals. Are combined with equal weights to generate the second set of input signals which are three sets of differential signals.
(Supplementary Note 16) Phase signal generating means for generating three or more different phase signals;
A phase synthesis circuit for synthesizing a periodic timing waveform whose phase is controlled by a control signal based on the phase signal from the phase signal generating means;
Control signal generating means for generating the control signal,
The phase synthesizing circuit includes weight signal generating means for generating a weight according to the control signal, and weighting means for respectively giving the weight of one of positive and negative polarities to each phase signal. A characteristic timing signal generation circuit. (Claim 6)
(Supplementary Note 17) Phase signal generating means for generating two or more different phase signals;
A phase synthesis circuit for synthesizing a periodic timing waveform whose phase is controlled by a control signal based on the phase signal from the phase signal generating means;
Control signal generating means for generating the control signal,
The phase synthesizing circuit includes weight signal generating means for generating a weight corresponding to the control signal, and weighting means for giving the weight capable of taking both positive and negative polarities for each phase signal. A timing signal generating circuit. (Claim 7)
(Supplementary note 18) In the timing signal generating circuit according to supplementary note 17, the weighting means includes means for giving a variable weight of positive or negative polarity to each phase signal, and the weight after the weighting. And a means for inverting the polarity of the timing signal generating circuit.
(Supplementary note 19) The timing signal generating circuit according to supplementary note 16 or 17, wherein the phase synthesizing circuit further includes integration means for integrating the sum of the weighted input signals. Signal generation circuit.
(Supplementary Note 20) In the timing signal generation circuit according to Supplementary Note 16 or 17, the control signal generation unit generates a control code of a predetermined bit, and the weight signal generation unit receives the control code from the control signal generation unit. A timing signal generation circuit characterized by generating a weight signal by performing digital-analog conversion.
(Supplementary note 21) The timing signal generation circuit according to supplementary note 20, wherein the weight signal is a current signal.
(Supplementary note 22) The timing signal generation circuit according to supplementary note 16 or 17, wherein the different phase signals are directly supplied to the weighting means.
(Supplementary Note 23) In the timing signal generation circuit according to Supplementary Note 16 or 17, the weighting unit includes a pre-driver having an output amplitude that increases or decreases with the weight, and a weighted signal generation circuit driven by the pre-driver. A timing signal generating circuit.
(Supplementary Note 24) In the timing signal generation circuit according to Supplementary Note 16 or 17, when the control signal changes, the time required for the weight generated corresponding to the control signal to change is determined by the phase synthesis circuit. A timing signal generation circuit characterized in that the timing signal generation period is approximately the same as the period of the phase signal.
(Supplementary note 25) In the timing signal generation circuit according to supplementary note 16, the phase synthesis circuit selects one of a plurality of phase synthesis units supplied with two different phase signals and an output of the plurality of phase synthesis units. A timing signal generating circuit.
(Supplementary note 26) The timing signal generating circuit according to supplementary note 16 or 17, wherein the phase signal generating means generates four-phase signals having phases different from each other by 90 degrees.
(Supplementary note 27) The timing signal generation circuit according to supplementary note 26, wherein the phase signal generation means is a four-phase clock generation circuit using a DLL.
(Supplementary Note 28) In the timing signal generation circuit according to Supplementary Note 16 or 17, the timing signal generation circuit generates an internal clock in the semiconductor integrated circuit device, and the control signal generation means is externally supplied from the outside. A timing signal generating circuit for generating a control signal corresponding to a phase shift between a clock and the internal clock.
(Supplementary note 29) In the timing signal generation circuit according to supplementary note 28, the control signal generation means changes the control code only when a phase shift between the external clock and the internal clock is larger than a predetermined value. A timing signal generating circuit.
(Supplementary Note 30) In the timing signal generation circuit according to Supplementary Note 16 or 17, a plurality of the input signals obtained by synthesizing the first input signal from a set of first input signals having a plurality of phases. A timing signal generating circuit comprising: a pair of second input signals having the following phases: (Claim 8)
(Supplementary note 31) In the timing signal generation circuit according to supplementary note 30, the first set of input signals is constituted by a set of differential signals, and the second set of input signals is composed of the plurality of phases. A timing signal generation circuit comprising: combining a first input signal having equal weighting synthesis; (Claim 9)
(Supplementary Note 32) In the timing signal generation circuit according to Supplementary Note 31, the first input signal set is subjected to equal weighting synthesis of a plurality of adjacent signals to synthesize the second input signal set. A timing signal generation circuit characterized by that.
(Supplementary note 33) In the timing signal generation circuit according to supplementary note 31, the first input signal set is two sets of differential signals having a phase difference of about 90 degrees, and the two sets of differential signals A timing signal generating circuit characterized in that two sets of second input signals, which are two sets of differential signals, are generated by combining signals with equal weights.
(Additional remark 34) In the timing signal generating circuit according to additional remark 31, the first input signal set is three sets of differential signals having a phase difference of about 60 degrees, and the three sets of differential signals. A timing signal generating circuit characterized in that a set of the second input signals, which are three sets of differential signals, is generated by combining signals with equal weights.
[0114]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a highly accurate timing signal generation circuit with a simple configuration with a small number of input phases. Furthermore, according to the present invention, a phase selector circuit that is a cause of phase error and jitter can be eliminated.
[Brief description of the drawings]
FIG. 1 is a diagram (part 1) for explaining the principle of a phase synthesis circuit according to the present invention;
FIG. 2 is a diagram (part 2) for explaining the principle of the phase synthesis circuit according to the present invention;
FIG. 3 is a diagram for explaining a modification of FIG. 1;
4 is a diagram for explaining a modification of FIG. 2; FIG.
FIG. 5 is a block diagram showing a first embodiment of a timing signal generating circuit according to the present invention.
6 is a circuit diagram showing an example of a phase detector in the four-phase clock generation circuit of the timing signal generation circuit shown in FIG. 5. FIG.
7 is a circuit diagram showing an example of a charge pump in the four-phase clock generation circuit of the timing signal generation circuit shown in FIG. 5. FIG.
8 is a circuit diagram showing an example of a delay stage in the four-phase clock generation circuit of the timing signal generation circuit shown in FIG. 5. FIG.
9 is a circuit diagram showing an example of a differential buffer in the four-phase clock generation circuit of the timing signal generation circuit shown in FIG. 5;
10 is a circuit diagram showing an example of a receiver in the timing signal generation circuit shown in FIG. 5;
11 is a circuit diagram showing an example of a phase synthesis circuit in the timing signal generation circuit shown in FIG. 5. FIG.
12 is a diagram for explaining how to give weights in the control signal generation circuit shown in FIG. 11; FIG.
13 is a circuit diagram showing an example of a load device in the phase synthesis circuit shown in FIG. 11. FIG.
14 is a block circuit diagram showing an example of a control signal generation circuit in the timing signal generation circuit shown in FIG. 5. FIG.
15 is a block circuit diagram showing an example of an up / down counter in the control signal generating circuit shown in FIG. 14;
16 is a circuit diagram showing an example of a clock generation circuit supplied to a shift register in the up / down counter shown in FIG. 15;
17 is a circuit diagram showing a configuration example of a switch in the clock generation circuit shown in FIG. 16;
18 is a circuit diagram showing an example of the D / A converter in FIG. 14. FIG.
19 is a circuit diagram showing an example of a circuit that generates a weight selection control signal used in the D / A converter shown in FIG. 18;
FIG. 20 is a block circuit diagram showing an example of a phase synthesis circuit as a second embodiment of the timing signal generation circuit according to the present invention;
21 is a circuit diagram showing an example of a D / A converter in the phase synthesis circuit shown in FIG. 20;
22 is a block circuit diagram showing an example of a pre-driver in the phase synthesis circuit shown in FIG.
23 is a circuit diagram showing an example of a pre-driver unit in the pre-driver shown in FIG.
24 is a block circuit diagram showing an example of a mixer and an output buffer in the phase synthesis circuit shown in FIG.
25 is a circuit diagram showing an example of a mixer section in the mixer and output buffer shown in FIG. 24. FIG.
26 is a circuit diagram showing an example of an output buffer unit in the mixer and the output buffer shown in FIG. 24. FIG.
27 is a circuit diagram showing an example of a weight processing circuit in the phase synthesis circuit shown in FIG. 20;
FIG. 28 is a circuit diagram showing another example of a four-phase clock generation circuit in the timing signal generation circuit according to the present invention.
FIG. 29 is a diagram showing an example of a change in weight in the timing signal generation circuit of the present invention.
FIG. 30 is a diagram showing another example of a change in weight in the timing signal generation circuit of the present invention.
FIG. 31 is a block circuit diagram showing an example of a phase synthesis circuit as a third embodiment of the timing signal generating circuit according to the present invention;
FIG. 32 is a circuit diagram showing an example of a phase synthesis circuit as a fourth embodiment of the timing signal generating circuit according to the present invention;
FIG. 33 is a circuit diagram showing an example of a phase synthesis circuit as a fifth embodiment of the timing signal generating circuit according to the present invention;
FIG. 34 is a circuit diagram showing an example of a phase synthesis circuit as a sixth embodiment of the timing signal generating circuit according to the present invention;
35 is a diagram illustrating an example of a change in weight in the phase synthesis circuit illustrated in FIG. 34;
FIG. 36 is a circuit diagram showing an example of a pre-driver in the phase synthesis circuit as the seventh embodiment of the timing signal generating circuit according to the present invention;
FIG. 37 is a circuit diagram showing an example of a weight signal generation circuit in the phase synthesis circuit as the eighth embodiment of the timing signal generation circuit according to the present invention;
FIG. 38 is a circuit diagram showing a modification of the differential pair applied to the phase synthesis circuit of the present invention.
FIG. 39 is a diagram for explaining a problem when the phase of the input signal used in the phase synthesis circuit is shifted.
FIG. 40 is a diagram for explaining the principle of the timing signal generation circuit according to the second embodiment of the present invention;
41 is a block diagram schematically showing a timing signal generation circuit shown in FIG. 40. FIG.
FIG. 42 is a diagram for explaining an operation principle of a timing signal generation circuit according to a second embodiment of the present invention;
43 is a block circuit diagram schematically showing a ninth embodiment of a timing signal generating circuit to which the operating principle shown in FIG. 42 is applied. FIG.
44 is a circuit diagram showing an example of a phase synthesis circuit in the timing signal generation circuit shown in FIG. 43. FIG.
45 is a diagram showing an example of a change in weight in the phase synthesis circuit shown in FIG. 44;
FIG. 46 is a block circuit diagram schematically showing a tenth embodiment of a timing signal generating circuit to which the operation principle shown in FIG. 42 is applied.
47 is a circuit diagram showing an example of a phase synthesis circuit in the timing signal generation circuit shown in FIG. 46. FIG.
FIG. 48 is a diagram for explaining another operation principle of the timing signal generation circuit according to the second embodiment of the present invention;
FIG. 49 is a block circuit diagram schematically showing an eleventh embodiment of the timing signal generating circuit to which the operation principle shown in FIG. 48 is applied.
50 is a circuit diagram showing an example of a phase synthesis circuit in the timing signal generation circuit shown in FIG. 49. FIG.
51 is a diagram showing an example of a change in weight in the phase synthesis circuit shown in FIG. 50. FIG.
52 is a circuit diagram showing another example of the phase synthesis circuit in the timing signal generation circuit shown in FIG. 49. FIG.
53 is a diagram showing an example of a change in weight in the phase synthesis circuit shown in FIG. 52;
[Explanation of symbols]
1 ... 4 phase clock generator
2 ... PLL circuit
3 ... Receiver
4. Control signal generation circuit
5, 7100, 7200, 7300, 802, 902... Phase synthesis circuit
11 ... Phase detector
12 ... Charge pump
41. Up / down signal generation circuit
42 ... Up / down counter (Johnson counter)
51,7500... Weight signal generation circuit
52 ... Load device
130; 131-135 ... delay stages
150; 151, 152 ... differential buffer
530 ... D / A converter
541-544 ... Weight processing circuit
550, 7400 ... Pre-driver
551-554 ... Pre-driver unit
560 ... Mixer and output buffer
561: Mixer section
562... Output buffer section
W1-W4, W1-W6 ... Weight
φ1 to φ4, f1 to f4, f1 to f6 ... Input phase (input signal, phase signal)
F1 to F4, F1 to F6 ... processed signals

Claims (8)

A phase synthesis circuit that synthesizes a periodic timing waveform controlled based on a control signal based on input signals of different phases,
An input signal processing circuit that selects a plurality of input signals from the input signals of different phases and generates a signal of an intermediate phase of the selected input signals;
A weight signal generation circuit for generating a weight according to the control signal;
A weighting circuit that gives the weight of positive or negative polarity to the intermediate phase signal;
A combination circuit for combining each of the weighted signals of the intermediate phase , wherein the plurality of input signals are two adjacent input signals in the input signals of different phases . A phase synthesis circuit that synthesizes a periodic timing waveform controlled based on a control signal based on input signals of different phases,
An input signal processing circuit that selects a plurality of input signals from the input signals of different phases and generates a signal of an intermediate phase of the selected plurality of input signals;
A weight signal generation circuit for generating a weight according to the control signal;
A weighting circuit that gives the weight of positive or negative polarity to the intermediate phase signal;
A synthesis circuit for synthesizing each of the weighted intermediate phase signals, wherein the plurality of input signals are adjacent three input signals in the different phase input signals. circuit. A phase synthesis circuit that synthesizes a periodic timing waveform controlled based on a control signal based on input signals of different phases,
An input signal processing circuit that selects a plurality of input signals from the input signals of different phases and generates a signal of an intermediate phase of the selected plurality of input signals;
A weight signal generation circuit for generating a weight according to the control signal;
A weighting circuit that gives the weight of positive or negative polarity to the intermediate phase signal;
And a weighting circuit for synthesizing each of the weighted intermediate phase signals, wherein the plurality of input signals are two input signals every predetermined number of the input signals having different phases. Phase synthesis circuit. 4. The phase synthesis circuit according to claim 1, wherein the number of intermediate phase signals is equal to or less than the number of input signals having different phases . 5. A phase signal generation circuit for generating signals of different phases;
A phase synthesis circuit that synthesizes a periodic timing waveform controlled based on a control signal based on input signals having different phases from the phase signal generation circuit;
A control signal generation circuit for generating the control signal,
The phase synthesis circuit selects a plurality of input signals from the input signals having different phases, generates an intermediate phase signal of the selected plurality of input signals, and a weight corresponding to the control signal A weighting signal generating circuit for generating the intermediate phase signal, a weighting circuit for giving the weight of positive or negative polarity to the intermediate phase signal, and a synthesis circuit for synthesizing each of the weighted intermediate phase signals. The timing signal generation circuit , wherein the plurality of input signals are two adjacent input signals in the input signals having different phases . A phase signal generation circuit for generating signals of different phases;
A phase synthesis circuit that synthesizes a periodic timing waveform controlled based on a control signal based on input signals of different phases from the phase signal generation circuit;
A control signal generation circuit for generating the control signal,
The phase synthesis circuit selects a plurality of input signals from the input signals of different phases, generates an intermediate phase signal of the selected plurality of input signals, and a weight corresponding to the control signal A weighting signal generating circuit for generating the intermediate phase signal, a weighting circuit for giving the weight of positive or negative polarity to the intermediate phase signal, and a synthesis circuit for synthesizing each of the weighted intermediate phase signals. The timing signal generating circuit , wherein the plurality of input signals are three adjacent input signals in the input signals having different phases. A phase signal generation circuit for generating signals of different phases;
A phase synthesis circuit that synthesizes a periodic timing waveform controlled based on a control signal based on input signals of different phases from the phase signal generation circuit;
A control signal generation circuit for generating the control signal,
The phase synthesis circuit selects a plurality of input signals from the input signals of different phases, generates an intermediate phase signal of the selected plurality of input signals, and a weight corresponding to the control signal A weighting signal generating circuit for generating the intermediate phase signal, a weighting circuit for giving the weight of positive or negative polarity to the intermediate phase signal, and a synthesis circuit for synthesizing each of the weighted intermediate phase signals. The timing signal generation circuit , wherein the plurality of input signals are two input signals every predetermined number of the input signals having different phases. 8. The timing signal generating circuit according to claim 5 , wherein the number of intermediate phase signals is equal to or less than the number of input signals having different phases .

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