JP2002132377A - Clock signal distributor circuit and distribution signal method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize clock skew even in the arrangement of a long wiring path with a relatively simple circuit configuration. SOLUTION: This circuit is provided with a driving circuit 1 composed of a differential amplifier for generating differential output signals having mutually complementary relations on the basis of a sine wave signal of a single frequency supplied from the outside, and a clock skew reducing means consisting of a signal distributing means having the signal transmission paths of an outward path 2a and a homeward path 3a where the complimentary differential output signals are distributed in a semiconductor integrated circuit with their supplying directions opposite to each other, and voltage comparators 4 to 7 for making the complementary differential output signals at optional observation points O, a, b and c of the signal transmission paths of the paths 2a and 3a to be inputs and converting the complementary differential output signals into a clock signal of a binary level of a logical level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock signal distribution circuit and a distribution method, and more particularly to a clock signal distribution circuit and a distribution method capable of minimizing clock skew with a relatively small-scale circuit.

[0002]

2. Description of the Related Art In recent years, with the advance of the miniaturization technology of semiconductor devices, the scale of LSIs such as memories, microcomputers, gate arrays, etc. constituted by the semiconductor devices has been increasing. For example, in a memory, a dynamic random access memory (DRAM) or a synchronous memory is used as a semiconductor memory having a capacity of 256 megabits per chip.
Random access memories (SDRAMs) have also been put to practical use.

As the scale of LSIs such as the above-mentioned memories, microcomputers, gate arrays, and the like increases in scale and the operating frequency increases, the phase shift between clocks developed on the LSI becomes remarkable, resulting in circuit operation problems. It has become.

As a conventional clock signal distribution method of this kind applied to these LSIs, there is a method using a method called a clock tree. In this clock tree method, for example, a clock driving buffer, a plurality of buffers, a plurality of registers, and the like are arranged on the same hierarchy,
The register group and the buffer group are respectively arranged such that the wiring of the clock signal is arranged in a tree shape in order to equalize the wiring load and the gate load of the buffer.

In each of the register groups, the wiring length from the buffer group is adjusted so that the wiring length from the clock driving buffer becomes equal, and a dummy buffer is added to balance the load in the tree structure.

Since the clock driving buffer and the register are wired at random, a skew occurs due to a difference in clock wiring length. Eliminating this skew is an important issue for speeding up chips, and various reduction methods have been tried. One example is described in JP-A-11-85310.

Referring to FIG. 5 showing the configuration of the clock signal distribution circuit described in the publication, a global clock generation circuit 100 for generating a global clock signal based on a reference clock signal input from the outside, and a global clock signal A global clock distribution circuit 200 distributed in a large-scale integrated circuit and arranged in a double loop so as to be in opposite directions to each other;
0, a local clock generation circuit 400 to 404 for generating a local clock signal based on the intermediate phase of each of the two global clock signals distributed by the global clock distribution circuit 200, and , And clock buffer pairs 31 to 41 inserted into the global clock wiring 300.

[0008] Local clock generation circuits 400 to 404
Although not shown here, the delay amount of the global clock signal is made variable according to the external signal and the first and second variable delay circuits having the same configuration, and the clock signal delayed by these variable delay circuits are A phase comparison circuit that compares the phase of the clock signal with the global clock signal transmitted in the opposite direction, and a control circuit that variably controls a delay amount in the variable delay circuit based on the comparison result, The global clock distribution means is configured to generate a local clock signal having an intermediate phase between the phases of the two global clock signals distributed in opposite directions by control.

On the other hand, although not shown here, the phase comparison circuit divides the clock signal delayed by the variable delay circuit and the global clock signal transmitted from the opposite direction from the clock signal into first and second clock signals. In the case where the phase difference between the clock signal delayed by the variable delay circuit and the global clock signal transmitted in the opposite direction to the clock signal is larger than one half of the input cycle time, However, it is said that it can operate freely.

Referring to FIG. 6 showing the configuration of an LSI to which the above-mentioned global clock distribution circuit 2 is applied, the LS
The I600 includes circuit blocks 411 to 418. The circuit blocks 411 to 418 have clock frequencies f1 to f5 and power supply voltages V1 to V5, respectively. The global clock distribution circuit 200 is arranged so as to go around each of the circuit blocks 411 to 418.

Each of the circuit blocks 411 to 418 generates a local clock of the global clock distribution circuit 200.
Distribution circuits 511 to 518 are provided, and an appropriate clock frequency and power supply voltage are selected in each of the circuit blocks 411 to 418 by the local clock generation / distribution circuits 511 to 518.

The local clock generation / distribution circuit 5
11 to 518 are local clock generation / distribution circuits 519
Can be replaced.

[0013]

As described above, in the conventional clock signal distribution circuit, when the global clock distribution circuit 2 is applied to an LSI, the clock signal distribution circuit is locally localized, that is, a local clock generation is performed to minimize clock skew. The circuit includes a variable delay circuit, a phase comparison circuit, and a control circuit for the variable delay circuit. The local clock distribution circuit includes a phase locked loop circuit such as a delay locked loop circuit or an oscillator. The phase comparison circuit includes a frequency divider circuit. Is included, the number of blocks is increased in terms of circuit and layout configuration, and as a result, the number of wiring paths is increased.

That is, circuits such as phase locked loop circuits are required as many as the number of circuit blocks provided on the LSI.

An object of the present invention is to provide a clock signal distribution circuit and a distribution method which have a relatively simple circuit configuration and minimize clock skew even in a long wiring path. To provide.

[0016]

A feature of the clock signal distribution circuit of the present invention is that a pair of differential output signals having a complementary relationship to each other are generated based on a single frequency sine wave signal supplied from the outside. Signal driving means, and two open loop-shaped wiring paths which circulate in opposite directions and return to the vicinity of the base point with the complementary output ends of the signal driving means as base points, are arranged close to and parallel to each other. A signal having a signal transmission line pair having the wiring path as an outward path and the other wiring path as a return path, and distributing the pair of differential output signals respectively corresponding to the pair of differential output signals into a semiconductor integrated circuit via the signal transmission line pair. A main clock skew comprising distribution means and voltage comparison means for converting the complementary differential output signal transmitted to an arbitrary observation point of the signal transmission line pair into a binary logical clock signal; There to be provided with a reduction means.

Another feature of the clock signal distribution circuit according to the present invention is that the clock signal distribution circuit is disposed at a plurality of points of an open loop signal transmission line pair formed in the semiconductor integrated circuit and includes forward and backward paths, and the signal transmission is performed. In a clock signal distribution circuit including a voltage comparison unit that compares a voltage level of a propagation signal supplied from a predetermined signal driving unit to a line pair and generates a result of the comparison as an internal clock signal, the signal driving unit is a differential signal. A pair of sine wave signals having a complementary relationship with each other based on a single frequency sine wave signal supplied from the outside, and sending the generated signal to the signal transmission line pair from a complementary signal output terminal. The voltage comparison means is to compare the voltage levels of the complementary sine wave signals and convert and output the binary clock signal of a logical level.

Further, the signal driving means can supply the complementary pair of the sine wave signals output differentially to the corresponding signal transmission lines of the signal transmission line pair via respective capacitive elements.

Further, as a means for removing conversion level fluctuation of the voltage comparison means caused by a bias voltage generated in the signal transmission line pair by the complementary pair of sine wave signals, a pair of complementary output terminals of the signal drive means and Capacitors are respectively inserted in series connection between the corresponding signal transmission lines of each of the signal transmission line pairs.

Further, the starting end of the signal transmission line pair is
The signal driving means may be connected to the complementary signal output terminals.

The outgoing path is a signal transmission path extending from one of a pair of complementary signal output terminals of the signal driving means as a starting point, around the periphery of the semiconductor integrated circuit, and extending near the starting end. The return path starts at the other of the pair of complementary signal output terminals of the signal drive means, and goes around the periphery of the semiconductor integrated circuit from the vicinity of the end of the forward path in a state close to and parallel to the forward path. A wiring structure is provided as a signal transmission path extending to near the start end of the return path.

Further, a pair of complementary signal output terminals of the signal driving means are provided as phase equalizing means for equalizing the phases of the clock signals converted into binary logical levels by the voltage comparing means at the plurality of observation points. Has a wiring structure in which the signal transmission paths of the forward path and the return path connected to the same path are arranged with equal length wiring.

Still further, in addition to the main clock skew reducing means for inputting the sine wave signal from the outside and providing the signal transmission line pair along a peripheral portion in the semiconductor integrated circuit, Along with inputting the sine wave signal from the forward path and the return path having means, the signal transmission line pair of the own means extends a sub-clock skew reduction means surrounding an arbitrary range inside the block area, At least one set may be further provided in an arbitrary block area inside the signal transmission line pair included in the main clock skew reduction unit.

The logic level clock signal provided from the voltage comparing means of the at least one set of sub clock skew reducing means is distributed to internal circuits by tree-structured delay adjusting buffer means.

According to the clock signal distribution method of the present invention, a propagation signal transmitted in opposite directions on a pair of open loop signal transmission lines formed on a peripheral portion in a semiconductor integrated circuit and formed of a forward path and a return path is provided. A pair of sinusoidal signals complementary to each other and having a predetermined single fundamental frequency are respectively supplied from corresponding complementary signal output terminals of the signal driving means, and a voltage of the transmitted complementary sinusoidal signal is supplied. Voltage comparison means for comparing levels and converting and outputting a binary clock signal of a logical level is arranged near an arbitrary position of the signal transmission line pair through which the complementary sine wave signal is transmitted. I do.

Further, the complementary sine wave signals provided as differential outputs from the output terminals of the signal driving means can be supplied to the corresponding signal transmission lines of the signal transmission line pair via respective capacitive elements. .

Further, the forward path extends around the periphery in the semiconductor integrated circuit with one of the pair of complementary signal output terminals of the signal driving means as a starting point, and extends along the signal transmission path so as to terminate near the starting point. And the return path starts at the other of the pair of complementary signal output terminals of the signal driving means, and from the vicinity of the end point of the forward path around the peripheral portion in the semiconductor integrated circuit close to and parallel to the forward path. The signal transmission path may be extended to the vicinity of the start end of the return path.

Furthermore, the signal transmission paths of each of the open loop-shaped signal transmission line pairs connected to the pair of complementary signal output terminals of the signal driving means may be arranged with equal length wiring.

Further, in addition to the main clock skew reducing means for inputting the sine wave signal from outside and extending the signal transmission line pair along a peripheral portion in the semiconductor integrated circuit, At least one set of sub-clock skew reduction means for inputting the sine wave signal from the forward path and the return path of the reduction means is arranged in an arbitrary block area inside the signal transmission line pair of the main clock skew reduction means. The signal transmission line pair of the auxiliary clock skew reducing means may extend so as to surround an arbitrary range inside the block area.

Further, the main clock skew reducing means, at least one set of the sub clock skew reducing means, and a tree structure for inputting a clock signal of a logic level output from the voltage comparing means included in the sub clock skew reducing means are provided. The clock signal of the logical level can be distributed to an internal circuit by using a delay adjusting buffer means.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of the present invention will be described.
As shown in FIG. 1 as a main part of the configuration of the present invention, a driving circuit 1 for supplying a sine wave signal and a signal transmitted by a signal transmission line pair including a forward path 2a and a return path 3a for transmitting signals in mutually opposite directions. Each observation point a, b,
Voltage comparators 4, 5, 6, 7 for extracting sine wave signals from the forward path 2a and the return path 3a propagated to c and d.
Is arranged.

The phase difference between the clock signals output from the voltage comparators 4, 5, 6, 7 at the observation points a, b, c, d is constant. Therefore, the outbound path 2a and the return path 3
The effect is obtained that the clock skew between the observation points when the wiring a is long can be minimized by a relatively small-scale circuit. In addition, since a sine wave is used as the basic clock, there is also an effect that the influence of frequency characteristic deterioration can be reduced with respect to a rectangular wave having an nth-order (n is a natural number) harmonic.

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a clock signal distribution circuit according to the present invention includes a driving circuit 1 for distributing a sine wave signal, a signal transmission path for transmitting an output signal of the driving circuit 1, and a sine wave from the signal transmission path. Voltage comparators 4 to 7 that generate pulse signals of logic level are provided.

The drive circuit 1 is composed of a differential amplifier, is arranged at an arbitrary position on the periphery of the semiconductor integrated circuit, for example, at the observation point O, and inputs a sine wave signal having a single frequency from the outside, and And a non-inverted signal having the same polarity and a non-inverted signal having its polarity inverted are individually output. That is, one of the two complementary signal output terminals of the drive circuit 1 outputs a non-inverted signal among differential sine wave signals having a complementary relationship to each other, and the other complementary signal output terminal outputs a non-inverted signal. Is output.

For the sake of convenience, it is assumed that the above-mentioned differential sine wave signal is biased to a half of the power supply voltage value. These non-inverted signals and non-inverted signals are sine wave signals that are the basis of a basic clock signal used in the semiconductor integrated circuit.

The signal transmission path is a signal transmission line pair composed of a forward path 2a and a return path 3a. The forward path 2a is a wiring for a non-inverted signal output from one of the complementary signal output terminals of the drive circuit 1, and exits from the drive circuit 1 and extends along a peripheral portion in the semiconductor integrated circuit, for example, in a clockwise open loop shape. Loop drive circuit 1
Is extended to return to the vicinity of.

The return path 3a is a wiring for a non-inverted signal output from the other complementary signal output terminal of the drive circuit 1, and is arranged along the periphery of the semiconductor integrated circuit in a direction opposite to the signal wiring path of the outward path 2a. For example, it is arranged so as to rotate counterclockwise and in an open loop in a state close to and parallel to the outward path 2a, and to return the terminal end to the vicinity of the drive circuit 1. Note that it is necessary to wire the outgoing path 2a and the return path 3a so that the wiring lengths are equal.

That is, a sine waveform having a complementary relationship is
The start end is the drive circuit 1 at the same observation point, but the transmission path is transmitted by the forward path 2a and the return path 3a which are branched in two directions and wired around the periphery in the semiconductor integrated circuit. The signal transmission directions of the lines are opposite to each other. Note that the signal delay after propagation is greatest near the observation point O, which is the terminal end of the wiring path, in both the forward path 2a and the return path 3a.

The voltage comparators 4 to 7 receive sine wave signals from the forward path 2a and the return path 3a, respectively, and compare voltage levels. As a result of the comparison, the sine wave signal of the forward path 2a
When the sine wave signal of the forward path 2a becomes higher than the sine wave signal of the return path 3a, the logic level "0" is output.

FIG. 2 showing an operation waveform diagram of the voltage level comparison.
Is referred to, for example, the outward path 2a at each observation point O, a, c
By comparing the propagation waveforms of the return path 3a with the voltage levels of the voltage comparators 4, 6, and 7, it is shown that the output of the voltage comparator makes a transition at the point where the waveforms cross each other.

That is, at time t = 1, the voltage level of the forward path 2a and the voltage level of the return path 3a at the observation point O are complementary, so that the voltage level of one half of the power supply voltage = 1V
And the output waveform of the differential amplifier 1 at the observation point O changes to the “1” level.

At time t = 33, the outgoing path 2a of the observation point O
At the observation point O, the output waveform of the differential amplifier 1 at the observation point O is inverted to the “0” level.

At time t = 9, the voltage level of the forward path 2a at the observation point a coincides with the voltage level of the return path 3a = 1.4 V, so that the output waveform of the voltage comparator 4 at the observation point a is at the "1" level. Changes to

At time t = 33, the outbound path 2a of the observation point a
And the voltage level of the return path 3a = 0.6V again, the output waveform of the voltage comparator 4 at the observation point a is inverted to the “0” level.

At time t = 9, the voltage level of the forward path 2a at the observation point c coincides with the voltage level of the return path 3a = 0.6 V, so that the output waveform of the voltage comparator 6 at the observation point c is "1" level. Changes to

At time t = 33, the outbound path 2a of the observation point c
And the voltage level of the return path 3a = 1.4 V, the output waveform of the voltage comparator 6 at the observation point c is inverted to the “0” level.

It can be seen that the phase of the waveform output at each observation point O, a, c, d is constant regardless of the distance.

When there is a block using a clock used at each observation point O, a, c, d as a basic clock,
If the clock skew is within the allowable range in operation, it is not necessary to add a control circuit.

In the present embodiment, the reason that the sine wave signal is input to the voltage comparators 4 to 7 is that the frequency of the sine wave signal has only the fundamental frequency (f0) component, and the frequency This is because there is an advantage that it is possible to avoid deterioration of the frequency characteristics in the transmission line without having a high harmonic.

Next, the operation of the propagation signal in the embodiment of the present invention having the above-described configuration will be described with reference to FIGS. First, the symbols in FIG. 2 will be described.

[0052] delay time _{T af = T-T a (} T in the delay time T _o = 0 delay time of the forward observation point _a T _ao = T a backward observation point a in the forward path and the backward path of the observation point O is the forward path Next, the operation will be described. As described above, the sine wave signal to be the original clock signal is supplied to the observation point O of the drive circuit 1 having the differential output. Output signals of the drive circuit 1 are supplied to signal transmission lines of the forward path 2a and the return path 3a which are arranged in opposite directions and with the same wiring length.

When this signal is expressed by an equation, for example, the signal waveforms of the forward path 2a and the return path 3a at the observation point a can be expressed by the following equations.

Signal at observation point a on outward path 2a ya = sin
{Ω (t−Ta)} ω = 2πf Signal at observation point a on return path 3a yaf = sin ｛ω (t−
T + Ta)｝ Assuming that a time at which ya = yaf at which both signals intersect is ta, sin ｛ω (ta−Ta)｝ = sin ｛ω (ta−T +
Ta) {2 cos {ω (ta-T)} sin} (ω (T
−2Ta)) / 2｝ = 0 sin {(ω (T−2Ta)) / 2} is a constant, and thus is not 0.

2cos {ω (ta−T)} = 0 Therefore, ω (ta−T) = π / 2 + 2mπ m = 0, 1, 2, ‥‥‥ ta = (1 / ω) (ωT + π / 2 + 2mπ) (1) At observation point a in FIG. 2, the time at the point where the forward waveform 1 and the return waveform 2 intersect represents ta in equation (1).

At the observation point a, the forward waveform 1 and the backward waveform 2
Is converted by the voltage comparator 4 to generate a clock waveform A having a binary level of a logical level “0” or “1”.

Similarly, for the observation point c, the time at which both signals intersect is represented by tc, and by solving the equation, sin {ω (tc−Tc)} = sin ｛ω (tc−T +
Tc)｝ Therefore, tc = (1 / ω) (ωT + π / 2 + 2mπ) (2) At observation point c in FIG. 2, the time at the point where the forward waveform 2 and the return waveform 1 intersect is expressed by the following equation. This represents tc in (2).

At observation point c, outgoing waveform 2 and returning waveform 1
Is converted by the voltage comparator 6 to generate a clock waveform C having a binary level of “0” or “1”.

As shown in the above equations (1) and (2) and the timing chart of FIG. 2, ta = tc. That is, it means that the time (phase) at which the waveforms at the observation points a and c intersect is the same.

As described above, according to the present invention, the driving circuit 1 for generating differential output signals complementary to each other based on a single-frequency sine wave signal supplied from the outside, A signal distributing means having a signal transmission path of a forward path 2a and a return path 3a for distributing output signals in opposite directions, and a forward path 2a and a return path 3 at each observation point.
a, which receives a differential output signal from the signal transmission path a and converts it to a binary level of a logical level “0” or “1”, thereby providing a skew of the clock signal between the observation points. Can be easily reduced.

Next, a second embodiment of the present invention will be described with reference to FIG. Its basic configuration is the same as that of the first embodiment described with reference to FIG.
And the signal distribution means of the return path 3a and the voltage comparators 4, 5, 7
And

That is, in addition to the main clock skew reducing means of the first embodiment, a sine wave signal is input from the outside and the signal transmission paths of the forward path 2a and the return path 3a are provided along the peripheral portion in the semiconductor integrated circuit. The sine wave signal is input to the differential input buffer 66 from the forward path 2a and the return path 3a of the main clock skew reduction means, and the signal transmission path of the own forward path 2b and the return path 3b is within an arbitrary range inside an arbitrary block area. And at least one set of sub clock skew reducing means 12 extending so as to surround the signal transmission path of the forward path 2a and the return path 3a of the main clock skew reducing means. is there.

The clock signal is used at every place in the semiconductor integrated circuit, and the wiring is often extended to the place where the clock signal is required in the semiconductor integrated circuit. This second embodiment shows a coping method at that time.

That is, taking the point of the observation point c as an example, a single-frequency and complementary sine wave signal supplied from the forward path 2a and the return path 3a is input to the differential input buffer 66. The sine wave signal amplified by the differential input buffer 66 is supplied to the drive circuit 8. The drive circuit 8 generates a differential output signal based on the amplified sine wave signal and supplies the signal to a block area (not shown) arranged at a predetermined place in the semiconductor integrated circuit.

The differential output signal supplied to the block area is provided with a logic level "0" or "1" by, for example, voltage comparators 9a and 9b at predetermined positions in the block area.
Is converted to a binary level clock signal having the following value, and supplied to necessary circuits in the block area.

As described above, in the second embodiment, even when the sine wave signals of the forward path 2a and the return path 3a of the main clock skew reducing means are further extended as the output wiring of the differential input buffer 66, the first As in the embodiment, the forward path 2a of the main clock skew reduction unit has
And the sine wave signal supplied from the return path 3a,
A drive circuit 8 for generating a differential output signal having a complementary relationship with each other, a signal distribution unit having a signal transmission path of a forward path 2b and a return path 3b for distributing the differential output signal in opposite directions, At each observation point within the application range of the sub clock skew reduction means, the differential output signal from the signal transmission path of the forward path 2b and the return path 3b is input, and the binary level of the logical level "0" or "1" is set. The provision of the voltage comparators 9a and 9b for conversion has an effect that the skew of the clock signal between the observation points can be easily reduced as in the first embodiment.

Next, a third embodiment of the present invention will be described. The basic configuration thereof is similar to that of the second embodiment described with reference to FIG. 3, and the signal distribution means including the drive circuit 1, the differential input buffer 66, the drive circuits 8, 2a and 3b, and 2b
And 3b and the voltage comparators 4, 5,
7 and voltage comparators 9a and 9b.

The difference from the second embodiment is that, in addition to the main clock skew reducing means and the sub clock skew reducing means, at least one set of the sub clock skew reducing means has a voltage comparator 9b having a logic level clock signal. And distributes the clock signal of the logical level to internal circuits by delay adjusting buffers 10 and 11 having a tree structure.

In the third embodiment described above, the clock signal is further extended by the voltage comparator 9b of the sub clock skew reduction means 12, and a delay adjusting buffer or the like, for example, a tree structure or the like is applied beyond that. With the configuration of the sub clock skew reducing means 13, the skew can be further adjusted by finely adjusting the clock delay.

Therefore, as in the first and second embodiments, the forward path 2a of the main clock skew reducing means is provided.
A driving circuit 8 for generating differential output signals having a complementary relationship with each other based on a clock signal of a differential input buffer 66 for inputting a sine wave signal of the return path 3a; The signal distribution means having the signal transmission paths of the forward path 2b and the return path 3b, and the observation points within the application range of the auxiliary clock skew reduction means, from the signal transmission paths of the forward path 2b and the return path 3b. By providing the voltage comparators 9a and 9b which receive the differential output signal as input and convert the binary level to a logical level "0" or "1" and a buffer having a tree structure, similarly to the first and second embodiments, There is an effect that the skew of the clock signal between the observation points can be easily reduced and the skew can be reduced more finely.

Next, a fourth embodiment will be described. Referring to FIG. 4 showing the configuration of the fourth embodiment, the difference from the first embodiment is that a sine wave signal serving as a basic clock is supplied to the drive circuit 1 and converted into a differential output signal. The forward path 2 c and the return path 3, which are connected to the subsequent stage and are provided so as to be transmitted in opposite directions once through the capacitive element 14.
c.

That is, by transmitting the signal to the signal transmission path via the capacitance elements 14 and 15, the bias voltage constantly applied to the transmission line by the capacitance (C) coupling (in this embodiment, the power supply voltage as described above)影響) can be eliminated.

The clock signal generated at each of the observation points 0, a, b, c, and d is such that a clock signal that oscillates around the bias voltage can be stably compared by the voltage comparators 4 to 7. It becomes possible.

Also in the above-described fourth embodiment, the driving circuit 1 for generating differential output signals complementary to each other based on a single-frequency sine wave signal supplied from the outside.
Signal distributing means having a signal transmission path of a forward path 2c and a return path 3c for distributing the differential output signals in opposite directions, and a forward path 2c and a return path 3c at each observation point.
And the voltage comparators 4 to 7 which receive the differential output signal from the signal transmission path and convert the signal into a binary level of a logical level “0” or “1”. Can be easily reduced and a complementary sine wave signal is sent out to the signal transmission path via the capacitance elements 14 and 15, respectively. Therefore, the clock generated at each of the observation points 0, a, b, c, d The signal has the effect of oscillating around the bias voltage.

[0075]

As described above, the clock signal distribution circuit and the distribution method of the present invention generate differential output signals complementary to each other based on a single-frequency sine wave signal supplied from the outside. Drive means comprising a differential amplifier and an open-loop circuit 2 which circulate in opposite directions and return to the vicinity of the base point with the complementary output terminals of the signal drive means as base points.
Signal distribution means having a pair of signal transmission lines having two wiring paths arranged close to and parallel to each other and having one wiring path as the outward path and the other wiring path as the return path, and arbitrary observation of the signal transmission paths of the outward path and the return path The main clock skew reducing means, which is composed of a voltage comparison means for converting a complementary differential output signal at a point into an input and converting the signal into a binary clock signal of a logic level, is distributed. Signal skew can be easily reduced.

Further, since the distribution can be performed by a combination of the main and sub clock skew reduction means, the skew of the clock signal between the observation points in each means can be easily reduced.

Further, since the distribution can be made by a combination of the main and sub clock skew reduction means and the delay adjusting buffer having the tree structure, the distribution can be made between the observation points in each means and at the end of the delay adjusting buffer having the tree structure. The skew of the clock signal in the internal circuit can be easily reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a configuration diagram of second and third embodiments of the present invention.

FIG. 4 is a configuration diagram of a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of an example of a conventional clock signal distribution circuit.

FIG. 6 is a diagram showing a configuration of an LSI to which the global clock distribution circuit 2 of FIG. 5 is applied.

[Explanation of symbols]

 O, a, b, c, d Observation points 1, 8 Driving circuits 2a, 2b, 2c Outbound paths 3a, 3b, 3c Inbound paths 4, 5, 6, 7, 9a, 9b Voltage comparators 10, 11 Delay adjustment buffers 12 , 13 Sub clock skew reducing means 14, 15 Capacitance elements 31,... 41 Clock buffer pair 66 Differential input buffer 100 Global clock generation circuit 200 Global clock distribution circuit 300 Global clock wiring 400,. ~, 418 Circuit block 500, ~, 504 Local clock distribution circuit

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Claims (15)

[Claims] 1. A signal driving means for generating a pair of differential output signals having a complementary relationship based on a single-frequency sine wave signal supplied from outside, and a complementary output terminal of the signal driving means. , Two open loop-shaped wiring paths that go around in opposite directions and return to the vicinity of the base point are arranged close to and parallel to each other, and one of the wiring paths is set as the outward path and the other is set as the return path. Having a signal transmission line pair,
Signal distribution means for distributing the pair of differential output signals respectively corresponding to the pair of differential transmission signals through the signal transmission line pair into the semiconductor integrated circuit; and the complementary differential transmitted to any observation point of the signal transmission line pair. A clock signal distribution circuit, comprising: a main clock skew reducing unit configured to convert an output signal into a binary clock signal of a logical level. 2. A method according to claim 1, wherein the plurality of signal transmission lines are arranged at a plurality of points in an open-loop signal transmission line pair including a forward path and a return path formed in the semiconductor integrated circuit. In a clock signal distribution circuit provided with voltage comparing means for comparing voltage levels of propagation signals transmitted from each other and generating a result of the comparison as an internal clock signal, the signal driving means comprises a differential amplifier and comprises a single externally supplied signal. Based on the sine wave signal of the frequency, a pair of sine wave signals having a complementary relationship with each other are generated and sent from the complementary signal output terminals to the signal transmission line pair, respectively. A clock distribution circuit for comparing a voltage level of a wave signal, converting the voltage level into a binary clock signal having a logical level, and outputting the converted clock signal. 3. The signal driver according to claim 1, wherein the signal driver supplies the complementary pair of sine wave signals that are differentially output to corresponding signal transmission lines of the signal transmission line pair via respective capacitive elements. A clock distribution circuit as described. 4. A pair of complementary output terminals of said signal driving means as means for removing conversion level fluctuation of said voltage comparing means caused by a bias voltage generated in said signal transmission line pair by said complementary pair of sine wave signals. 3. The clock distribution circuit according to claim 1, further comprising a capacitive element inserted in series between each corresponding signal transmission line of each of the signal transmission line pairs. 5. The clock distribution circuit according to claim 1, wherein the start ends of said signal transmission line pairs are connected to complementary signal output ends of said signal driving means, respectively. 6. A signal transmission path extending from one of a pair of complementary signal output terminals of the signal driving means as a starting point, around the periphery in the semiconductor integrated circuit, and extending near the starting end. The return path starts at the other of the pair of complementary signal output terminals of the signal drive means, and goes around the periphery of the semiconductor integrated circuit from the vicinity of the end of the forward path in a state close to and parallel to the forward path. The clock distribution circuit according to claim 1, further comprising a wiring structure serving as a signal transmission path extending to near a start end of the return path. 7. A pair of complementary signal output terminals of said signal driving means as phase equalization means for equalizing the phase of said clock signal converted into binary of a logic level by said voltage comparison means at a plurality of said observation points. 3. The clock distribution circuit according to claim 1, wherein the clock distribution circuit has a wiring structure in which the signal transmission paths of the forward path and the return path connected to the signal path are arranged with equal-length wiring. 8. The main clock skew reducing means in addition to the main clock skew reducing means which receives the sine wave signal from the outside and provides the signal transmission line pair along a peripheral portion in the semiconductor integrated circuit. The sine wave signal is input from the forward path and the return path, and the sub-clock skew reducing means extends so that its own signal transmission line pair surrounds an arbitrary range inside the block area. 4. The clock signal distribution circuit according to claim 1, further comprising at least one set in an arbitrary block area inside the signal transmission line pair included in the main clock skew reduction unit. 9. The buffer circuit according to claim 8, wherein said logic level clock signal provided from said voltage comparing means of said at least one set of sub-clock skew reducing means is distributed to internal circuits by tree-structured delay adjusting buffer means. Clock signal distribution circuit. 10. Propagation signals transmitted in opposite directions on an open-loop signal transmission line pair formed on a peripheral portion in a semiconductor integrated circuit and formed of a forward path and a return path, are defined in a complementary relationship with each other and in advance. A pair of sine wave signals having a single fundamental frequency are provided from corresponding complementary signal output terminals of the signal driving means, respectively, and the voltage levels of the transmitted complementary sine wave signals are compared to determine a logical level. 2
A clock distribution method, wherein voltage comparison means for converting and outputting a clock signal of a value is arranged near an arbitrary position of the signal transmission line pair to which the complementary sine wave signal is transmitted. 11. The complementary sine wave signal provided as a differential output from an output terminal of the signal driving means is supplied to a corresponding signal transmission line of the signal transmission line pair via a capacitance element. The described clock distribution method. 12. The forward path extends from one of a pair of complementary signal output terminals of the signal driving means as a starting point, around a peripheral portion in the semiconductor integrated circuit, and extending near the starting end as a terminating end. And the return path starts at the other of the pair of complementary signal output terminals of the signal driving means, and from the vicinity of the end point of the forward path around the peripheral portion in the semiconductor integrated circuit close to and parallel to the forward path. The clock distribution method according to claim 10, wherein a signal transmission path extends and extends near a start end of the return path. 13. The clock distribution method according to claim 10, wherein the signal transmission paths of each of said pair of signal transmission lines in an open loop connected to a pair of complementary signal output terminals of said signal driving means are arranged with equal length wiring. 14. The main clock skew reducing means which receives the sine wave signal from the outside and extends the signal transmission line pair along a peripheral portion in the semiconductor integrated circuit. At least one set of sub-clock skew reduction means for inputting the sine wave signal from the forward path and the return path of the reduction means is arranged in an arbitrary block area inside the signal transmission line pair of the main clock skew reduction means. 12. The clock signal distribution method according to claim 10, wherein said pair of signal transmission lines of said auxiliary clock skew reducing means extends so as to surround an arbitrary range inside said block area. 15. The main clock skew reducing means,
At least one set of said auxiliary clock skew reducing means;
15. The clock signal of a logical level is distributed to an internal circuit by using a delay adjusting buffer means having a tree structure for inputting a clock signal of a logical level output from the voltage comparing means of the sub clock skew reducing means. The clock signal distribution method as described in the above.