JP2696738B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a circuit composed of a CMOS transistor and a bipolar transistor and having a synchronous circuit, and more particularly to a semiconductor integrated circuit in which the skew of clock and data output from a chip is very small. .

[0002]

2. Description of the Related Art FIG. 4 shows a conventional semiconductor integrated circuit LSI ₁₀ . The semiconductor integrated circuit LSI ₁₀ represents one chip and has a CM
It has a circuit in which OS transistors and bipolar transistors coexist (see Reference 1: “Highly Integrated ECL”).
/ TTL gate array "Ueda, Hanibuchi, Ueda, Hatanaka, Azumaya, Saito, IEICE Integrated Circuits Study Group, ICD8
9-91, p33-38). CI ₁₀ is a clock input terminal, DI ₁₀ is a data input terminal, CO ₁₀ is a clock output terminal, and DO ₁₀ is a data output terminal. Each input signal is EC
The input circuits ECI ₁ and ECI ₂ are L level signals.
This is a BiCMOS circuit for level-converting an ECL level input signal into a CMOS level input signal (Ref. 1, p3)
6, Reference document 2: "BiCMOS technology" by Kubo, IEICE, Corona, p. 122). Each output signal is at the ECL level, and the output circuits CEO ₁ , C
EO ₂ is a BiCMOS circuit for level-converting an internal CMOS level input to an ECL level output (see References 1, p36, FIG. 6). CK ₁₀ is a conventional clock circuit system, and includes driver circuits (CMOS or BiCMOS driver Ref. 2, p119, 120, etc.) CB ₁₀ , C
B ₁₁ and CB ₁₂ . Input terminal I of the clock circuit CK ₁₀ is connected to the input of the driver circuit CB _10, the output of the driver circuit CB ₁₀ is connected is connected to the input of the driver circuit CB ₁₁ to the output terminal C ₁₀ of the clock circuit CK ₁₀ The output of the driver circuit CB ₁₁ is the driver circuit C
Is connected is connected to the input of the R ₁₂ to the output terminal C ₁₁ of the clock circuit CK _10, the output of the driver circuit CB ₁₂ is connected to the output terminal O and the output terminal C ₁₂ of the clock circuit CK _10. Input terminal I of the clock circuit CK ₁₀ is connected to the output of the input circuit ECI _1, the output terminal O of the clock circuit CK ₁₀ is connected to the input I of the output circuit CEO _1.
CC ₁₀ in FIG. 4 is an internal C for synchronous transfer of data at the clock
It is a MOS (or BiCMOS) circuit. L ₁₀ , L
Reference numeral ₁₁ denotes an arbitrary circuit, and any circuit such as a logic circuit and a memory circuit is not concerned with the claims of this specification. CF ₁₀ ,
CF ₁₁ and CF ₁₂ are CMOS flip-flop circuits. Input terminal of the internal circuit CC ₁₀ is connected to the output of the input circuit EC _12, the data input D of the flip-flop circuit CF _10. Of flip-flop circuit CF ₁₀ clock input C
Is connected to the input terminal C ₁₀ of the internal circuit CC _10, the data output Q of the flip-flop circuit CF ₁₀ is connected to the input I of any circuit L _10. Data input D of the flip-flop circuit CF ₁₁ is connected to the output terminal O of any circuit L _10,
Clock input C is connected to the input terminal C ₁₁ of the internal circuit CC _10, the data output Q of the flip-flop circuit CF ₁₁ is connected to the input of an arbitrary circuit L _11. Data input D of the flip-flop circuit CF ₁₂ is the output terminal O of any circuit L ₁₁
Is connected to the clock input C is connected to the input terminal C ₁₂ of the internal circuit CC _10, the data output Q of the flip-flop circuit CF ₁₂ is connected to the output terminal O of the internal circuit CC _10. The output terminal O of the internal circuit CC ₁₀ is further connected to the output circuit CF.
It is also connected to the input of O _2.

The operation of the conventional semiconductor integrated circuit LSI ₁₀ will be described with reference to FIG. Clock ECL level is inputted to the input terminal CI ₁₀ of the semiconductor integrated circuit LSI _10. The clocked by input circuit FCI ₁ is input to the input terminal I of the CK ₁₀ is converted to CMOS levels (Figure 5 CK _10,
I). The driver circuit CB ₁₀ is in the clock (FIG. 5 to the flip-flop circuit CF ₁₀ as an input the clock C
K _10, and supplies the C _10. On the other hand, a semiconductor integrated circuit LSI ₁₀
Data of the ECL level is inputted to the input terminal DI ₁₀ of. The input circuit EC ₁₂ data input to the input terminal I of the internal circuit CC ₁₀ is converted to CMOS levels (Fig. 5 CC _10, I). Flip-flop circuit CF
_10, the input data of the input terminal I of the internal circuit CC ₁₀ synchronized with the output clock of the driver circuit CB _10, and outputs the synchronized data (FIG. 5 CF _10, Q) from the output terminal Q.
A synchronized clock, the data _{(D 1, D 2, ...} ) the clock CK _10, C ₁₀ uptake in the flip-flop circuit CF ₁₀ at the high, flip-flop circuit CF ₁₀ at the falling edge of the clock CK _10, C ₁₀ Holds data within
From falling edge of the clock CK _10, C ₁₀ to the output terminal O of the flip-flop circuit CF ₁₀ is to output the held data.

The synchronization data (D ₁ , D ₂ ,...) Output from the flip-flop circuit CF ₁₀ is passed through a multi-stage logic gate in an arbitrary circuit L ₁₀ (or is taken in and out of a memory). logic output data of the circuit L ₁₀ (in FIG. 5 L _10, O of _{D 1 ', D 2',} ...) become. The logic output data further in the flip-flop circuit CF _11,
Clock output from the driver circuit CB ₁₁ (in FIG. 5 C
F ₁₁ , C). Although not shown in FIG. 5, the synchronization data which is the output of the flip-flop circuit CF _11, the logic is taken by any circuit L _11, flip-flop circuit CF ₁₂ from the flip-flop circuit CF ₁₀ of the
Through the same process and delivery to, synchronization is taken by the output clock of the driver circuit CB _12, is output from the output terminal of the internal circuit CC _10. The output data is output from the output circuit CEO.
_2, the data is converted from the CMOS level to the ECL level and subjected to the desired logic processing in the semiconductor integrated circuit LSI ₁₀ , and is also converted into C by the output circuit CEO _1.
Is output in synchronization with the output terminal DO ₁₀ of the semiconductor integrated circuit LSI ₁₀ to the MOS level level converted to ECL level from the clock signal (output from the terminal CO _10). As described above, the data processing is performed by the arbitrary circuit L while performing the cyclic transfer of the data.
₁₀ has been described the operation of the conventional semiconductor integrated circuit LSI ₁₀ performed in L _11. Here, the flip-flop circuit is CF ₁₀ ,
Although three stages of CF ₁₁ and CF ₁₂ are described, the number of stages is arbitrary. Although the number of data is taken as one bit, the number of bits is arbitrary.

Next, a conventional semiconductor integrated circuit L will be described with reference to FIG.
The clock delay time of the SI ₁₀ will be described. The clock signal is supplied to the input circuit ECI in the entire semiconductor integrated circuit LSI _10.
1 and the delay time t _{d1 for} the transit time of the driver circuit CB ₁₀ ,
Transit time t _d2 of the driver circuit CB _11, the driver circuit CB
It is the sum of the transit time of the transit time and the output circuit CEO ₁ of ₁₂ with a propagation delay time t _dA1. These delay times are determined as follows.

First, in order to obtain a stable operation of the flip-flop circuit, the clock fetch edge (falling edge in this case) needs to be located substantially at the center of the data. Taking the flip-flop circuits CF ₁₀ and CF ₁₁ as an example, it is necessary to keep the data setup times t _s1 and t _s2 and the data hold times t _h1 and t _h2 in FIG. 5 at about T / 2. Therefore, the driver circuit and the delay time t _d2 of the clock by CB _11, the sum of the data delay time of the data output delay time and any circuit L ₁₀ of the flip-flop circuit CF ₁₀ t
_dL1 must be designed equal. However, since the general logic circuit stages of any circuit L ₁₀ is the greater than the number of circuit stages of the driver circuit CB _11, and imparted a delay circuit to the driver circuit, the delay time of the delay time t _dL1 a driver circuit of any circuit L ₁₀ ((T _d2 −T
/ 2) = t _dL1 + (driver delay)). Therefore, the delay time of the driver circuit CB ₁₁ and CB ₁₂ are the optional circuit L ₁₀ L
Includes a delay delay time adjustment amount of the _11, the clock propagation delay time of the semiconductor integrated circuit LSI ₁₀ t _dA1 be any circuit L
It will contain the ₁₀ and delay time adjustment amount of the delay time of the L _11.

[0007]

In a conventional semiconductor integrated circuit, a multi-stage CM including a circuit for delay adjustment is provided in a one-chip clock signal passage path like a circuit LSI _{10 in} FIG.
There is an OS (or BiCMOS) driver circuit. Therefore, the propagation delay time t _dA1 of the clock signal increases as shown in FIG. The delay time variation of the circuit due to the chip manufacturing / operating environment (process condition, power supply voltage, temperature) is called skew. The skew of one stage of the CMOS driver circuit used in the conventional semiconductor integrated circuit is the propagation delay time. It is 1.5 to 2.0 times as large as the central value (Ref. 3: "Design of CMOS VLSI" by Iizuka, Baifukan, p124). For this reason, the conventional semiconductor integrated circuit has a disadvantage that the clock signal propagation delay time t _dA1 is large in the entire chip and the skew is 1.5 to 2.0 times as large.

The present invention relates to a CMOS (or BiCMO)
S) The clock signal propagation delay time of the semiconductor integrated circuit is reduced and the clock propagation delay time skew is reduced while maintaining the large scale of the semiconductor integrated circuit and the high-speed synchronous operation function. It is an object of the present invention to provide a semiconductor integrated circuit suitable for stably transmitting and receiving a high-speed signal at the same time.

[0009]

According to the present invention, first, a semiconductor integrated circuit is integrated with an ECL circuit region and a CMOS (or Bi) circuit.
The internal logic circuit requiring a high degree of integration is a CMOS (or BiCMOS) circuit formed by dividing the clock signal path into high-speed and low-skew ECL circuits. Is different from the prior art. Second, it has a retiming circuit that synchronizes the data output of the internal logic circuit with a clock that does not have a unique phase relationship with the data output, and a clock that passes only through the ECL circuit;
This is different from the prior art in that a delay difference between data passing through a MOS (or BiCMOS) circuit and a variation of the delay difference due to a process variation or the like can be corrected from an external terminal by a retiming circuit.

[0010]

FIG. 1 shows a first embodiment of the present invention. In the figure, L
SI ₁ is the semiconductor integrated circuit of the present invention, ECL ₁ is the first EC
L circuit area, ECL ₂ is the second ECL circuit area, CMO
S ₁ is a CMOS (or BiCMOS) circuit area, C
K ₁ is an ECL clock circuit, TI
M is a retiming circuit characterized by the present invention, CK ₂ is C
MOS (or BiCMOS) clock circuit, CC
Reference numeral ₁₀ denotes a CMOS (or BiCMOS) internal circuit. The semiconductor integrated circuit LSI ₁ has a clock input terminal CI
_1, the data input terminal DI _1, the clock output terminal CO _1,
Data output terminal DO ₁ , clock phase switching terminal CF
With a _1. The first ECL circuit area includes an ECL input circuit E
I ₁ and EI ₂ and an ECL clock driver circuit EB ₁ are arranged, and an ECL output circuit EO is provided in the second ECL circuit area.
₁ , EO ₂ and ECL clock driver circuit EB ₂ and EC
L placing flip-flop circuit EF ₁ and ECL phase switching circuit ED _1. First ECL circuit area and CMOS
(Or BiCMOS) circuit area
ECL- for converting a level signal to a CMOS level
CMOS level conversion circuits EC ₁ and EC ₂ are arranged,
ECL circuit area and CMOS (or BiCMOS)
The span, ECL-CMOS level converter circuit EC ₃ for level converting the ECL level signals to CMOS level and C
CM for converting a MOS level signal to an ECL level
Placing the OS-ECL level converting circuit CE _1. CMO
The S (or BiCMOS) circuit region, a clock circuit CK _2, placing the internal circuit CC ₁₀ similar to the prior art. Input terminal CI ₁ of the semiconductor integrated circuit LSI ₁ is connected to the input terminal I of the input circuit EI _1, the output terminal O of the input circuit EI ₁ is connected to an input of the driver circuit EB _1, the output of the driver circuit EB ₁ level connected to the input of the input conversion circuit EC ₁ and the driver circuit EB _2. Driver circuit EB ₂
The output terminal O of the connection life and death to an input terminal I of the phase switching circuit ED _1, vital connected to the clock input terminal C of the flip-flop circuit EF _1, connected to the input terminal I of the output circuit EO _1. The output terminal O of the output circuit EO ₁ is connected to the output terminal CO ₁ of the semiconductor integrated circuit LSI ₁ . Input terminals DI ₁ of the semiconductor integrated circuit LSI ₁ is connected to the input terminal I of the input circuit EI _2, the output terminal of the input circuit EI ₂ is connected to the input terminal I of the level conversion circuit EC _2. An output terminal O of the level conversion circuit EC ₂ is connected to the input terminal I of the internal circuit CC _10, the output terminal O of the internal circuit CC ₁₀ is connected to the input terminal I of the level conversion circuit CE _1, the level conversion circuit CE ₁ the output terminal O of the connected to the data input terminal D of the flip-flop circuit EF _1, the data output Q of the flip-flop circuit EF ₁ is connected to the input terminal I of the output circuit EO _2, the output terminal O of the output circuit EO ₂ is connected to the output terminal DO ₁ of the semiconductor integrated circuit LSI _1. The level converter circuit output terminal O of the EC ₁ is connected to an input terminal I of the clock circuit CK _2, the output terminal C ₁₀ of the clock circuit CK ₂ is an internal circuit CC
Connected to the input terminal C ₁₀ of _10, a clock circuit CK output terminal C ₁₁ of ₂ is connected to the input terminal C ₁₁ of the internal circuit CC _10, the level conversion circuit EC ₃ to the input terminal C ₁₂ of the internal circuit CC ₁₀
Output terminal O is connected. An output terminal O of the phase switching circuit ED ₁ is connected to the input terminal I of the level conversion circuit EC _3, the control input terminal C of the phase switching circuit ED ₁ to the clock phase switching the external signal input terminals CF ₁ of the semiconductor integrated circuit LSI ₁ Connecting. On the other hand, the input terminal I of the clock CK ₂ is connected to an input of the driver circuit CB _1, the output of the driver circuit CB ₁ is connected to the output terminal C ₁₀ of the clock circuit CK ₂ as well as connected to the input of the driver circuit CB ₂ , the output of the driver circuit CB ₂ is connected to the output terminal C ₁₁ of the clock circuit CK _1. Connection in the internal circuit CC ₁₀ is maintained at conventional, L ₁₀ and L ₁₁ is arbitrary circuit, CF _10,
CF _11, CF ₁₂ is a CMOS flip-flop circuit, the input terminal I of the internal circuit CC ₁₀ is connected to the data input D of the flip-flop circuit CF _10, the clock input C is an internal circuit CC ₁₀ of the flip-flop circuit CF ₁₀ connected to the input terminal C ₁₀ of the data output Q of the flip-flop circuit CF ₁₀ is connected to the input I of any circuit L _10, data input D of the flip-flop circuit CF ₁₁ is connected to the output terminal O of any circuit I ₁₀ and, a clock input C is connected to the input terminal C ₁₁ of the internal circuit CC _10, the data output Q of the flip-flop circuit CF ₁₁ is connected to an input of an arbitrary circuit L _11. Data input D of the flip-flop circuit CF ₁₂ is connected to the output terminal O of any circuit L _11, the clock input C is an internal circuit CC ₁₀
Connected to the input terminal C ₁₂ of the flip-flop circuit CF ₁₂
The data output Q is connected to the output terminal O of the internal circuit CC _10.

Next, the operation of the semiconductor integrated circuit LSI _{1 according to} the first embodiment of the present invention will be described with reference to FIG. _First , the data input from the input terminal DI _{1 is} converted to an arbitrary circuit L
_The process up to output to the ₁₁ output terminal O will be described. Input terminal D
Data input from the I ₁ passes through the input circuit EI ₂ input to the level conversion circuit EC _2. The data (CC ₁₀ and I in FIG. 2) converted from the ECL level to the CMOS level by the level conversion circuit EC ₂ is synchronized with the output clock of the driver circuit CB ₁ by the flip-flop circuit CF ₁₀ . The clock is input from an input terminal CI ₁ of the semiconductor integrated circuit LSI ₁ (CI _{1 in} FIG. 2), driven by an input circuit EI ₁ and a driver circuit EB ₁ , and driven by a level conversion circuit EC _1.
Conversion from L level to CMOS level. Clock converted to CMOS levels, supplied to the internal circuits in the driver circuit CB ₁ (in FIG. ₂ CK 2, C _10). Flip-flop circuit CF ₁₀ takes the synchronization of the data of FIG. 2 in CK _2, C clock in Figure 2 in CC ₁₀ for _10, I. The output data (CF ₁₀ and Q in FIG. 2) is input to an arbitrary circuit L ₁₀ and takes a desired logic (read / write to a memory including). Optional circuit L ₁₀
(L ₁₀ , O in FIG. 2) is synchronized by the flip-flop circuit CF ₁₁ with an inverted clock (CF ₁₁ , C in FIG. 2) of the output of the driver circuit CB ₂ . Here, it is needless to say the output of the driver circuit CB ₂ can be synchronized without necessarily inverted clock. Since the range the effect of the present invention if it has a synchronization circuit to the internal circuit CC _10, and an example of the inverted clock as an example. The output of the flip-flop circuit CF ₁₁ is input to any circuit L _11, outputs from the output terminal O of any circuit L ₁₁ takes the desired logic (read or write to the free memory) (FIG. 2 in L _11, O).

[0012] occurs at this point, the output data (in FIG. 2 L ₁₁ any circuit L ₁₁ from an input clock (FIG. 2 in CI _1),
The delay until O) is described below. This delay is the delay from the input clock to the data output of the flip-flop circuit CF _10, and the delay flip-flop circuit CF _11, it is divided into delay plus one clock cycle of 2 minutes to delay any circuit L ₁₁ it can. Delay from the input clock to the data output of the flip-flop circuit CF ₁₀ includes an input clock of the clock input to flip-flop circuit CF ₁₀ (CI
The delay from ₁₎ is obtained by adding one clock period of 2 minutes, the delay from the input clock of the clock input to flip-flop circuit CF ₁₀ (CI ₁₎ is an input circuit E
Is I ₁ and the driver circuit EB ₁ and level converting circuit EC ₁ and the driver circuit CB ₁ of the propagation delay time of the sum t _d1 '. Delay of the flip-flop circuit CF ₁₁ includes a delay of any circuit L ₁₀ and the delay time equally combined driver circuit CB ₂ 2
This is the sum t _d2 'of one-half clock periods. The delay of any circuit L ₁₁ is t _dL2 (see FIG. 2). Therefore, the delay from the input clock (FIG. 2 in CI ₁₎ output to the data (in FIG. 2 L _11, O) for any circuit L ₁₁ may be summarized as follows.

(Data delay) = t _d1 ′ + t _d2 ′ + t _dL2 +
T / 2 ............ (1)

Next, the circuit operation of the clock system will be described.
Unlike the prior art, the clock input to the input terminal CI ₁ includes an input circuit EI ₁ and the driver circuit EB _1, EB ₂
And the output circuit EO ₁ . All of these circuits are ECL circuits having a shorter propagation delay time than a CMOS circuit. As shown in FIG.
Delay time t _dA from the input clock CI ₁ of ₁ is the sum of the propagation delay time of each circuit can be summarized as follows in comparison with the prior art clock delay time t _dA1.

(2) t _dA2 = t _dEI1 + t _dEB1 + t _dEB2 + t _dEO1 (2-a) t _dA1 = t _dECI1 + t _dCB10 + n _L10 · t _dg + n _L11 · t _dCEO1 (2-b) Here, t _dEI1 : propagation delay time of ECL input circuit EI ₁ t _dEB1 : propagation delay time of ECL driver circuit EB ₁ t _dEB2 : propagation delay time of ECL driver circuit EB ₂ t _dEO1 : propagation of ECL output circuit EO ₁ Delay time t _dEC1 : Propagation delay time of ECL-CMOS level conversion input circuit t _dCB11 : Propagation delay time of CMOS driver circuit n _L10 : _Number of gate stages of arbitrary circuit L ₁₀ n _L11 : _Number of gate stages of arbitrary circuit L ₁₁ t _dg : CMOS Gate propagation delay time t _dCEo1 : Propagation delay time of CMOS-ECL level conversion output circuit

[0014] The propagation delay time of the ECL driver circuit is 1/2 to 1/3 of the propagation delay time of the CMOS driver circuit or the CMOS gate. Therefore, the sum of the number of gate stages of the arbitrary circuits L ₁₀ and L ₁₁ is assumed to be n, and the ECL
Output circuit is ECL-CMOS level conversion circuit or CMOS
Assuming that the propagation delay time of the ECL level conversion circuit is 1/2 to 1/3, the clock delay time ratio is (2
From the expressions -a) and (2-b), the following holds.

T _dA2 / t _dA1 = (0.5 + 0.5 + 0.5 + 0.5) / (1 + 1 + n × 1 + 1) = 2 / (n + 3) (3)

The increase in propagation delay time due to a change in the chip environment of the ECL driver circuit (process fluctuation, power supply fluctuation, temperature fluctuation) is about 1.3 times, and a change in the chip environment of the CMOS driver circuit (process fluctuation, power supply fluctuation). , Temperature fluctuation), the increase of the propagation delay time is about 1.5 to 2.0 times. When this variation is applied to equation (3), the clock skew improvement effect of the present invention is obtained as in the following equation.

_{４t dA2} / △ t _dA1 = [2 / (n + 3)] × 1.3 / 2.0) = 1.3 / (n + 3) (4)

If it is assumed that the number n of gate stages of the logic circuit in the LSI is 10, the effect of reducing the clock skew to about 1/10 is obtained from the equation (4).

The operation of the retiming circuit TIM will be described. The retiming circuit TIM is a flip-flop circuit C
A circuit to match the phase of the clock signal and the data signal to be input to the F _12. The phase switching circuit ED _1, and inversion / non-inversion of the phase of the clock signal input to flip-flop circuit CF _12, is a circuit to synchronize a stable data signal unpredictable phase difference between the clock signal. As described above, data to be input to the flip-flop circuit CF ₁₂ is (1) a semiconductor integrated circuit LSI as represented by the formula
Has a delay time from the input clock to ₁ . Meanwhile, the clock input to flip-flop circuit CF ₁₂ from the input clock to the semiconductor integrated circuit LSI _1, an input circuit EI
₁ and the delay time of the driver circuits EB ₁ and EB ₂ (t _dEI1 +
_t dEB2 + t dEB2) and delayed by the time of the sum of the phase switching circuit ED ₁ and the level conversion circuit EC ₃ of the delay time _(t dED1 + t dEC3). The delay time of these data and clock is
Since the number of gate stages in each path and the type of transistor forming the gate (MOS transistor, bipolar transistor) are different, there is no correlation between the direction of change (increase or decrease in delay time) and the amount of change in the LSI manufacturing process. Thus, as indicated by a solid line and a dotted line in FIG. 2L _11. O, and try to fix the clock position, for example, the delay value of any circuit L ₁₁ fluctuates by LSI as t _dL2 and t _dL2 ', the clock of the synchronization position t _p1, operation data setup time available t _s3 or data hold time t _h3 of the flip-flop circuit CF ₁₂ can not be secured. In other words, the clock circuit C including only the ECL circuit
Only the K _1, although the clock skew can be reduced,
The stability of the internal circuit operation of the semiconductor integrated circuit LSI ₁ cannot be equal to or higher than that of the conventional technology. Therefore, selection of the phase switching circuit ED ₁ from the external signal input terminal CF ₁ to input H / L either switching signal, the output of the 180 ° from the solid line or dotted phase signals ED ₁ .O in FIG I do. In FIG. 2, the solid line and the dotted line show the case where synchronization is applied, respectively. Synchronization takes the output signal of the flip-flop circuit CF ₁₂ converts the CMOS level by the level converting circuit to the ECL level, and inputs to the flip-flop circuit EF ₁ (in FIG. 2 EF ₁ .D). This data is stored in the driver circuit E
In the inverted clock of B _2, the flip-flop circuit data setup time EF ₁ t _s4 and the data hold time t _h4
Is satisfied, so that synchronization can be achieved. Therefore, the output of the flip-flop circuit EF ₁ is outputted in synchronization with the clock that has passed through only the ECL circuit. These clock and data signals are output to ECL output circuits EO ₁ , E
Each by O _2, ECL level clock output and 2 in DO ₁ of the semiconductor integrated circuit LSI ₁ shown in FIG. 2 CO ₁
And output as ECL level synchronization output data.

Although the synchronous transfer in the flip-flop circuit of the internal circuit CC ₁₀ is described here twice as an example,
It is arbitrary as long as it is at least once. Although the data width is set to 1 bit for simplicity of description here,
It can easily be inferred that the data width can be arbitrarily set by having a plurality of data passing circuits. Further, although the phase switching circuit example using a circuit to rotate 180 ° the phase of the clock by the control input of the control terminal CF ₁ as ED ₁ in this embodiment, a plurality of control inputs, stepwise (45 clock phases °, 90 °, 135 °, ...)
By applying a well-known phase switching circuit or delay circuit, the phase of the clock and the phase of the data can be more precisely matched. The phase switching circuit ED ₁ In this example, although constituted by ECL circuits,
ECL-CMOS level converter to connect the input terminal I to the output terminal O of the circuit EC _3, connects the output terminal O to the input terminal C ₁₂ of the internal circuit CC _10, TTL from the outside of the semiconductor integrated circuit LSI ₁ (or CMOS) the phase switching circuit ED ₁ C to provide the control signal level input to the control terminal C
It is also possible to use a MOS circuit.

FIG. 3 shows a second embodiment of the present invention. This embodiment differs from the first embodiment in that a serial-parallel (1: 2) conversion circuit and a parallel-serial (2: 1) conversion circuit are added to the data path, and the time margin of the retiming circuit can be further increased. Have. In the figure, LSI
₂ is a second embodiment of the semiconductor integrated circuit of the present invention, ECL ₃ is a first ECL circuit area, ECL ₄ is a second ECL circuit area, CMOS ₂ is a CMOS (or BiCMOS) circuit area, and CK ₂₀ is the present invention. TIM ₂ is a clock path of the ECL circuit, which is a feature of the present invention. The semiconductor integrated circuit LSI ₂ has a clock input terminal CI ₁ , a data input terminal DI ₁ , a clock output terminal CO ₁ , a data output terminal DO ₁ , and clock phase switching terminals CF ₂ and CF ₃ . The first ECL circuit area includes ECL input circuits EI ₂₀ and EI ₂₁ , ECL clock driver circuits EB ₂₀ and EB ₂₁ , and a T-type flip-flop circuit ET.
₂₀ , 1: 2 serial / parallel (S / P) conversion circuit ESP
₂₀ are arranged, and the ECL output circuits EO ₂₀ and EO ₂₁ and the ECL clock driver circuit E are provided in the second ECL circuit area.
B _22, 2: 1 parallel serial (P / S) conversion circuit EP
Placing the S _20, ECL phase switching circuit ED _21, ED _22. First ECL circuit area and CMOS (or BiC
MOS) circuit area, and the ECL level signal is
ECL-CMOS level converter circuit EC ₂₀ for level converting the OS level, the EC _21, EC ₂₂ disposed, a second ECL
Spans the circuit area and the CMOS (or BiCMOS), CMOS-E to the level converting ECL-CMOS level converter circuit EC ₂₃ for level converting the ECL level signals to CMOS level, the CMOS level signal to the ECL level
CL level conversion circuits EC ₂₀ and EC ₂₁ are arranged. CMO
S (or BiCMOS) in the circuit region, CMOS driver circuit _{CB 20, CB 21, CB 22} , CB 23, CMOS
T-type flip-flop circuit C ₂₀ , 1: 2 S / P conversion circuits CSP ₂₀ , CSP ₂₁ , flip-flop circuit CF ₂₀ ,
CF ₂₁ , CF ₂₂ , CF ₂₃ , 2: 1 P / S conversion circuit CPS
₂₀ , CPS ₂₁ and optional circuits L ₂₀ , L ₂₁ are arranged.

The input terminal CI ₁ of the semiconductor integrated circuit LSI ₂
Is connected to the input terminal I of the input circuit EI _{20 and} the input circuit EI ₂₀
An output terminal O of ₂₀ is connected to an input of the driver circuit EB _20,
The output of the driver circuit EB ₂₀ is a flip-flop circuit ET
Connected to the input of the ₂₀ clock input terminal C and the S / P conversion circuit ESP ₂₀ clock input terminal f and the driver circuit EB _21. The output of the driver circuit EB ₂₁ is phase switching circuit ED
₂₁ and the input terminal I of the ED ₂₂ and the P / S conversion circuit EP
Connected to the clock input terminal f of S _20, and the output circuit EO
Connect to ₂₀ input terminals I. An output terminal O of the output circuit EO ₂₀ is connected to the output terminal CO ₁ of the semiconductor integrated circuit LSI _2. The switching control terminal C of the phase switching circuit ED _21, connect the external terminal CF ₂ of the semiconductor integrated circuit LSI _2, the output terminal O of the phase switching circuit ED ₂₁ is 2: 1P /
S converter EPS ₂₀ divided by 2 clock input terminal f / 2
Connect to The switching control terminal C of the phase switching circuit ED _22, connect the external terminals CF ₃ of the semiconductor integrated circuit LSI _2, terminal O of the phase switching circuit ED ₂₂ is connected to the input terminal I of the level conversion circuit EC _23, level Conversion circuit EC
The output terminal O of ₂₃ is a 2: 1 P / S conversion circuit CPS ₂₀ , CP
Connected to the input terminal f / 2 divided by 2 clock S _21.

Further, the output terminal Q of the T-type flip-flop circuit ET ₂₀ is connected to an input terminal of the driver circuit EB _22. An output terminal of the driver circuit EB ₂₂ connects the input terminal I of the level conversion circuit EC _20, to the input terminal f / 2 divided by 2 clocks of the S / P conversion circuit ESP _20. The output terminal O of the level conversion circuit EC ₂₀ is input to the input terminal of the CMOS driver circuit CB _20, the output of the driver circuit CB ₂₀ 1: 2 round of clock input terminals of the 2S / P converting circuit CSP _20, CSP ₂₁ connected to the clock input terminal C of the f / 2 and CMOS of the T-type flip-flop circuit CT _20. Output terminal Q of the T-type flip-flop circuit CT ₂₀ is connected to an input terminal of the driver circuit CB _21, the output terminal of the driver circuit CB ₂₁ 1: 4 divided clock input terminal of the 2S / P converting circuit CSP _20, CSP ₂₁ connected to the input terminal of f / 4 and the driver circuit CB _22, the input terminal of the output terminal of the driver circuit CB ₂₂ is a flip-flop circuit _{CF 20, CF 21, CF 22} , clock CF ₂₃ input terminal C and the driver circuit CB ₂₃ Connect to An output terminal of the driver circuit CB ₂₃ is 2: 1P / S conversion circuit CPS _20, 4-divided clock input terminal f of the CPS ₂₁
/ 4.

The input terminal DI ₁ of the semiconductor integrated circuit LSI ₂
Is connected to the input terminal I of the input circuit EI ₂₁ and the input circuit EI
An output terminal O of ₂₁ 1: connected to the input terminal I of the 2S / P converting circuit ESP _20. 1: Output terminal O ₁ of the 2S / P converting circuit ESP ₂₀ is connected to the input terminal I of the level conversion circuit EC _21, the output terminal O ₂ is connected to the input terminal I of the level conversion circuit EC _22. Output terminals O of the level conversion circuits EC ₂₁ and EC ₂₂ are respectively connected to input terminals I of the 1: 2 S / P conversion circuits CSP ₂₀ and CSP ₂₁ , and output terminals O ₁ and O of the 1: 2 S / P conversion circuit CSP ₂₀ are connected. ₂ is an input terminal I ₁ of any circuit L _20, I
Connected to _2, 1: 2S / P converting circuit output terminal O _1, O ₂ of CSP ₂₁ is connected to the input terminal I _3, I ₄ of any circuit L _20. Output terminal O ₁ of any circuit _{L 20, O 2, O 3} , O 4
Are the flip-flop circuits CF ₂₀ , CF ₂₁ , CF ₂₂ , C
Respectively connected to the data input terminal D of the F _23, the flip-flop circuit _{CF 20, CF 21, CF 22} , the input terminal I ₁ of the data output terminal of the CF ₂₃ Q is each optionally circuit _{L 21, I 2, I 3} ,
To connect to I _4. Output terminal O ₁ of any circuit L _21, O ₂ is 2: 1P / S respectively connected to the input terminal I _1, I ₂ of the conversion circuit CPS _20, the output terminal O ₃ of any circuit L _21, O ₄ is 2:
It is connected to the input terminals I ₁ and I ₂ of the 1P / S conversion circuit CPS ₂₁ respectively. 2: 1P / S conversion circuit CPS _20, the output terminal O of the CPS ₂₁ are respectively connected to the input terminal I of the level conversion circuit CE _20, CE _21, the level conversion circuit CE _20, the output terminal O of the CE ₂₁ are each 2: input terminal I ₁ of 1S / P conversion circuit ESP _20, connected to the I _2. 2: 1 S / P conversion circuit ESP ₂₀
The output terminal O of the connected to the input terminal I of the output circuit EO _21,
The output terminal O of the output circuit EO ₂₁ is a semiconductor integrated circuit LSI ₂
Connecting of the data output terminal DO _1.

Next, the operation of the semiconductor integrated circuit LSI _{2 according to} the second embodiment of the present invention will be described. The basic synchronizing operation is the same as in the first embodiment, and a detailed description will be omitted. Also in the second embodiment, the passage path of the clock signal is E
CL circuit input circuit EI ₂₀ and driver circuits EB ₂₀ , EB
₂₁ and the output circuit EO ₂₀ only. Therefore, similarly to the first embodiment, the propagation delay time of the clock signal is significantly smaller than that of the prior art, and the clock skew can be reduced to about 1/10. In this embodiment, in particular, 1:
Two stages of 2S / P conversion circuits (ESP ₂₀ , CSP ₂₀ , CSP
₂₁ ) Two stages of 2: 1 P / S conversion circuits (CPS ₂₀ , CPS
₂₁ and ESP ₂₀ ), and CMOS arbitrary circuits L ₂₀ , L ₂₁
Is different from that of the first embodiment in that the operation speed is 1/4 of the input / output speed of the LSI. In addition to the same clock the clock signal and the input speed, 2-divided clock, for using various clocks as 4 divided clock, a phase switching circuit to multiple inserts as ED _21, ED _22.

The operation margin of the retiming circuit is expanded as follows. In the present embodiment, the reason why the delay difference between the data and the clock is large, the delay variation is increased due to manufacturing variations, and the margin at the time of synchronization is reduced is that the output stages of the P / S conversion circuits CPS ₂₀ and CPS ₂₁ and synchronization, a synchronization input stage of the P / S conversion circuit EPS _20. This is because the P / S conversion circuits CPS ₂₀ and CPS ₂₁ divide the frequency by 4 (f /
4) and is because the number of gate stages and type of gate of the passage path of the divide-by-2 clock (f / 2) different, the P / S conversion circuit EPS _20, the data level conversion circuit EC ₂₃ and CE ₂₀
This is because it has a relatively large delay of (CE ₂₁ ). Therefore, the phase switching circuit ED _{21 is connected} to the P / S conversion circuit EPS ₂₀
To the clock path to, the phase switching circuit ED ₂₂ P / S
It is inserted into the clock path of the conversion circuits CPS ₂₀ and CPS ₂₁ . As in the first embodiment, by switching the inputs (H, L) of the external terminals CF ₂ and CF ₃ , the clock phase is inverted according to the delay difference between the data and the clock, so that the setup time and the hold time of the flip-flop circuit are changed. Can be secured. In addition, in this embodiment, in addition to the phase switching circuits provided at two locations having a small synchronization margin,
Since rate compared to the first embodiment is synchronized with respect to 1 / 4,1 / 2 and slow data, t in FIG. 2 _s3, t _h3
The data setup time and data hold time are quadrupled and doubled as shown in FIG.

The above described 1: 2 S / P conversion circuit and 2: 1 P / S
Although the configuration using the conversion circuit has been described as an example, it is apparent that the same effect can be obtained with an S / P conversion circuit and a P / S conversion circuit having an arbitrary number of parallel expansions. In this example, the number of clocks and the data width are easy to explain and simplified.
It can be easily analogized that the claimed effect can be obtained with a plurality of clocks and a plurality of data based on the technical idea of the present invention.

[0026]

As described above, according to the present invention,
The clock skew can be reduced to about 1.3 / (n + 3) times (n is the number of logic stages in the LSI, and 1/10 assuming n = 10), and the circuit is reduced due to process variations. Even if the propagation delay time fluctuates, stable synchronous transfer of data becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional semiconductor integrated circuit.

FIG. 5 is a time chart for explaining an operation of a conventional example of a semiconductor integrated circuit.

[Explanation of symbols]

LSI ₁ Semiconductor integrated circuit of the present invention ECL ₁ First ECL circuit area ECL ₂ Second ECL circuit area CMOS ₁ CMOS circuit area CK ₁ ECL clock circuit CK ₂ CMOS clock circuit TIM Retiming circuit CC ₁₀ CMOS Internal Circuit CI ₁ clock input terminal DI ₁ data input terminal CO ₁ clock output terminal DO ₁ data output terminal CF ₁ clock phase switching external signal input terminal EI ₁ , EI ₂ ECL input circuit FB ₁ , FB ₂ ECL clock driver circuit EO ₁ , EO ₂ ECL output circuit FF ₁ flip-flop circuit ED ₁ ECL phase switching circuit EC ₁ , EC ₂ , EC ₃ ECL-CMOS level conversion circuit CE ₁ CMOS-ECL level conversion circuit CB ₁ , CB ₂ driver circuit CF ₁₀ , CF ₁₁ , CF ₁₂ CMOS flip-flop circuit L _{1 0} , L ₁₁ Arbitrary circuit C ₁₀ , C ₁₁ , C ₁₂ Internal circuit input terminal LSI ₁₀ Conventional semiconductor integrated circuit CI ₁₀ clock input terminal DI ₁₀ data input terminal CO ₁₀ clock output terminal DO ₁₀ data output terminal CK ₁₀ conventional Clock circuit system CB ₁₀ , CB ₁₁ , CB ₁₂ driver circuit ECI ₁ , ECI ₂ input circuit CEO ₁ , CEO ₂ output circuit

Claims (1)

(57) [Claims] 1. A circuit which is formed of a CMOS transistor and a bipolar transistor and inputs an ECL level clock, and a circuit which outputs an ECL level clock,
A circuit for inputting data synchronized with an input clock, a circuit for outputting data synchronized with an output clock, and a CMOS
Circuit and ECL for level conversion from ECL level to ECL level
A logic circuit having a circuit for converting a level from a CMOS level to a CMOS level and performing arbitrary data processing at the CMOS level;
A semiconductor integrated circuit having at least one synchronization circuit for synchronizing data with the clock, comprising: an ECL circuit for propagating and outputting the input clock while maintaining the ECL level; A circuit for synchronizing the phase of data after passing through a logic circuit that performs arbitrary data processing at the CMOS level with the input of an external signal in the synchronous circuit, and an input terminal for inputting the external signal A semiconductor integrated circuit comprising: