JPH09326689A - Clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce the clock signals which have less jitters against the fluctuation of power voltage caused by the power noises, etc., by controlling a delay circuit and a ring oscillator based on the output of a frequency comparator and a phase comparator. SOLUTION: A clock generation circuit consists of a phase comparator 1 which detects the phases of a reference clock signal CKin and a feedback clock signal CKf, a delay circuit 3 which includes 2n pieces of CMOS inverters concatenated together that can vary their delay times according to the control voltage VF generated by an LPF 2 in response to the phase difference detected by the comparator 1, a ring oscillator 4 which includes (n) pieces, i.e., the half of logic gate circuits which construct the circuit 3, and a frequency comparator 5 which compares the frequency of an oscillation signal CKV of the oscillator 4 and the signal CKin with each other. In such a constitution, the LPF 2 generates the voltage VF based on the output of both comparators 1 and 5 and controls the circuit 3 and the oscillator 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock forming technique in a semiconductor integrated circuit, and more particularly to a technique effective when applied to a semiconductor integrated circuit having a PLL (phase locked loop) circuit built therein as a clock generation circuit. The present invention relates to a clock generation circuit including a line type PLL circuit.

[0002]

2. Description of the Related Art In a clock synchronous logic LSI,
The basic clock signal supplied from the outside is distributed to the latch circuit (flip-flop) of each part in the LSI to perform operations such as decoding, memory read / write, and various operations. If the delay amount of the signal to the destination is different, the arrival timing of each clock signal is deviated (clock skew). If there is a clock skew, there is a risk that the latch circuit may take in an incorrect signal, or that the logic gate circuit may generate an unwanted whisker-like pulse at the output to cause the circuit to malfunction. Therefore, in the clock synchronous LSI, the magnitude of clock skew is a factor that determines the performance (operating speed) of the LSI. Further, such a clock synchronous logic LSI
In the system consisting of, it is important to eliminate clock skew in order to speed up signal transfer between LSI chips.

Therefore, in recent years, a PLL circuit has come to be used as a clock generation circuit. If a PLL circuit is used, a basic clock signal is input to one of its input terminals and the other input terminal (reference side)
By returning the clock signal input to the latch circuit at the end, the phase of the final clock signal can be matched with the phase of the basic clock signal, so that the clock skew can be reduced. As such a clock generation circuit, for example, a delay line type PLL
Techniques using circuits have been proposed (eg IEEE Jou
rnal of Solid-State Circuits, Vol.SC-23, No.5 (1988) p
p1218-1223).

[0004]

PROBLEM TO BE SOLVED BY THE INVENTION Delay line type PL
A clock generation circuit using an L circuit is composed of a negative feedback system composed of a phase comparator, a low-pass filter and a delay circuit, and the input reference clock signal is delayed by one cycle of the clock by the delay circuit to obtain a reference signal. A synchronous clock whose phase matches the clock is generated. However, in the conventional clock generation circuit using the delay line type PLL circuit, if the variable width of the delay time of the internal delay circuit is small, the delay time of one cycle may not be obtained,
In that case, the synchronous clock cannot be generated.

On the other hand, in order to prevent this, if the variable width of the delay time of the delay circuit is increased, the delay time may become twice or more the cycle of the reference clock. In that case, an integer of the cycle of the reference clock. Even when doubled, the phases match and P
A so-called pseudo synchronization in which the LL circuit is locked may occur. When such pseudo-synchronization occurs, the delay time fluctuation in the delay circuit due to power supply noise or the like becomes larger than that in the normal synchronization state, so that the phase fluctuation of the generated synchronization clock also becomes large and the jitter increases. There is. Further, in a system including a plurality of clock synchronization type LSIs, malfunction occurs when a normal synchronization clock is generated in one LSI but pseudo synchronization is generated in another LSI.

In addition, if the delay circuit in the delay line type PLL circuit is composed of a logic circuit such as a CMOS inverter whose output has a full amplitude up to the power supply voltage, the power supply voltage fluctuates due to power supply noise or the like. It was revealed that there was a problem that the delay time fluctuated at the same ratio as the above and the jitter increased.

An object of the present invention is to provide a delay line type PLL.
It is an object of the present invention to provide a clock generation circuit using a circuit in which pseudo synchronization does not occur.

Another object of the present invention is to provide a clock generation circuit capable of generating a clock signal with small jitter with respect to fluctuations in power supply voltage due to power supply noise or the like. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a delay line type PLL which includes a phase comparator, a low-pass filter and a delay circuit, and delays an input reference clock signal by the delay circuit to generate a synchronous clock whose phase matches that of the reference clock.
In a clock generation circuit using a circuit, the delay circuit is configured by cascading 2n logic gate circuits (n is a positive integer) whose delay time changes according to a control voltage from a low-pass filter, The frequency comparison is provided by providing a ring oscillator in which half the same number of logic gate circuits constituting the circuit are cascade-connected and a frequency comparator for comparing the frequency of the oscillation signal of the ring oscillator with the frequency of the reference clock signal. A control voltage is formed based on the output of the phase comparator and the output of the phase comparator to control the delay circuit and the ring oscillator.

Preferably, a transistor is interposed between the logic gate circuit and the power supply voltage terminal, and a control terminal of the transistor is a time constant circuit having a time constant larger than the response time of the PLL circuit. Is applied as a bias voltage.

According to the above means, since the number of gate stages of the ring oscillator is half the number of gate stages of the delay circuit, the oscillation period is the same as the delay time of the delay circuit. Therefore, the delay time in the delay circuit is equal to the reference clock. Even if the phase comparator outputs a coincidence signal in the state of an integer multiple of two or more of the cycle, the frequency comparator outputs a signal that the oscillation frequency of the ring oscillator is smaller, so the delay time of the delay circuit is small. The PLL circuit locks only when the generated synchronization clock signal is delayed by exactly one cycle from the reference clock, and pseudo synchronization does not occur.

Further, according to the above means, a transistor is interposed between the logic gate circuit forming the ring oscillator and the power supply voltage terminal, and the control terminal of the transistor is longer than the response time of the PLL circuit. Since the time constant circuit having a constant is configured to apply the voltage smoothed from the power supply voltage as the bias voltage, the bias voltage supplied to the control terminal of the above-mentioned transistor changes very slowly even if the power supply voltage changes. It will be Moreover, since the time constant of the time constant circuit that generates this bias voltage is set so as to be slower than the response speed of the PLL circuit, the operation of the PLL circuit is the same as that of the bias voltage that is not changing. The output amplitude of the logic gate circuit does not change even if the power supply voltage changes. As a result, even if the power supply voltage fluctuates due to power supply noise or the like, the delay time of the delay circuit does not fluctuate, the phase fluctuation of the generated synchronous clock signal disappears, and the jitter is reduced.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a delay line type PL according to the present invention.
It is a block diagram which shows one Example of L circuit. Although not particularly limited, the circuit elements forming each block in the figure are formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The PLL circuit of this embodiment has a reference clock signal CKin and a feedback clock signal CK input from the outside.
The phase comparator 1 for detecting the phase difference of f, the low-pass filter (LPF) 2 for generating the control voltage VF according to the detected phase difference, and the 2n CMOS inverters are cascade-connected to each other. A delay circuit 3 whose delay time is variable according to a control voltage VF; a ring oscillator 4 in which n half of CMOS inverters having the same structure as the logic gate circuit forming the delay circuit 3 are cascade-connected;
It comprises a frequency comparator 5 for comparing the frequencies of the oscillation signal CKV of the ring oscillator 4 and the reference clock signal CKin, and the low pass filter 2 is controlled based on the output of the frequency comparator 5 and the output of the phase comparator 1. The voltage VF is formed to control the delay circuit 3 and the ring oscillator 4.

The synchronous clock signal CLK output from the delay circuit 3 is fed back to the phase comparator 1 as a feedback clock CKf, and is constructed in a tree shape in which the H-shaped branches are sequentially branched toward the end circuit in the LSI. LS via a clock distribution system consisting of
I is distributed to the flip-flop circuits of each part.

Here, the number of stages of the ring oscillator 4 (CM
The number of OS inverters: n is the number of stages of the delay circuit 3 (CMO).
The reason why the number of S inverters is 1/2 of 2n) is shown in FIG.
Also, a brief description will be given with reference to FIG.

First, as shown in FIG. 12A, when a ring oscillator in which n stages of inverters each having a delay time τ are cascade-connected, the ring oscillator changes the input waveform of each stage. Is transmitted to the next stage with a delay of τ, the inverted output waveform of the final stage is fed back to the first stage after a delay time of 3τ in the third stage and nτ in the n stage.
As shown in FIG. 2B, it is understood that the oscillation period T of this ring oscillator is 2nτ.

As shown in FIG. 13, in the conventional PLL circuit, the feedback clock CKf (synchronous clock CKL)
Control is performed only so as to phase lock with the reference clock CKin, so even if the delay time of the feedback clock CKf (PLL synchronization clock CKL) is twice or more the reference clock CKin, phase lock is established between the two. Is considered to occur, so-called pseudo synchronization occurs (see FIG. 13).
See).

On the other hand, when the ring oscillator 4 and the frequency comparator 5 are provided as in this embodiment of FIG. 1, the frequency of the oscillation signal CKV of the ring oscillator 4 ( The cycle is controlled to be equal to the frequency (cycle) of the reference clock CKin, and the cycle of the oscillation signal CKV of the ring oscillator 4, that is, the delay time of the PLL feedback clock CKf (PLL synchronization clock CKL) is made equal to one cycle of the reference clock CKin. , False synchronization is prevented (see FIG. 14). Therefore,
Number of stages of ring oscillator 4 (Number of CMOS inverters:
n) is the number of stages of the delay circuit 3 (the number of CMOS inverters: 2)
The half of n) prevents the occurrence of pseudo synchronization, and the PLL circuit is locked only when the feedback clock CKf (synchronization clock CKL) is delayed from the reference clock CKin by one cycle.

Although not particularly limited, in this embodiment, the frequency of the synchronous clock signal CLK output from the clock generating circuit composed of the PLL circuit is the same as the frequency of the reference clock CKin input from the outside. If the frequency of the generated synchronous clock signal CLK is N times the frequency of the reference clock CKin, the delay circuit 3
A frequency divider circuit may be provided in the subsequent stage, and a clock divided by 1 / N by this frequency divider circuit may be supplied to the phase comparator 1 as the feedback clock CKf.

Further, a pulse generating circuit 6 for generating a one-shot pulse having a pulse width smaller than that of the reference clock CKin is provided, and the pulse PLS from the pulse generating circuit 6 is supplied to the low pass filter 2 and delayed. It may be arranged to generate a control voltage VF for controlling the circuit 3.

FIG. 2 shows a concrete circuit configuration example of the phase comparator 1.

As shown in FIG. 2, the phase comparator 1 of this embodiment has a reference clock CK input from the outside.
The flip-flop FF1 receives in as the data terminal D and the feedback clock CKf from the delay circuit 3 as the clock terminal CK, the reference clock CKin as the clock terminal CK, and the feedback clock CKf from the delay circuit 3 as the data terminal D. Flip-flop FF2
And an AND gate circuit G1 which receives the output Q of the flip-flop FF1 and the inverted output / Q of FF2 at its input terminals.
And an AND gate circuit G2 which receives the inverted output / Q of FF1 and the output Q of FF2 at its input terminals.

The phase comparator 1 of this embodiment is shown in FIG.
If the phase of the feedback clock CKf lags the phase of the reference clock CKin, the output Q of the flip-flop FF1 is set to the high level as shown in FIG.
The output EPup of the D gate G1 becomes high level. Also,
As shown in FIG. 3B, the reference clock CKin
If the phase of the feedback clock CKf is ahead of the phase of, the output Q of the flip-flop FF2 is set to high level, and the output EPdown of the AND gate G2 becomes high level.

On the other hand, when the phase of the reference clock CKin and the phase of the feedback clock CKf match, both flip-flops FF1 and FF2 become indefinite, but since they are the logical product of two flip-flops, FF1 When both FF2 latch high level or both FF1 and FF2 latch low level, AND gate G1
Output EPup of G2 and output EPdown of G2 become low level.

FIG. 4 shows a specific circuit configuration example of the frequency comparator 5.

The frequency comparator 5 of this embodiment calculates the logical product of the outputs of these flip-flops FF11 and FF12, and the flip-flops FF11 and FF12 connected so that their inverted outputs are input to the data terminals. The AND gate circuit G11, four flip-flops FF13 to FF16 connected in cascade, and output flip-flops FF17 and FF18 for latching the outputs of FF15 and FF16 among these flip-flops.

The reference clock CKin is input to the clock terminal CK of the flip-flop FF11, and the output of the flip-flop FF11 is flip-flop FF12.
Is input to the clock terminal CK. As a result, the outputs a and b of the flip-flops FF11 and FF12 become a clock having a cycle twice that of the reference clock CKin and b a clock having a cycle twice that of a, as shown in FIG. That is, the flip-flops FF11 and FF12 operate as a frequency dividing circuit that divides the reference clock CKin by four. It should be noted that this frequency division ratio is one example, and may be three or five or more.

On the other hand, the data terminal D of the flip-flop FF13 is connected to the power supply voltage Vcc, and FF13 to F
The oscillation signal CKV from the ring oscillator 4 is commonly input to the clock terminal CK of F16. As a result, the flip-flops FF13 to FF16 operate as shift registers that sequentially propagate the high level from the FF13 to the FF16 in synchronization with the rise of the oscillation signal CKV. Furthermore, these flip-flops FF1
FF11, FF1 are connected to the reset terminals R of 3 to FF16.
The output of the AND gate circuit G11 that takes the logical product of the outputs of 2 is input, and the outputs of the AND gate circuit G11 reset the FF13 to FF16 at the same time.

Further, the flip-flops FF17 and F
The flip-flop FF16 is connected to the data terminal D of F18.
And the output of FF15 is input respectively,
The output b of the FF12 is input to the clock terminals CK of the FF17 and FF18, and the flip-flop FF1 is synchronized with the rising of the output b of the flip-flop FF12.
7 is the output of the flip-flop FF16, and FF18
Is configured to latch the output of FF15.
The output Q of the flip-flop FF17 serves as a signal EFdown indicating that the frequency of the oscillation signal CKV is higher than the reference clock CKin (the periods T0 and Tf of the two clocks are T0 <Tv).
The inverted output / Q of F18 is output to the low-pass filter 2 as a signal EFup indicating that the frequency of the oscillation signal CKV is lower than the reference clock CKin (T0> Tv).

The operation of the frequency comparator 5 will be described with reference to FIG.

The frequency comparator 5 of this embodiment uses the first cycle T1 as the four cycles of the reference clock CKin as one cycle.
Then, the shift register is reset (the outputs of the flip-flops FF13 to FF16 are “L”), and the reference clock CKin and the oscillation are generated by determining how many stages of “H” (high level) propagate during the remaining three cycles. The magnitude of the frequency of the signal CKV is detected.

That is, when the frequencies of the reference clock CKin and the oscillation signal CKV match, as shown by the solid line in FIG. 5, the oscillation signal CKV is between the second period and the fourth period of the reference clock CKin. Has three rising edges (here, for convenience, description will be made assuming that two clocks are out of phase with each other), and thus "H" propagates to the third stage (FF15) in the shift register including FF13 to FF16 ( Outputs c to e of each stage). Then, at the timing t2 when the next cycle starts, the AND gate circuit G11
Of the shift register, that is, flip-flops FF13 to FF16.
Is reset. That is, when the frequencies of the reference clock CKin and the oscillation signal CKV match, "H" propagates to the third stage (FF15) in the shift register, and the output f of the fourth stage (FF16) is "L". Will remain. Therefore, the output Q of the flip-flop FF17 indicating that the frequency of the oscillation signal CKV is higher than the reference clock CKin.
(EFdown) is also a flip-flop FF1 indicating that the frequency of the oscillation signal CKV is lower than the reference clock CKin.
The inverted output / Q (EFup) of 8 also becomes low level.

Next, when the frequency of the oscillation signal CKV is higher than the frequency of the reference clock CKin (cycle T0> Tv)
5, the oscillation signal CKV rises before the start timing t2 of the next cycle, and in synchronization with this, the output signal f of the flip-flop FF16 rises as shown by the dotted line. That is, "H" is propagated up to the fourth stage in the shift register. Therefore, the output Q (EFdown) of the flip-flop FF17 indicating that the frequency of the oscillation signal CKV is higher than the reference clock CKin.
Changes to the high level at the timing t2.
At this time, since the flip-flop FF18 takes in the output e of the flip-flop FF15 which has changed to the high level at the rising edge of one cycle before t2, the oscillation signal CKV
The inverted output / Q (EFup) indicating that the frequency of is lower than the reference clock CKin becomes low level.

On the other hand, when the frequency of the oscillation signal CKV is lower than the frequency of the reference clock CKin (cycle T0 <Tv)
As shown by the arrow A in FIG.
The second rising edge comes after the start timing t2 of the next cycle. By this, the flip-flop FF
The next cycle starts before the output signal e of 15 rises, that is, the shift register including FF13 to FF16 propagates "H" only up to the second stage. Therefore, the inverted output / Q (EFup) of the flip-flop FF18 that takes in the output e of the FF15 changes to a high level indicating that the frequency of the oscillation signal CKV is lower than the reference clock CKin at the timing t2.
At this time, the flip-flop FF17 has the timing t.
Output of the flip-flop FF16 at 2 (low level)
Is taken in, the output Q (EFdown) indicating that the frequency of the oscillation signal CKV is higher than the reference clock CKin becomes low level.

The frequency comparator of this embodiment outputs a matching signal (both EFdown and EFup are low level) even when the frequencies do not match due to the phase difference between the reference clock CKin and the oscillation signal CKV. However, in such a case, the above-mentioned phase comparator 1 detects the phase difference and outputs a mismatch signal (EFdown or EFup). Therefore, the clock generating circuit as a whole can operate effectively.

FIG. 6 shows a specific circuit configuration example of the low-pass filter 2.

The low-pass filter 2 of this embodiment has a pair of constant current sources I1 and I2 and a pair of switch MOSFETs connected in series between the power supply voltage Vcc and the ground point.
A charge pump 21 composed of S1 and S2, a capacitance CF charged and discharged by the charge pump 21, phase mismatch signals EPup, EPdown from the phase comparator 1 and a frequency mismatch signal EFup from the frequency comparator 5,
The control circuit 22 forms a signal for controlling the charge pump 21 based on EFdown.

In the control circuit 22, the signal EPup indicating the phase delay of the feedback clock CKf from the phase comparator 1 is supplied to one input terminal, and the other input terminal receives the frequency mismatch (high level) from the frequency comparator 5. ) An AND gate circuit G21 supplied with a signal obtained by inverting the signal EFdown by the inverter IV1 and the feedback clock CK from the phase comparator 1
An AND gate circuit in which a signal EPdown indicating the phase advance of f is supplied to one input terminal and a signal obtained by inverting the frequency mismatch (low) signal EFup from the frequency comparator 5 by the inverter IV2 is supplied to the other input terminal. G22 and an OR gate circuit G23 in which the output signal of the AND gate circuit G21 is supplied to one input terminal and the frequency mismatch (low) signal EFup from the frequency comparator 5 is supplied to the other input terminal, and An output signal of the AND gate circuit G22 is supplied to one input terminal, and an OR gate circuit G24 to which the frequency mismatch (high) signal EFdown from the frequency comparator 5 is supplied to the other input terminal, and the OR gate circuit G23. Gate signal G to which the output signal of 1 and the one-shot pulse PLS from the pulse generation circuit 6 are input.
25 and an AND gate circuit G26 to which the output signal of the OR gate circuit G24 and the one-shot pulse PLS from the pulse generation circuit 6 are input.

In the low-pass filter 2 of this embodiment, when the signal EPup indicating the phase delay of the feedback clock CKf from the phase comparator 1 is at high level, or the frequency mismatch (low) signal EFup from the frequency comparator 5 is received. At the high level, the output of the OR gate circuit G23 of the control circuit 22 becomes the high level, and the output of the NAND gate circuit G25 becomes the low level according to the period when the one-shot pulse PLS is at the high level. As a result, switch MOSFE
The T (P-channel type) S1 is turned on to inject charges into the capacitor CF by the current from the constant current source I1 to increase the voltage VF.

On the other hand, the feedback clock C from the phase comparator 1
When the signal EPdown indicating the phase advance of Kf is at high level, or when the frequency mismatch (high) signal EFdown from the frequency comparator 5 is at high level, the output of the OR gate circuit G24 becomes high level and the one-shot pulse The output of the AND gate circuit G26 becomes high level according to the period when PLS is high level. As a result, the switch MOSFET (N-channel type) S2 is turned on, and the electric current of the constant current source I2 extracts the electric charge of the capacitor CF to lower the voltage VF.

Moreover, the low-pass filter of this embodiment is provided with the inverters INV1 and INV2 and AND gate circuits G21 and G22, and the frequency mismatch (low) signal EFup and the frequency mismatch (high) signal EFdown from the frequency comparator 5 are provided. Signal E indicating the phase delay of the feedback clock CKf from the phase comparator 1 only when is low level
Pup or signal E indicating the phase lead of feedback clock CKf
When Pdown becomes high level, switch MOSFET
S1 is turned on to inject charges into the capacitor CF to increase the voltage VF, or the switch MOSFET S2 is turned on to extract charges from the capacitor CF to decrease the voltage VF. That is, the low-pass filter 2 of this embodiment operates with priority on the frequency mismatch signals EFup and EFdown, and the signal indicating the phase delay or the phase lead becomes effective only when the frequencies match, so that the PLL is quasi-synchronized. It is possible to avoid locking the circuit.

In this embodiment, the NAND gate circuit G25 and the AND gate circuit G26 are provided so that the charge pump 21 can be charged and discharged using the one-shot pulse PLS as an enable signal.
NAND gate circuit G25 and AND gate circuit G2
6 can also be omitted. However, in that case, O
The output of the R gate circuit G24 is directly the switch MOSF.
Although it may be supplied to the gate terminal of ET S2, the NOR gate circuit G23 is replaced with a NOR gate circuit and the NO
A device such as supplying the output of the R gate circuit to the gate terminal of the switch MOSFET S1 is required.

If the NAND gate circuit G25 and the AND gate circuit G26 are provided and the one-shot pulse PLS is used as the enable signal to perform the charging / discharging operation of the charge pump 21 as in the present embodiment, the charge pump 21 is charged. The charge / discharge charge amount per cycle of 21 can be adjusted not by adjusting the currents of the constant current sources I1 and I2, but by adjusting the pulse width of the one-shot pulse PLS, which is advantageous in designing.

FIG. 7 shows an example of the pulse generation circuit 6.

The pulse generating circuit 6 has a reference clock C.
A delay circuit 61 including an odd number of inverter trains for delaying Kin, and a reference clock CKin is input to one terminal and the reference clock CKin is input to the other terminal.
AND gate circuit 6 to which the signal CK 'delayed by is input
2, and a pulse having a width corresponding to the delay time tpd of the delay circuit 61 is formed and output as shown in FIG.

FIG. 9 shows a specific circuit configuration example of the ring oscillator 4. In the ring oscillator of this embodiment, n CMOS inverters G1 to Gn are connected in cascade and each CMOS inverter G1 is connected.
~ Pn-type current control MOSFET Q11 between Gn P-channel MOSFET and power supply voltage Vcc ~
Q1n and N-channel type current control MOSFETs Q21 to Q2n are connected between the N-channel MOSFETs of the CMOS inverters G1 to Gn and the ground point.
Further, between the power supply voltage Vcc and the ground point, a MOSFET Q1 having a gate terminal to which a control voltage VF from the low-pass filter 2 is applied, a diode-connected MOSFET Q2 connected in series with the MOSFET Q1, and
M which constitutes a current mirror circuit with the MOSFET Q2 and the MOSFETs for current control Q21 to Q2n
A bias voltage generating circuit is provided which includes an OSFET Q3 and a MOSFET Q4 which is connected in series with the MOSFET Q3 and constitutes a current mirror circuit together with the current controlling MOSFETs Q11 to Q1n.

In the ring oscillator 4 of this embodiment, when the control voltage VF supplied from the low pass filter 2 becomes high, the current of the MOSFET Q1 increases, and the current controlling MOSFETs Q11 to Q11 via the current mirror circuit.
The currents flowing through 1n and Q21 to Q2n are increased, and the time required to charge and discharge the parasitic capacitance existing at the output nodes of the CMOS inverters G1 to Gn, that is, the gate delay time is reduced.

As a result, the oscillation frequency becomes high. on the other hand,
When the control voltage VF supplied from the low pass filter 2 becomes low, the current of the MOSFET Q1 decreases, and the current controlling MOSFET Q11 passes through the current mirror circuit.
~ Q1n and Q21 ~ Q2n current is also reduced, each CMO
The time required to charge and discharge the parasitic capacitance existing at the output nodes of the S inverters G1 to Gn, that is, the gate delay time is increased. As a result, the oscillation frequency becomes low.

The delay circuit 3 also has the same structure as the ring oscillator shown in FIG. The only difference is that the number of cascaded CMOS inverters is 2n, which is twice the number of CMOS inverters forming a ring oscillator, and the output of the final stage inverter is not fed back to the first stage inverter.

FIG. 11 shows a delay line type P of the present invention.
A second embodiment of the clock generation circuit using the LL circuit is shown. The clock generating circuit of this embodiment differs from the first embodiment in the following two points.

First, the delay circuit 3 includes a variable delay circuit 31 composed of 2n gate circuits whose delay time is changed by the control voltage VF from the low pass filter 2, and a plurality of delay circuits whose delay time is not changed by the control voltage. And a fixed delay circuit 32 composed of the gate circuit of FIG. 3 and the ring oscillator 4 has a variable delay circuit 41 having the same configuration as the variable delay circuit 31 and having n gate circuits with half the number of stages of the gate circuit. And the fixed delay circuit 42 having the same configuration as the fixed delay circuit 32 and the number of stages of the gate circuit is half, that is, the delay time is TD / 2 which is half the delay time TD of the fixed delay circuit 32. . Even in the case of such a configuration, the oscillation cycle of the ring oscillator 4 matches the delay time of the delay circuit 3.

With the above configuration, the ratio of the variable delay amount to the delay time of the delay circuit 3 as a whole is
It can be set by the ratio of the number of gate stages of the variable delay circuit 31 and the number of gate stages of the fixed delay circuit 32.

The reference clock C supplied from the outside
When Kin is configured to be input to the phase comparator 1 and the delay circuit 3 via the buffer BFF, the delay time TD of the fixed delay circuit 32 is designed to be the same as the delay time of the buffer BFF. By doing so, there is an advantage that the generated synchronous clock can be matched with the phase of the reference clock applied to the input pin IN. However, in this case, the clock CLK supplied to the inside of the LSI
Is taken out from the gate circuit at the final stage of the variable delay circuit 31.

The second difference between the second embodiment and the first embodiment is that, as shown in FIG. 10, the gate circuit which constitutes the ring oscillator 4 and the delay circuit 3 includes a CMOS inverter Gi and a CMOS inverter Gi. A bipolar transistor TRi connected between the PMOS side and the power supply voltage Vcc and having a bias voltage Vb applied to the base, and a CMOS
A current control MOSF composed of an N-channel MOSFET connected between the NMOS side of the inverter and the ground point and having the gate to which the control voltage VF from the low pass filter 2 is applied.
ET Qi and the bias voltage Vb is composed of a resistor R1 and a capacitor C1 and is a power supply voltage Vc.
This is a point generated by the smoothing circuit 7 for smoothing c. The time constant of the smoothing circuit 7 is set larger than the response time of the PLL circuit.

The delay circuit 3 and the ring oscillator 4 using the gate circuit of FIG.
The gate terminal of the MOSFET Qi connected to the NMOS side of is controlled by the control voltage VF from the low pass filter 2 to control the current flowing through the CMOS inverter Gi and change the delay time.

Further, in this embodiment, the upper limit of the amplitude of the CMOS inverter Gi is the bias voltage V from the smoothing circuit 7.
Due to the cascode transistor TRi biased by b, the base voltage Vb becomes a voltage (Vb-VBE) lower than the base voltage Vb by the base-emitter voltage Vb, but the bias voltage Vb has a time constant longer than the response time of the PLL circuit. The bias voltage Vb does not fluctuate in the operation of the PLL since it is configured to be supplied from the smoothing circuit 7 which is set to a large value. That is, the gate circuit Gi that constitutes the delay circuit 3 and the ring oscillator 4
Is the same as the output amplitude does not fluctuate even if the power supply voltage Vcc fluctuates, and the delay time of the delay circuit 3 and the ring oscillator 4 does not fluctuate depending on the fluctuation of the power supply voltage. As a result, the phase of the generated clock CKf is not changed by the fluctuation of the power supply voltage, and jitter is less likely to occur.

In the gate circuit which constitutes the delay circuit 3 and the ring oscillator 4 of the above embodiment, CM is used.
Although a bipolar transistor is used as the cascode type transistor TRi connected to the PMOS side of the OS inverter, a MOS is used instead of the bipolar transistor.
You may make it use FET. In the embodiment, the cascode type transistor TR is provided for each CMOS inverter.
Although i is connected, these transistors may be commonly used. Alternatively, the cascode type transistors TRi may be configured so that their emitters or sources are coupled to each other. By this, each C
There is an advantage that the variation of the signal amplitude of the MOS inverter can be reduced.

As described above, the above embodiment is provided with the phase comparator, the low-pass filter and the delay circuit, and the input reference clock signal is delayed by the delay circuit to generate a synchronous clock whose phase matches that of the reference clock. In a clock generation circuit using a delay line type PLL circuit, the delay circuit is configured by cascading 2n logic gate circuits whose delay time changes according to the control voltage, and the logic configuring the delay circuit. A ring oscillator in which half the same number of logic gate circuits as the gate circuit are cascade-connected and a frequency comparator for comparing the frequency of the oscillation signal of the ring oscillator and the frequency of the reference clock signal are provided, and the output of the frequency comparator and the above A control voltage is generated based on the output of the phase comparator to control the delay circuit and ring oscillator. Since the number of gate stages of the ring oscillator is half the number of gate stages of the delay circuit, the oscillation cycle is the same as the delay circuit and the delay time in the delay circuit is more than twice the reference clock cycle. Even if the phase comparator outputs a coincidence signal in the state of being an integral multiple, the frequency comparator outputs a signal that the oscillation frequency of the ring oscillator is smaller, so the delay time of the delay circuit is controlled to be small, There is an effect that the PLL circuit locks only when the generated synchronization clock signal is delayed by exactly one cycle from the reference clock, and pseudo synchronization does not occur.

Further, a transistor is interposed between the logic gate circuit forming the ring oscillator and the power supply voltage terminal, and the control terminal of the transistor is a time constant circuit having a time constant larger than the response time of the PLL circuit. Since the voltage smoothed from the power supply voltage is applied as the bias voltage, the fluctuation of the bias voltage supplied to the control terminal of the transistor is very gentle even if the power supply voltage changes. Moreover, since the time constant of the time constant circuit that generates this bias voltage is set so as to be slower than the response speed of the PLL circuit, the operation of the PLL circuit is the same as that of the bias voltage that is not changing. The output amplitude of the logic gate circuit does not change even if the power supply voltage changes. As a result, the delay time of the delay circuit does not change even if the power supply voltage changes due to power supply noise, etc.
There is an effect that the phase fluctuation of the generated synchronous clock signal is also eliminated and the jitter is reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and for example, a CMOS inverter is used as a gate circuit constituting the delay circuit 3 or the ring oscillator 4. Alternatively, a NOR gate or the like may be used.

Further, the number of logic gate circuits forming the ring oscillator is not limited to half the number of logic gate circuit stages of the delay circuit, and can be set to an arbitrary number by changing the comparison ratio of the frequency comparator. it can. That is, when the ring oscillator is set to 1/4 of the number of delay circuit stages, the frequency comparator compares the frequency twice the reference clock with the oscillation frequency of the ring oscillator, and the ring oscillator is set to the number of delay circuit stages. If it is the same, the frequency comparator compares the half frequency of the reference clock with the oscillation frequency of the ring oscillator. Therefore, when the number of logic gate circuit stages of the delay circuit and the ring oscillator is (x), the frequency ratio (y) for comparison between the reference clock frequency and the ring oscillator oscillation frequency in the frequency comparator.
Should be set to x / 2.

In the above description, the invention made by the present inventor has been mainly applied to a semiconductor integrated circuit having a built-in clock generating circuit composed of a delay line type PLL circuit, which is the field of application of the invention. The present invention is an L which incorporates a delay line type PLL circuit.
SI is generally available.

[0066]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to realize a clock generation circuit using a delay line type PLL circuit, in which pseudo synchronization does not occur. Further, it is possible to realize a clock generation circuit that can generate a clock signal with small jitter with respect to fluctuations in the power supply voltage due to power supply noise or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock generation circuit using a delay line type PLL circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a specific circuit of a phase comparator.

FIG. 3 is a time chart showing the timing of signals in the phase comparator.

FIG. 4 is a circuit diagram showing a configuration example of a specific circuit of a frequency comparator.

FIG. 5 is a time chart showing the timing of signals in the frequency comparator.

FIG. 6 is a circuit diagram showing a configuration example of a specific circuit of a low-pass filter.

FIG. 7 is a circuit diagram showing a configuration example of a specific circuit of a pulse generation circuit.

FIG. 8 is a time chart showing the timing of signals in the pulse generation circuit.

FIG. 9 is a circuit diagram showing a configuration example of a specific circuit of a ring oscillator.

FIG. 10 is a circuit diagram showing a specific configuration example of a gate circuit that constitutes a delay circuit and a ring oscillator.

FIG. 11 is a block diagram showing a second embodiment of a clock generation circuit using a delay line type PLL circuit according to the present invention.

FIG. 12 is a time chart showing the operation of the ring oscillator.

FIG. 13 is a time chart showing waveforms of a reference clock and a feedback clock in a pseudo lock state in a conventional PLL circuit.

FIG. 14 is a time chart showing waveforms of a reference clock and a feedback clock in a locked state in the PLL circuit according to the present invention.

[Explanation of symbols]

 1 Phase Comparator 2 Low Pass Filter 3 Delay Circuit 4 Ring Oscillator 5 Frequency Comparator 6 Pulse Generation Circuit 7 Smoothing Circuit

Claims (8)

[Claims] 1. A delay line type PLL circuit comprising a phase comparator, a low-pass filter, and a delay circuit, wherein a delay circuit delays an input reference clock signal to generate a synchronous clock whose phase matches that of the reference clock. In the clock generation circuit, the delay circuit is formed by cascading 2n logic gate circuits whose delay time changes according to the control voltage from the low pass filter, and is the same as the logic gate circuit forming the delay circuit. A ring oscillator in which half the number n of logic gate circuits having the above-mentioned configuration are connected in cascade and a frequency comparator for comparing the frequencies of the oscillation signal of the ring oscillator and the reference clock signal are provided, and the output of the frequency comparator and the phase comparator are provided. A control voltage is formed based on the output of the delay circuit and the ring oscillator to control the delay circuit and the ring oscillator. A clock generation circuit characterized by being made. 2. A transistor is interposed between the logic gate circuit and the power supply voltage terminal, and the power supply voltage is supplied to the control terminal of the transistor by a time constant circuit having a time constant larger than the response time of the PLL circuit. The clock generation circuit according to claim 1, wherein a smoothed voltage is applied. 3. A current control circuit configured to form a current mirror circuit with a transistor through which a current corresponding to the control voltage from the low pass filter flows between the logic gate circuit and a power supply voltage terminal or a ground point. 3. A transistor according to claim 1, wherein a transistor is interposed.
The clock generation circuit described in 1. 4. The delay circuit and the ring oscillator are each composed of a variable delay circuit including a logic gate circuit having a variable delay time and a fixed delay circuit having a fixed delay time. The clock generation circuit described in 1, 2, or 3. 5. When the reference clock signal supplied from the outside is configured to be input to the phase comparator and the delay circuit via a buffer circuit, the delay time of the fixed delay circuit is the buffer circuit. 2. The delay time is set to be the same as the delay time of.
The clock generation circuit described in 2, 3 or 4. 6. The frequency comparator comprises a frequency dividing circuit for dividing the reference clock into 1 / N, and a shift register composed of N flip-flop circuits for performing a shift operation using an oscillation signal of the ring oscillator as a clock. A latch circuit for latching the output of the final stage of the shift register and the flip-flop circuit one stage before the final stage by the output signal of the frequency dividing circuit. The clock generation circuit according to 3, 4, or 5. 7. The low-pass filter is controlled by a phase comparison output signal of the phase comparator and a frequency comparison output signal of the frequency comparator, the low-pass filter being higher than the phase comparison output signal of the phase comparator. When the frequency of the frequency comparison output signal of the frequency comparator is prioritized and the frequencies of the ring oscillator and the reference clock are substantially equal, the delay circuit and the ring oscillator are controlled by the phase comparison output signal of the phase comparator. 7. The clock generation circuit according to claim 1, which is controlled. 8. The clock generating circuit according to claim 1, and a clock distribution system for distributing and supplying a clock generated by the clock generating circuit to desired portions of a semiconductor integrated circuit. Semiconductor integrated circuit.