JP4724670B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to an analog circuit device that requires a stable constant current source.

  2. Description of the Related Art In recent years, semiconductor integrated circuit devices are required to have higher speed and constant power consumption, and lower power supply voltage and smaller signal amplitude have been promoted. This is a MOS (Metal-Oxide-Semiconductor) or more widely a semiconductor integrated circuit device composed of MIS (Metal-Insulator-Semiconductor) transistors, that is, a CMOS (Complementary MOS) circuit that requires a stable constant current source. The same applies to the constructed analog circuit device, and therefore there is a demand for a semiconductor integrated circuit device capable of generating a stable constant current even with a low power supply voltage.

  Further, a semiconductor integrated circuit device having a small signal amplitude at a recent low power supply voltage (for example, 1.8 V, 1.2 V or less) and a conventional high power supply voltage (for example, 3.3 V or 2.5 V). There is also a need to provide a level shift circuit capable of high-speed operation capable of interfacing with a semiconductor integrated circuit device having a large signal amplitude.

  Conventionally, the basic idea of a current source circuit is to generate a stable current without depending on power supply voltage, process, and temperature.

  FIG. 1 is a circuit diagram showing an example of a conventional semiconductor integrated circuit device, and shows an example of a current source circuit independent of a power source. In FIG. 1, reference numeral Vdd is a high potential power supply line (high potential power supply voltage), Vss is a low potential power supply line (low potential power supply voltage), 101 to 103 are p-channel MOS transistors (pMOS transistors), and 104 and 105 are An n-channel MOS transistor (nMOS transistor) and 106 indicate resistors.

The circuit shown in FIG. 1 is considered as an ideal current source, the resistance value of the resistor 106 is R, and the low potential power supply voltage Vss = 0V. First, since the transistors 101 and 102 are connected in a current mirror, I01 = I02 holds. The gate of the transistor 104 - source voltage Vgs01, the current amplification factor and beta _01, the gate of the transistor 105 - source voltage Vgs02, the current amplification factor and Kbeta _01, and the threshold of the transistors 104 and 105 When the voltage Vth equal, the current I01 flowing through the transistor _{104, 01 = β 01 (Vgs01-} Vth) 2/2 , and the addition, the current I02 flowing through the transistor _{105, I02 = Kβ 01 (Vgs02-} Vth) 2 / 2. Further, Vgs01 = Vgs02 + I02 · R is established.

From these equations, clearing the threshold voltage Vth, current flowing through the transistor 102 and the current mirror connected transistor 103 Iout is, Iout = I01 = I02 = 2 / β1 · 1 / R 2 · (1-1 / √K) ² , and since the power supply voltage is not included in the equation, it can be said that the circuit does not depend on the power supply voltage. As in the case of the transistor 105, a current copy similar to the current Iout can be generated as necessary by connecting each transistor to the transistor 102 in a current mirror connection.

FIG. 2 is a diagram schematically showing the Vds-Ids characteristic of the transistor.
However, for example, there is a characteristic as shown in FIG. 2 between the source-drain voltage Vds and the drain current (source-drain current) Ids of the transistor, and the slope is actually even in the saturation region. Therefore, when the power supply voltage (Vdd) increases, the source-drain voltage Vds of the transistors 101 and 102 also increases and the current increases. When the power supply voltage decreases, the source-drain voltage Vds of the transistors 101 and 102 increases. May decrease and current may decrease, or may enter a linear region.

  Therefore, the voltage drop in the transistors 104 and 105 changes, and the value differs between the voltage V01 at the node N01 and the voltage V02 at the node N02. In view of this, when considering the current value from the resistance component Rds between the source and drain of the transistor 105, I02 = I01 + (V02−V01) / Rds. Furthermore, an error may be caused by a mismatch of the threshold voltage Vth of the transistor or the current amplification factor β.

  In other words, the conventional current source circuit shown in FIG. 1 does not actually have a possibility of depending on the power supply voltage, and it is considered that the temperature dependence and process dependence are large. Furthermore, conventionally, when a certain level of power supply voltage can be secured, the accuracy of the current source can be improved by vertically stacking the transistors. However, in recent years, transistor miniaturization and operation speed have been reduced. With the demand for higher speed, the power supply voltage has also been lowered, and it has become impossible to cope with the conventional method. In addition, the slope of the saturation region in the current characteristics is increased, making it more difficult to design a stable current source. In addition, current sources have become essential even in amplifiers that can receive high frequencies, and if the current value is not stable, problems such as making it difficult for the amplifier output to produce the intended frequency also occur. ing.

  By the way, the input signal currently determined by the standard is often set higher than the power supply voltage which has been lowered recently. To cope with this, two types of power supply voltages (Vdd1: high high-potential power supply voltage; for example, 3.3V and 2.5V, and Vdd2: low high-potential power supply voltage; for example, 1.8V and 1.2V) The differential input signal (IN, / IN) is received by the pMOS and nMOS differential pair transistors.

  FIG. 3 is a circuit diagram showing another example of a conventional semiconductor integrated circuit device, and shows a conventional differential amplifier having a level shift function. In FIG. 3, reference numeral 200 denotes a differential amplifier, 250 denotes a level shift unit, 201 to 210 denote pMOS transistors, 211 to 218 denote nMOS transistors, and 219 denotes an inverter. Reference numeral Vdd1 is a high high-potential power supply voltage (for example, 3.3V or 2.5V), Vdd2 is a low high-potential power supply voltage (for example, 1.8V or 1.2V), and Vss is a low-potential power supply voltage. (For example, 0V). The pMOS transistors 201 to 209 and the nMOS transistors 211 to 217 are high voltage MOS transistors, and the pMOS transistor 210 and the nMOS transistor 218 are low voltage MOS transistors.

  That is, as shown in FIG. 3, in the conventional semiconductor integrated circuit device (differential amplifier having a level shift function), a high potential power supply voltage Vdd1 is applied and pMOS transistors 201 to 207 and nMOS transistors 211 to 215 are connected. And a level shift unit 250 having pMOS transistors 208 to 210, nMOS transistors 216 to 218, and an inverter 219, to which a low high potential power supply voltage Vdd2 is applied.

  The differential input signals IN and / IN are supplied to the pMOS differential pair transistors 206 and 207 and are also supplied to the nMOS differential pair transistors 214 and 213 to secure the dynamic range of the input signal. ing. The differentially amplified signal is supplied to the gates of the nMOS transistors 216 and 217 in the level shift unit 250. Here, although the low high potential power supply voltage Vdd2 is applied to the level shift unit 250, the nMOS transistors 216 and 217 and the pMOS transistors 208 and 209 that receive the output signal of the differential amplifier unit 200 are transistors for high voltage. The pMOS transistor 210 and the nMOS transistor 218 constituting the next-stage inverter are low-voltage transistors. As described above, the level shift unit 250 shifts the output signal level of the differential amplification unit 200, thereby obtaining an output corresponding to the lowered power supply voltage.

  However, in the semiconductor integrated circuit device shown in FIG. 3, the gain in the differential amplifying unit 200 increases too much, and the output of the differential amplifying unit 200 becomes higher than the power supply voltage (Vdd2) of the level shift unit 250. Since the output of the unit 250 takes time to invert by the voltage of (Vdd1-Vdd2), the time is lost and the operation becomes slow. Further, since the level shift unit 250 does not have a current source, a through current flows and there is a problem in terms of power consumption.

FIG. 4 is a diagram schematically showing the Vgs-Ids characteristic of the transistor.
Further, as shown in FIG. 4, the high-voltage transistors (transistors 208 and 209) other than the input differential pair (transistors 216 and 217) of the level shift unit 250 have a threshold value when the power supply voltage is lowered. Since the voltage Vth is high, the gate-source voltage Vgs is low, so that the intended current does not flow easily and high-speed operation is difficult.

  In view of the problems of the above-described conventional semiconductor integrated circuit device, the present invention has a level shift function that can handle a wide range of small-amplitude high-frequency inputs and can convert an input signal into a signal of a predetermined logic voltage. An object is to provide a semiconductor integrated circuit device.

According to the present invention, Rutotomoni is connected between the first power supply line and the second power supply line, connected between the amplifier for amplifying an input differential signal, and said second power supply line and the third power supply line is Rutotomoni, and a level shift unit for shifting the level of said amplified input differential signal, the amplifier unit includes a first transistor which is diode-connected, and a second transistor which is diode-connected, said first A third transistor disposed in parallel with one transistor; and a fourth transistor disposed in parallel with the second transistor; and the level shift unit includes a fifth transistor and a sixth transistor; 1 the drain of the transistor is connected to the gates of said fifth transistor of the fourth transistor, a gate of the drain the third transistor of the second transistor The semiconductor integrated circuit device according to claim Rukoto connected to the gate of the sixth transistor is provided.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device having a level shift function capable of converting an input signal into a signal of a predetermined logic voltage while supporting high frequency input with a small amplitude in a wide range.

  Hereinafter, embodiments of a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 5 is a circuit diagram showing a first embodiment of the semiconductor integrated circuit device of the present invention. In FIG. 5, reference numeral Vdd is a high potential power supply line (high potential power supply voltage), Vss is a low potential power supply line (low potential power supply voltage), 1 to 5 are pMOS (MIS) transistors, and 6 to 8 are nMOS (MIS). Transistors 9 and 9 indicate resistance. The current source circuit (semiconductor integrated circuit device) shown in FIG. 5 is a circuit that hardly depends on fluctuations in the power supply voltage, temperature, and the like with respect to the conventional current source circuit described with reference to FIG.

  As shown in FIG. 5, the current source circuit of the first embodiment is connected to the low-potential power line Vss, and is connected to the low-potential power line Vss via the resistor 9 through which the current I0 flows. The nMOS transistor 8, the nMOS transistors 6 and 7 which are current mirrored with the nMOS transistor 8, the pMOS transistor 1 connected to the nMOS transistor 6 and the high potential power supply line Vdd, and the pMOS transistor 1 and the current mirror relationship. The pMOS transistor 3 connected to the nMOS transistor 8 and the high potential power supply line Vdd, the pMOS transistor 2 connected to the nMOS transistor 7 and the high potential power supply line Vdd, and the pMOS transistor 2 and the current mirror. PMOS transistor 4 and the source to the high potential power supply line Vdd It includes a pMOS transistor that has been continued, the. The gates of the nMOS transistors 6, 7, and 8 are connected to the connection node N2 between the pMOS transistor 2 and the nMOS transistor 7, the drain of the nMOS transistor 7 is connected to the connection node N1 between the nMOS transistor 8 and the resistor 9, The gates of pMOS transistors 2 and 4 are connected to connection node N4 between nMOS transistor 8 and pMOS transistor 3, and connection node N4 between nMOS transistor 8 and pMOS transistor 3 is connected to the gate of pMOS transistor 5 to supply current. It is designed to mirror.

  By the way, the Vds-Ids characteristic of the transistor has a predetermined slope, as shown in FIG. 2 described above, in which the current is not constant even in the saturation region. Therefore, when the potential of the power supply voltage (Vdd) rises, the currents I1, I2, I3, I4, I5, and Iout also try to increase. Next, since the current I4 increases, the potential V1 of the node N1 rises. As a result, the Vgs of the transistor 8 becomes shallow and an attempt is made to reduce the current. As a result, an increase in current due to power supply fluctuation can be suppressed. Similarly, current fluctuation due to temperature fluctuation can be suppressed.

  Further, the current generated in the transistor 2 has a function of stabilizing the current through the transistor 7 → the transistor 6 → the transistor 3. Such feedback makes it possible to configure a more stable current source. By adopting this circuit, a stable current source can be obtained without vertically stacking transistors, so that it can be used even when the power supply voltage is low.

  Furthermore, the threshold voltage Vth of the transistor changes depending on the temperature, and the current value also changes. However, by utilizing a portion where the gate-source voltage Vgs of the transistor is low, the threshold voltage of the transistor A change in Vth is almost eliminated, and the current source has almost no temperature dependence.

  Thus, it can be said that the current source circuit (semiconductor integrated circuit device) of the first embodiment is a stable current source having almost no dependency on the power supply voltage and temperature.

FIG. 6 is a circuit diagram showing a modification of the semiconductor integrated circuit device of FIG.
As apparent from the comparison between FIG. 5 and FIG. 6, the modification shown in FIG. 6 is different from the first embodiment shown in FIG. 5 in that the pMOS transistors 1 to 5 are composed of nMOS transistors 1 ′ to 5 ′. 6 to 8 are composed of pMOS transistors 6 'to 8', and the high potential power line Vdd corresponds to the low potential power line Vss, and the low potential power line Vss corresponds to the high potential power line Vdd. In the present modification of FIG. 6, the currents I0 to I4 and Iout in the first embodiment of FIG. 5 correspond to the currents I0 ′ to I4 ′ and Iout ′, respectively. In this modification of FIG. 6, the resistor 9 ′ is connected between the high potential power supply line Vdd and the source of the pMOS transistor 8.

FIG. 7 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit device of the present invention.
As shown in FIG. 7, the current source circuit (semiconductor integrated circuit device) of the second embodiment adds nMOS transistors 6a, 7a, 8a to the current source circuit of the first embodiment shown in FIG. An nMOS transistor 6a is provided between the source of the nMOS transistor 6 and the low-potential power line Vss, an nMOS transistor 7a is provided between the source of the nMOS transistor 7 and the low-potential power line Vss, and An nMOS transistor 8a is provided between the source of the nMOS transistor 8 and the resistor 9 (node N1).

  In other words, the current source circuit according to the second embodiment outputs nMOS transistors 6a, 7a and 8a in cascade connection to the nMOS transistors 6, 7 and 8 in the current source circuit according to the first embodiment shown in FIG. The resistance is increased to supply a more stable current than the current source circuit of FIG. However, in the current source circuit of the second embodiment, the power supply voltage (Vdd) is required to be a voltage higher than a certain level (for example, about 3.3 V). Note that the current source circuit of the first embodiment of FIG. 5 can be sufficiently used even when the power supply voltage (Vdd) is about 1.2V, for example.

FIG. 8 is a circuit diagram showing a third embodiment of the semiconductor integrated circuit device of the present invention.
As shown in FIG. 8, the current source circuit of the third embodiment has the same configuration as that of the first embodiment shown in FIG. However, the pMOS transistor 3 in the first embodiment is the same as the other pMOS transistors 1, 2, 4 and 5, whereas in the current source circuit of the third embodiment shown in FIG. It is configured by different types of pMOS transistors 3b.

  That is, in the third embodiment, the pMOS transistor 3b provided between the high potential power supply line Vdd and the node N4 has the other pMOS transistors 1, 2, 4 and 5 in order to reduce the value of the current I3. Or a transistor having a threshold voltage Vthb larger than the threshold voltage Vth, or when the other pMOS transistors 1, 2, 4 and 5 are made of high-speed transistors, the low-speed (normal operation) Speed), or a substrate bias deeper than the substrate bias (bias voltage applied to the well) of the other pMOS transistors 1, 2, 4 and 5 is configured.

  Thus, for example, by making the threshold voltage Vthb of the pMOS transistor 3b larger than the threshold voltage Vth of the other pMOS transistors 1, 2, 4, and 5, the value of the current I3 (I0) is set. The output current Iout is reduced (adjusted) so that a stable current can be supplied.

  As described above, each of the embodiments of the current source circuit (semiconductor integrated circuit device) according to the present invention has almost no power supply voltage dependency and can reduce the temperature dependency. It is possible to supply a stable current source that can cope with low voltage.

  FIG. 9 is a circuit diagram showing a fourth embodiment of the semiconductor integrated circuit device according to the present invention, which corresponds to a small amplitude input signal at a high frequency and a wide range of input levels, and the input signal is level-shifted to a logic level voltage. Thus, a differential amplifier having a level shift function for output is shown. In FIG. 9, reference numeral 20 denotes a differential amplifier, 50 denotes a level shift unit, 21 to 31 denote pMOS transistors, 32 to 39 and 221, 222 denote nMOS transistors, and 40 denotes an inverter. Reference numeral Vdd1 is a high high-potential power supply voltage (for example, 3.3V or 2.5V), Vdd2 is a low high-potential power supply voltage (for example, 1.8V or 1.2V), and Vss is a low-potential power supply voltage. (For example, 0V). The pMOS transistors 21 to 27 and the nMOS transistors 32 to 36, 221, and 222 are high voltage MOS transistors, and the pMOS transistors 28 to 31 and the nMOS transistors 37 to 39 are low voltage MOS transistors.

  That is, as shown in FIG. 9, the semiconductor integrated circuit device (differential amplifier having a level shift function) of the fourth embodiment is applied with a high high-potential power supply voltage Vdd1 and pMOS transistors 21 to 27 and nMOS transistors. And a level shift unit 50 having pMOS transistors 28 to 31, nMOS transistors 35 to 39, and an inverter 40 to which a low high potential power supply voltage Vdd2 is applied. .

  As is clear from the comparison between FIG. 3 and FIG. 9 described above, in the fourth embodiment, the nMOS transistors 221 and 222 (corresponding to the nMOS transistors 211 and 212 in FIG. 3) in the differential amplifier 20 are diode-connected, A current mirror connection is made with the nMOS transistors 36 and 35 of the level shift unit 50. Here, in the level shift unit 50, only the nMOS transistors 35 and 36 are constituted by high voltage MOS transistors, and the other pMOS transistors 28 to 31 and the nMOS transistors 37 to 39 are constituted by low voltage MOS transistors. Yes. The nMOS transistors 37 to 39 each constitute a current source.

  According to the semiconductor integrated circuit device of the fourth embodiment, current consumption can be suppressed by controlling the level shift current, and high-speed operation can be achieved by suppressing the gain. . Further, in the level shift unit 50, normal (low voltage) transistors other than the input transistors 35 and 36 are used, so that even if the power supply voltage is lowered, the low voltage transistor has its threshold voltage Vth. Is low, a sufficient gate-source voltage Vgs can be secured, and high-speed operation becomes possible.

FIG. 10 is a circuit diagram showing a fifth embodiment of the semiconductor integrated circuit device of the present invention.
As apparent from the comparison between FIG. 9 and FIG. 10, the semiconductor integrated circuit device of the fifth embodiment shown in FIG. 10 includes the diode-connected nMOS transistors 221 and 222 in the fourth embodiment shown in FIG. 232. That is, the voltages of the nodes N11 and N12 do not need to be higher than the low high-potential power supply voltage Vdd2, so that the gain is excessively increased by replacing the transistors 221 and 222 of the fourth embodiment with the resistors 231 and 232. This makes it possible to achieve a higher speed circuit.

FIG. 11 is a circuit diagram showing a sixth embodiment of the semiconductor integrated circuit device of the present invention.
As is apparent from the comparison between FIGS. 9 and 11, the semiconductor integrated circuit device of the sixth embodiment shown in FIG. 11 is crossed with respect to the diode-connected nMOS transistors 221 and 222 in the fourth embodiment shown in FIG. Coupled nMOS transistors 241 and 242 are provided to increase the gain. That is, the semiconductor integrated circuit device of the sixth embodiment is effective when, for example, the circuit of the fourth embodiment of FIG. 9 has insufficient gain.

FIG. 12 is a circuit diagram showing a seventh embodiment of the semiconductor integrated circuit device of the present invention.
As apparent from the comparison between FIG. 9 and FIG. 12, the semiconductor integrated circuit device of the seventh embodiment shown in FIG. 12 has an input signal to the pMOS transistors 26 and 27 in the circuit of the fourth embodiment shown in FIG. By providing the pMOS transistors 251 and 252 that receive IN and / IN and whose drains are cross-connected, the inversion speed of the transistors is increased to enable higher-speed operation. That is, in the seventh embodiment of FIG. 9 described above, when the input signal IN is at the low level “L” and the input signal / IN is at the high level “H”, a current flows through the transistors 26 and 221 and the transistor 27 In this seventh embodiment, since the drain of the transistor 251 that is turned on is connected to the drain of the transistor 27, a current path is created and current flows through the transistors 27 and 222 as well. Become. As a result, the gate voltages of the transistors 36 and 35 of the level shift unit 50 are input from a voltage earlier than the threshold voltage Vth, as described above with reference to FIG. High speed operation is possible.

FIG. 13 is a circuit diagram showing an eighth embodiment of the semiconductor integrated circuit device of the present invention.
In FIG. 13, a current source circuit 301 is obtained by applying the first to third embodiments (current source circuit) of the semiconductor integrated circuit device according to the present invention described with reference to FIGS. The differential amplifier circuit 303 is obtained by applying the fourth to seventh embodiments (differential amplifier circuit having a level shift function) of the semiconductor integrated circuit device according to the present invention described with reference to FIGS. It is.

  FIG. 14 is a diagram showing a part of the circuit in the semiconductor integrated circuit device of FIG. 13. As the current source circuit 301, the first embodiment shown in FIG. 5 (pMOS transistors 1 to 5, nMOS transistors 6 to 8, and resistors) is shown. 9) is applied, and the current mirror circuit 302 corresponds to the one in which the pMOS transistors 321, 325 and the nMOS transistors 322, 323, 324 are applied.

  As shown in FIG. 14, in order to apply the bias voltage Vbn1 to the gate of the high-voltage nMOS transistor 34 in the differential amplifier circuit 303, the drain of the pMOS transistor 321 and the low-potential power line (Vss) A high-voltage nMOS transistor 323 that is current-mirror connected to the transistor 34 is provided between them, and the bias voltage Vbn2 is applied to the gate of the low-voltage nMOS transistor 38 so that the pMOS transistor 5 Between the drain and the low-potential power supply line (Vss), a low-voltage nMOS transistor 322 that is current-mirror connected to the transistor 38 is provided, and a bias voltage is applied to the gate of the high-voltage pMOS transistor 21. In order to apply Vbp, the drain of the nMOS transistor 324 Between the high potential power supply line (Vdd), transistor 21 and the pMOS transistor 325 of the current mirror connected to high voltage is provided. In the semiconductor integrated circuit device shown in FIG. 14, the first embodiment shown in FIG. 5 is applied as the current source circuit 301. However, other embodiments can be applied, and the current mirror circuit 302 is also applied. It goes without saying that various circuits can be applied to the differential amplifier circuit 303.

  As described above, according to the semiconductor integrated circuit device of the eighth embodiment of the present invention, the current source in the differential amplifier circuit 303 can be stabilized to sufficiently cope with a high-frequency input signal.

  As described above, the current source circuit (semiconductor integrated circuit device) according to the present invention has almost no power supply voltage dependence and can reduce the temperature dependence. In addition, the power supply voltage has been lowered with the recent miniaturization of transistors. It is possible to provide a stable current source corresponding to the above. Further, the differential amplifier circuit (semiconductor integrated circuit device) according to the present invention can cope with a common level of a wide range of inputs at a high frequency, and has a function of level-shifting the output to a logic voltage value. be able to. By combining the current source circuit and the differential amplifier circuit according to the present invention, a semiconductor integrated circuit device corresponding to a more stable high frequency can be provided.

(Additional remark 1) It has the 1st MIS transistor of the 1st conductivity type, the 2nd MIS transistor of the 2nd conductivity type, and resistance which were connected in series between the 1st power supply line and the 2nd power supply line A semiconductor integrated circuit device,
A third MIS transistor of the first conductivity type having a gate connected to a connection node of the first MIS transistor and the second MIS transistor and a drain connected to a connection node of the second MIS transistor and the resistor A semiconductor integrated circuit device comprising:

(Appendix 2) In the semiconductor integrated circuit device according to Appendix 1,
A second conductivity type fourth and fifth MIS transistor connected in a current mirror connection with the second MIS transistor;
A sixth MIS transistor of a first conductivity type connected to the fourth transistor and the first power supply line and connected to the first MIS transistor as a current mirror;
A seventh MIS transistor of the first conductivity type connected to the fifth MIS transistor and the first power supply line and having a gate connected to a connection node of the first MIS transistor and the second MIS transistor; A semiconductor integrated circuit device comprising:

  (Appendix 3) In the semiconductor integrated circuit device according to Appendix 1 or 2, the source is connected to the first power supply line, and the gate is connected to a connection node of the first MIS transistor and the second MIS transistor. A semiconductor integrated circuit device comprising: an eighth MIS transistor of a first conductivity type that is connected and allows an output current to flow.

(Appendix 4) In the semiconductor integrated circuit device according to any one of appendices 1 to 3,
A second conductivity type ninth MIS transistor provided between the second MIS transistor and the resistor;
A second conductivity type tenth and eleventh MIS transistor provided between the fourth and fifth MIS transistors and the second power supply line, the second, fourth and fifth MIS transistors; 9. A semiconductor integrated circuit device, wherein the ninth, tenth and eleventh MIS transistors are cascade-connected to a MIS transistor.

  (Supplementary Note 5) In the semiconductor integrated circuit device according to any one of Supplementary notes 1 to 4, the first MIS transistor is configured as a transistor having characteristics different from those of other MIS transistors of the first conductivity type. A semiconductor integrated circuit device.

  (Appendix 6) In the semiconductor integrated circuit device according to Appendix 5, the first MIS transistor having the different characteristics has a smaller transistor size and a higher threshold voltage than the other MIS transistors of the first conductivity type. Or a semiconductor integrated circuit device, wherein the substrate bias is increased.

(Supplementary Note 7) An input signal is supplied, and an amplifying unit configured by first-conductivity-type and second-conductivity-type high-voltage MIS transistors, and an output of the amplifying unit are received and a level-shifted signal is output. A semiconductor integrated circuit device having a level shift unit,
The amplifying unit includes a diode-connected second conductivity type high voltage MIS transistor,
The level shift unit includes a second conductivity type high voltage MIS transistor connected to the diode-connected second conductivity type high voltage MIS transistor, a second conductivity type high voltage MIS transistor, and a first conductivity type and a second conductivity type. A semiconductor integrated circuit device comprising a low-voltage MIS transistor.

  (Supplementary note 8) The semiconductor integrated circuit device according to supplementary note 7, wherein the diode-connected second conductivity type high-voltage MIS transistor is replaced with a resistor.

  (Supplementary Note 9) In the semiconductor integrated circuit device according to Supplementary Note 7, the second conductivity type high voltage MIS transistor is cross-coupled to the diode-connected second conductivity type high voltage MIS transistor. A semiconductor integrated circuit device.

  (Supplementary Note 10) In the semiconductor integrated circuit device according to any one of Supplementary Notes 7 to 9, the amplifying unit includes a first conductivity type high-voltage MIS transistor pair that receives a differential input signal. A semiconductor integrated circuit device.

  (Supplementary Note 11) In the semiconductor integrated circuit device according to Supplementary Note 10, a pair of first conductivity type high voltages whose drains are cross-connected to the first conductivity type high voltage MIS transistor pair and whose drains are cross-connected. A semiconductor integrated circuit device comprising a MIS transistor for use.

(Appendix 12) In the semiconductor integrated circuit device according to any one of appendices 7 to 11, the amplifying unit includes:
A first differential pair having a first conductivity type high voltage MIS transistor pair for receiving a differential input signal;
A semiconductor integrated circuit device comprising: a second differential pair having a second-conductivity-type high-voltage MIS transistor pair that receives the differential input signal.

(Supplementary note 13) The semiconductor integrated circuit device according to any one of supplementary notes 1 to 6 is a current source circuit,
The semiconductor integrated circuit device according to any one of appendices 7 to 12 is a differential amplifier circuit,
A semiconductor integrated circuit device, wherein an output current of the current source circuit is used as a bias voltage of a current source in the differential amplifier circuit via a current mirror circuit.

It is a circuit diagram which shows an example of the conventional semiconductor integrated circuit device. It is a figure which shows roughly the Vds-Ids characteristic of a transistor. It is a circuit diagram which shows the other example of the conventional semiconductor integrated circuit device. It is a figure which shows roughly the Vgs-Ids characteristic of a transistor. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit device of the present invention; FIG. 6 is a circuit diagram showing a modification of the semiconductor integrated circuit device of FIG. 5. It is a circuit diagram which shows the 2nd Example of the semiconductor integrated circuit device of this invention. It is a circuit diagram which shows the 3rd Example of the semiconductor integrated circuit device of this invention. It is a circuit diagram which shows the 4th Example of the semiconductor integrated circuit device of this invention. FIG. 10 is a circuit diagram showing a fifth embodiment of the semiconductor integrated circuit device of the present invention. It is a circuit diagram which shows 6th Example of the semiconductor integrated circuit device of this invention. It is a circuit diagram which shows the 7th Example of the semiconductor integrated circuit device of this invention. It is a circuit diagram which shows the 8th Example of the semiconductor integrated circuit device of this invention. It is a figure which shows a part of circuit in the semiconductor integrated circuit device of FIG.

Explanation of symbols

1-5; 6'-8 '; 101-103 p-channel MOS transistor (pMOS transistor)
1 ′ to 5 ′; 6 to 8; 6a to 8a; 104, 105 n-channel MOS transistor (nMOS transistor)
9; 106; 231, 232 Resistance 20,200 Amplification section (differential amplification section)
21-27; 201-209; 251, 252; 325 High-voltage pMOS transistors 28-31; 210; 321 Low-voltage pMOS transistors 32-36; 211-217; 221, 222; 241, 242; 323 nMOS transistors 37 to 39; 218; 322, 324 Low voltage nMOS transistors 40, 219 Inverters 50, 250 Level shift unit 301 Current source circuit 302 Current mirror circuit 303 Differential amplification circuit IN, / IN Differential input signal Vdd High potential Power supply line (high potential power supply voltage)
Vdd1 High high potential power supply voltage Vdd2 Low high potential power supply voltage Vss Low potential power supply line (low potential power supply voltage)

Claims (6)

Rutotomoni is connected between the first power supply line and the second power supply line, an amplifying unit for amplifying an input differential signal,
Rutotomoni connected between the second power supply line and the third power supply line, and a level shift unit for shifting the level of said amplified input differential signal,
The amplification unit is
A diode-connected first transistor ;
A diode-connected second transistor;
A third transistor disposed parallel to the first transistor;
A fourth transistor disposed in parallel with the second transistor ,
The level shift unit includes a fifth transistor and a sixth transistor ,
The drain of the first transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor ;
The semiconductor integrated circuit device in which the drain of the second transistor is characterized Rukoto connected to gates of said sixth transistor of the third transistor. The amplifying unit converts a voltage level of the input differential signal into a drain voltage of the first transistor and a drain voltage of the second transistor according to the first transistor and the second transistor. The semiconductor integrated circuit device according to claim 1 . The semiconductor integrated circuit device according to claim 2 , wherein the fifth transistor and the sixth transistor are high-voltage transistors. It said third transistor and said fourth transistor, to the first transistor and the second transistor, the semiconductor integrated according to any one of claims 1 to 3, characterized that you have been cross-coupled Circuit device. Said first transistor, said fifth transistor, said second transistor and the sixth transistor, the semiconductor integrated circuit device according to any one of claims 1 to 4, characterized in that the same conductivity type. 2. The level shift unit includes a plurality of transistors other than the fifth transistor and the sixth transistor, and the plurality of transistors includes a transistor for lower voltage than the first transistor. The semiconductor integrated circuit device according to any one of to 5 .

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