JP5061957B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that stabilizes the gain of a resistive load amplifier against fluctuations in power supply voltage, temperature, transistor process parameters, and the like.

  The current mirror circuit is a circuit that outputs a current having the same direction and the same current value as the input current. The basic idea of a current source circuit using a current mirror circuit is to generate a stable current without depending on the power supply voltage, temperature, transistor process parameters, and the like. By using such a current mirror circuit as a current source, a mutual conductance compensation circuit for compensating for the mutual conductance of the transistor can be configured.

FIG. 10 is an explanatory diagram showing an example of a conventional mutual conductance compensation circuit. The transconductance compensation circuit 10 shown in FIG. 10 is an example of a current source circuit that does not depend on the power supply voltage. As shown in FIG. 10, the transconductance compensating circuit 10 is configured to include four transistors M1, M2, M3, M4, and resistors _{R s,} a. The transistors M1 and M2 are N-channel transistors, and the transistors M3 and M4 are P-channel transistors. VDD is a power supply voltage.

In the transconductance compensation circuit 10 shown in FIG. 10, since the transistors M3 and M4, which are P-channel transistors, are current mirror connected, the current flowing through the mutual conductance compensation circuit 10 satisfies I1 = I2. The gate of the N-channel transistors M1 - source voltage _{V gs1,} the drain - source voltage _{V ds1,} the current amplification factor _{β 1 (= μ n × C} ox × (W / L), μ n: the mobility , C _ox : gate capacitance per unit area, W: transistor gate width, L: transistor gate length), gate-source voltage of the N-channel transistor M2 is V _gs2 , and drain-source voltage is V _ds2 the current amplification factor as a K × beta _1, the threshold voltage _{V th} of the N-channel transistors M1, M2 are equal respectively, holds the following equation.

The following formulas are established by these formulas 1 to 3.

This equation 4, the circuit shown in FIG. 10 _is a transconductance compensating circuit in _V ds1 ₌ V _ds2. Since the power supply voltage VDD is not included in the above formula 4, the circuit shown in FIG. 10 can be said to be a circuit whose current value does not depend on the power supply voltage.

However, for example, there is a characteristic as shown in FIG. 11 between the drain-source voltage _Vds and the drain-source current _Ids of the transistor. Figure 11 is an explanatory view schematically showing a _V ds- _{I ds} characteristics of the transistors. As shown in FIG. 11, in an ideal transistor, I _ds should not increase even if V _ds increases in the saturation region of FIG. 11, but actually, as shown in FIG. As V _ds increases, I _ds increases gently. Therefore, the power supply voltage VDD increases.

  Therefore, when the power supply voltage VDD increases, the drain-source voltages of the P-channel transistors M3 and M4 in the mutual conductance compensation circuit 10 shown in FIG. 10 increase accordingly, and the amount of current increases. Conversely, when the power supply voltage VDD decreases, the drain-source voltages of the P-channel transistors M3 and M4 also decrease and the amount of current decreases. Depending on the conditions, a linear region is entered in the characteristics shown in FIG. There is also a risk.

In transconductance compensating circuit 10 shown in FIG. 10, the gate of the P-channel transistor M4 - When the source voltage and _{V GS4,} the drain voltage _{V d2} of the N-channel transistors M2 and P-channel transistor M4 is determined by _{VDD-V GS4,} The drain voltage V _d1 of the N channel transistor M1 and the P channel transistor M3 is determined by V _gs1 . Therefore, V _d1 and V _d2 are different. Taking this into consideration, the current value is calculated from the drain-source resistance component _{Rds2 of} the N-channel transistor M2 as follows.

From Expression 5, I2 ≠ I1, and a phenomenon occurs in which the current value cannot be mirrored correctly, and the mutual conductance compensation circuit 10 is degraded in accuracy as a current mirror circuit. Further, the accuracy as the current mirror circuit may be further deteriorated due to factors such as a mismatch of the threshold voltage _Vth between the transistors and the current amplification factor β.

  As a result, the conventional transconductance compensation circuit 10 shown in FIG. 10 should ideally be able to pass current without depending on the power supply voltage. However, in reality, it may depend on the power supply voltage VDD, and the temperature dependency and the transistor process parameter dependency may be large.

Conventionally, when a certain level of power supply voltage (power supply margin) can be ensured, a technique for improving the accuracy as a current mirror circuit by connecting a plurality of transistors in series to form a cascode configuration Is disclosed. However, with recent demands for finer transistors, faster operating frequencies, and lower power consumption, it is necessary to lower the power supply voltage (for example, it is necessary to operate with a power supply voltage of 1.2 V or less). ). Therefore, the conventional method has a problem that it is difficult to ensure and improve accuracy as a current mirror circuit. Furthermore, the slope in the saturation region of the V _ds- I _ds characteristics of the transistor also increases, there is a problem that the design of the stable current source is becoming more difficult.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to realize a current mirror circuit with high accuracy even in a low power supply voltage or a fine process, and to provide a power supply voltage, temperature, It is an object of the present invention to provide a new and improved semiconductor integrated circuit capable of realizing a circuit independent of a process parameter of a transistor.

  In order to solve the above problems, according to one aspect of the present invention, there is provided a semiconductor integrated circuit provided between a first potential line that supplies a power supply voltage and a second potential line that has a potential lower than the power supply voltage. A first constant current output means for inputting a power supply voltage and outputting a plurality of currents having a first current value; and a first constant current output means for inputting a power supply voltage and outputting a plurality of currents having a second current value. 2 constant current output means, and an adjustment means for adjusting the first current value and the second current value to be equal to each other. The adjustment means has a current having a first current value by a differential input. Provided is a semiconductor integrated circuit characterized in that a first current value and a second current value are adjusted to be equal by equalizing a flowing potential and a potential at which a current having a second current value flows. Is done.

  According to such a configuration, the first constant current output means inputs the power supply voltage and outputs a plurality of currents having the first current value, and the second constant current output means inputs the power supply voltage and the second constant current output means inputs the power supply voltage. A plurality of currents having a current value of Then, the adjusting means equalizes the potential at which the current having the first current value flows and the potential at which the current having the second current value flows by the differential input, so that the first current value and the second current are equalized. Adjust so that the values are equal. As a result, even in a low power supply voltage or a fine process, a current mirror circuit with high accuracy can be realized without depending on the power supply voltage, temperature, and transistor process parameters.

  The first constant current output means includes a first transistor and a second transistor having a source terminal connected to the first potential line and a current mirror connection. The second constant current output means has a source terminal connected to the first potential line. A third transistor and a fourth transistor connected to one potential line and connected in a current mirror manner; the adjusting means includes: a fifth transistor having a drain terminal connected to the drain terminal of the third transistor; and a drain terminal Is connected to the drain terminal of the second transistor, the sixth transistor is current-mirror connected to the fifth transistor, the drain terminal is connected to the drain terminal of the first transistor, and the gate terminal is connected to the drain of the sixth transistor. The seventh transistor connected to the drain terminal and the drain terminal connected to the drain terminal of the fourth transistor A gate terminal connected to the drain terminal of the sixth transistor, an eighth transistor constituting the fifth transistor and the differential pair may contain. As a result, a transconductance compensation circuit with high accuracy can be realized even in a low power supply voltage or in a fine process by using a feedback configuration using transistors without adopting a cascode configuration.

  The semiconductor integrated circuit may further include a resistor connected to the source terminal of the fifth transistor. As a result, by making the drain potential of the fifth transistor equal to the drain potential of the sixth transistor, it is possible to realize a transconductance compensation circuit with further improved accuracy.

  The first constant current output means includes a first transistor and a second transistor connected in a current mirror, and the second constant current output means includes a third transistor and a fourth transistor connected in a current mirror. The adjusting means includes a fifth transistor having a source terminal connected to the first potential line, a drain terminal connected to the drain terminal of the third transistor, and a source terminal connected to the first potential line; The drain terminal is connected to the drain terminal of the second transistor, the sixth transistor is current mirror connected to the fifth transistor, the source terminal is connected to the first potential line, and the drain terminal is the drain of the first transistor. And the gate terminal is connected to the drain terminal of the sixth transistor to form a differential pair with the sixth transistor. A transistor having a source terminal connected to the first potential line, a drain terminal connected to the drain terminal of the fourth transistor, and a gate terminal connected to the drain terminal of the sixth transistor; May be included. As a result, a transconductance compensation circuit with high accuracy can be realized even in a low power supply voltage or in a fine process by using a feedback configuration using transistors without adopting a cascode configuration.

  The semiconductor integrated circuit may further include a first resistor connected to a source terminal of the fourth transistor or a source terminal of the eighth transistor. Here, by connecting a resistor to the source terminal of the eighth transistor, it is possible to realize a mutual conductance compensation circuit that has both the mutual conductance of the amplifier having the P-channel transistor input configuration and the resistance load correction. .

  The semiconductor integrated circuit may further include a second resistor connected to the source terminal of the fifth transistor. As a result, by making the drain potential of the fifth transistor equal to the drain potential of the sixth transistor, it is possible to realize a transconductance compensation circuit with further improved accuracy.

  In order to solve the above problem, according to another aspect of the present invention, a semiconductor integrated circuit provided between a first potential line for supplying a power supply voltage and a second potential line having a potential lower than the power supply voltage. A first constant current output means for inputting a power supply voltage and outputting a plurality of first currents having a first current value; and a plurality of inputs having a power supply voltage and having a second current value Second constant current output means for outputting the second current, first adjustment means for outputting a third current having a third current value equal to the first current value, and a second current value And a second adjustment unit that adjusts the third current value to be equal to each other. The first adjustment unit includes a potential at which the first current having the first current value flows through the differential input and the first current value. By equalizing the potential through which the third current having a current value of 3 flows, the first current value and the third current value The second adjustment means adjusts the current value to be equal to each other, and the second adjustment means is configured to cause a potential at which a second current having a second current value flows and a potential at which a third current having a third current value flows by differential input. Are made equal so that the second current value and the third current value are adjusted to be equal.

  According to such a configuration, the first constant current output means inputs the power supply voltage and outputs a plurality of currents having the first current value, and the second constant current output means inputs the power supply voltage and the second constant current output means inputs the power supply voltage. A plurality of currents having a current value of Then, the first adjusting means equalizes the potential at which the first current having the first current value flows through the differential input and the potential at which the third current having the third current value flows. The second adjustment means adjusts the potential at which the second current having the second current value flows by the differential input and the third current value so that the current value of 1 is equal to the third current value. The second current value and the third current value are adjusted to be equal by equalizing the potential at which the third current flows. As a result, even in a low power supply voltage or a fine process, a current mirror circuit with high accuracy can be realized without depending on the power supply voltage, temperature, and transistor process parameters.

  The first constant current output means includes a first transistor and a second transistor having a source terminal connected to the second potential line and a current mirror connection. The second constant current output means has a source terminal connected to the first transistor. The first adjusting means includes a third transistor and a fourth transistor that are connected to one potential line and are current-mirror connected. The first adjustment means has a source terminal connected to the first potential line and a drain terminal connected to the first transistor. A fifth transistor connected to the drain terminal; a source terminal connected to the first potential line; a sixth transistor connected to the fifth transistor in a current mirror; and a source terminal connected to the first potential line; A seventh transistor having a gate terminal connected to the drain terminal of the sixth transistor and a drain terminal connected to the drain terminal of the tenth transistor; The source terminal is connected to the first potential line, the drain terminal is connected to the drain terminal of the second transistor, the gate terminal is connected to the drain terminal of the sixth transistor, and forms a differential pair with the fifth transistor. An eighth transistor, and the second adjustment means includes a ninth transistor having a drain terminal connected to the drain terminal of the third transistor, and a drain terminal connected to the drain terminal of the eighth transistor, A tenth transistor that is current-mirror connected to the ninth transistor, an eleventh transistor having a drain terminal connected to the drain terminal of the sixth transistor and a gate terminal connected to the drain terminal of the tenth transistor; The drain terminal is connected to the drain terminal of the fourth transistor, and the gate terminal is the tenth transistor. It is connected to the drain terminal of the capacitor, and a twelfth transistor which constitutes the ninth transistor and the differential pair may contain.

  The semiconductor integrated circuit may further include a resistor connected to the source terminal of the eleventh transistor or the source terminal of the sixth transistor. Here, by connecting a resistor to the source terminal of the sixth transistor, it is possible to realize a transconductance compensation circuit having both the transconductance compensation of the amplifier having the P-channel transistor input configuration and the resistance load correction. it can.

  As described above, according to the present invention, by using the feedback configuration, a current mirror circuit with high accuracy can be realized even in a low power supply voltage or a fine process, and the circuit does not depend on the power supply voltage, temperature, or transistor process parameters. A new and improved semiconductor integrated circuit capable of realizing the above can be provided.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

(First embodiment)
First, the current mirror circuit 100 according to the first embodiment of the present invention will be described. FIG. 1 is an explanatory diagram illustrating the configuration of a current mirror circuit 100 according to the first embodiment of the present invention. The current mirror circuit 100 according to the first embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 1, a current mirror circuit 100 according to the first embodiment of the present invention includes an eight transistors M1 to M8, a resistor R _s, a. Transistors M1, M2, M5, and M6 are N-channel transistors, and transistors M3, M4, M7, and M8 are P-channel transistors. VDD is a power supply voltage.

  The current mirror circuit 100 shown in FIG. 1 has a configuration in which N-channel transistors M5 and M6 and P-channel transistors M7 and M8 are added to the mutual conductance compensation circuit 10 shown in FIG. The transistors M4 and M8 are an example of the configuration of the first constant current output unit of the present invention. The transistors M3 and M7 are an example of the configuration of the second constant current output unit of the present invention. The transistors M1 and M2 , M5 and M6 are examples of the configuration of the adjusting means of the present invention.

なお、Ｖ_ｇ１、Ｖ_ｇ５は、それぞれ図２に示したトランジスタＭ１、Ｍ５のゲート電位を表している。 FIG. 2 is a circuit diagram in which the transistors M1, M3, M5, and M7 are extracted from the current mirror circuit 100 shown in FIG. As shown in FIG. 2, it can be considered that the current mirror circuit 100 includes an operational amplifier 110 including transistors M1, M3, M5, and M7. The configuration shown in FIG. 2 is a configuration of an N-channel transistor differential input type unity gain buffer. That is, it can be said that the current mirror circuit 100 shown in FIG. 1 adopts a feedback configuration using N-channel transistors M1 and M5. Accordingly, assuming that the voltage gain of the operational amplifier 110 is A and that A is sufficiently large, the following equation is established.

V _g1 and V _g5 represent the gate potentials of the transistors M1 and M5 shown in FIG.

  In the current mirror circuit 100 shown in FIG. 1, assuming that the current amplification factors and threshold voltages of the P-channel transistors M4 and M8 are equal and that the channel length L is sufficiently large in consideration of the channel length modulation effect, P Since the channel transistors M4 and M8 are current mirror connected, the relationship between the current values I1 and I2 is I1 = I2.

  Similarly, for the P channel transistors M3 and M7, assuming that the current amplification factor and the threshold voltage are equal and the channel length is sufficiently large, the P channel transistors M3 and M7 are connected in a current mirror, so that The relationship between I3 and I4 is I3 = I4.

  Further, similarly for N channel transistors M5 and M6, assuming that the current amplification factor and the threshold voltage are equal and the channel length is sufficiently large, N2 transistors M5 and M6 are current mirror connected, so that I2 = I3 holds. Accordingly, the current flowing through the current mirror circuit 100 shown in FIG. 1 satisfies the relationship I1 = I2 = I3 = I4.

Source voltage _{V gs1,} the drain - - gate of N-channel transistors M1-source voltage _{V ds1,} the current amplification factor _{β 1 (= μ n × C} ox × (W / L), μ n: the mobility, C _ox : gate capacitance per unit area, W: transistor gate width, L: transistor gate length), N-channel transistor M2 gate-source voltage _Vgs2 , drain-source voltage _Vds2 , current Assuming that the amplification factor is K × β ₁ and the threshold voltages V _th of the N-channel transistors M1 and M2 are equal, the following equation is established.

The following formulas are established by these formulas 7-9.

Equation 10 is the same as Equation 4 described above. Therefore, a current mirror circuit 100 shown in FIG. _1, it can be seen that established as transconductance compensating circuit in _V ds1 ₌ V _ds2. Also, the current mirror circuit 100 shown in FIG. 1 is a in case of rising from it adopts a feedback configuration with N-channel transistors M1, M5, if the drain potential V _d1 of the N-channel transistor M1 is by a change in the power supply voltage VDD However, it operates so as to be equal to the drain potential V _d2 of the N-channel transistor M2.

Further, in the current mirror circuit 100 shown in FIG. 1, the drain potential V _d1 of the N-channel transistor M1 and the drain potential V _d2 of the N-channel transistor M2 are the gate-source voltage V _{gs3 of the} P-channel transistors M3 and M4, respectively. , V _gs4 . Therefore, if the same size of the P-channel transistors M3, M4, _{respectively,} V _{gs3, V GS4} also the same _{value, V d1} and _{V d2} becomes equal to each other.

  Therefore, the current mirror circuit 100 shown in FIG. 1 is more accurate as a current mirror circuit than the conventional current mirror circuit. Therefore, the current mirror circuit 100 according to the first embodiment of the present invention does not adopt a cascode configuration, but uses a feedback configuration using an N-channel transistor, so that accurate mutual conductance compensation can be achieved even in a low power supply voltage or a fine process. A circuit can be realized.

  Next, a modification of the current mirror circuit according to the first embodiment of the present invention will be described. FIG. 3 is an explanatory diagram illustrating the configuration of the current mirror circuit 101, which is a modification of the first embodiment of the present invention. Hereinafter, a current mirror circuit 101 according to a modification of the first embodiment of the present invention will be described with reference to FIG.

In the current mirror circuit 100 shown in FIG. 1, the drain potentials V _d5 and V _d6 of the N-channel transistors M5 and M6 should ideally be equal. However, a slight error may occur between the two due to fluctuations in the power supply voltage, temperature, and process parameters of the transistor. FIG. 3 shows an example in which an error occurs in the drain potentials V _d5 and V _d6 , and the value of (W / L) of the N-channel transistor M5 is the value of (W / L) of the N-channel transistor M6. It is shown that it is K times.

In such a case, a resistor R _sa is connected to the source terminal of the N-channel transistor M5 as shown in FIG. The resistor R _sa is connected so that the drain potentials V _d5 and V _d6 of the N-channel transistors M5 and M6 are equal. The resistance value of the resistor R _sa is the drain potential V _d5 of the N-channel transistor M5. It is set to be equal to the drain potential V _d6 of the transistor M5. The resistance value of the resistor R _sa is preferably a value equal to the resistance of the resistor R _s.

As described above, the resistance R _sa is connected to the source terminal of the N-channel transistor M5 so that the drain potentials V _d5 and V _{d6 of} the N-channel transistors M5 and M6 are equal to each other. A conductance compensation circuit can be realized.

(Second Embodiment)
In the first embodiment of the present invention, a transconductance compensation circuit with improved accuracy is realized by feedback using N-channel transistors M5 and M6. In the second embodiment of the present invention, a transconductance compensation circuit whose accuracy is improved by feedback using a P-channel transistor will be described.

  FIG. 4 is an explanatory diagram illustrating the configuration of the current mirror circuit 200 according to the second embodiment of the present invention. The current mirror circuit 200 according to the second embodiment of the present invention will be described below with reference to FIG.

  The current mirror circuit 200 shown in FIG. 4 has a configuration in which N-channel transistors M5 and M6 and P-channel transistors M7 and M8 are added to the mutual conductance compensation circuit 10 shown in FIG. Further, the drain terminal of the P-channel transistor M7 and the gate terminals of the P-channel transistors M3 and M4 are connected. Further, since the drain terminal of the P-channel transistor M8 and the gate terminal of the P-channel transistor M7 are connected, the P-channel transistors M7 and M8 are current mirror connected. Therefore, the current mirror circuit 200 shown in FIG. 4 has a feedback configuration using P-channel transistors. The transistors M1 and M5 are an example of the configuration of the first constant current output unit of the present invention. The transistors M2 and M6 are the example of the configuration of the second constant current output unit of the present invention. The transistors M3 and M4 , M7 and M8 are examples of the configuration of the adjusting means of the present invention.

なお、Ｖ_ｇ３、Ｖ_ｇ７は、それぞれ図５に示したトランジスタＭ３、Ｍ７のゲート電位を表している。 FIG. 5 is a circuit diagram in which the transistors M1, M3, M5, and M7 are extracted from the current mirror circuit 200 shown in FIG. As shown in FIG. 5, the current mirror circuit 200 can be considered to constitute an operational amplifier 210 with transistors M1, M3, M5, and M7. The configuration shown in FIG. 5 is a P-channel transistor differential input type unity gain buffer configuration. That is, it can be said that the current mirror circuit 200 shown in FIG. 4 adopts a feedback configuration using P-channel transistors M3 and M7. Accordingly, assuming that the voltage gain of the operational amplifier 210 is A and that A is sufficiently large, the following equation is established.

V _g3 and V _g7 represent gate potentials of the transistors M3 and M7 shown in FIG.

  In the current mirror circuit 200 shown in FIG. 4 and assuming that the current amplification factors and threshold voltages of the P-channel transistors M4 and M8 are equal and the channel length is sufficiently large, from the above equation 11, I1 = I2 holds.

  Similarly, for the P channel transistors M7 and M8, assuming that the current amplification factor and the threshold voltage are equal and the channel length is sufficiently large, the P channel transistors M7 and M8 are connected in a current mirror, so that I2 = I3 holds.

  Similarly, assuming that the N channel transistors M1 and M5 have the same current amplification factor and threshold voltage and a sufficiently large channel length, the N channel transistors M1 and M5 are connected in a current mirror, so that I3 = I4 holds. Therefore, the current flowing through the current mirror circuit 200 shown in FIG. 4 has a relationship of I1 = I2 = I3 = I4.

Source voltage _{V gs1,} the drain - - gate of N-channel transistors M1-source voltage _{V ds1,} the current amplification factor _{β 1 (= μ n × C} ox × (W / L), μ n: the mobility, C _ox : gate capacitance per unit area, W: transistor gate width, L: transistor gate length), N-channel transistor M2 gate-source voltage _Vgs2 , drain-source voltage _Vds2 , current Assuming that the amplification factor is K × β ₁ and the threshold voltages V _th of the N-channel transistors M1 and M2 are equal, the following equation is established.

The following formulas are established by these formulas 12-14.

Equation 15 is the same as Equation 4 described above. Thus, the current mirror circuit 200 shown in FIG. _4, it can be seen that established as transconductance compensating circuit in _V ds1 ₌ V _ds2. Further, since the current mirror circuit 200 shown in FIG. 4 adopts a feedback configuration using a P-channel transistor, even if the drain potential V _d1 of the N-channel transistor M1 rises due to a change in the power supply voltage VDD, It operates so as to be equal to the drain potential V _d2 of the N-channel transistor M2.

  Therefore, the current mirror circuit 200 shown in FIG. 4 is more accurate as a current mirror circuit than the conventional current mirror circuit. Therefore, the current mirror circuit 200 according to the second embodiment of the present invention does not adopt a cascode configuration, but uses a feedback configuration using a P-channel transistor, so that accurate mutual conductance compensation can be achieved even in a low power supply voltage or a fine process. A circuit can be realized.

  Next, a modification of the current mirror circuit according to the second embodiment of the present invention will be described. FIG. 6 is an explanatory diagram illustrating the configuration of a current mirror circuit 201, which is a first modification of the second embodiment of the present invention. Hereinafter, a current mirror circuit 201 according to a modification of the second embodiment of the present invention will be described with reference to FIG.

In the current mirror circuit 200 shown in FIG. 5, the drain potentials V _d5 and V _d6 of the N-channel transistors M5 and M6 should ideally be equal. However, a slight error may occur between the two due to fluctuations in the power supply voltage, temperature, and process parameters of the transistor. FIG. 6 shows an example in which an error occurs in the drain potentials V _d5 and V _d6 , and the value of (W / L) of the N-channel transistor M5 is the value of (W / L) of the N-channel transistor M6. It is shown that it is K times.

In such a case, as shown in FIG. 6, the resistor R _sa is connected to the source terminal of the N-channel transistor M5 as in the above-described modification of the first embodiment of the present invention. The resistor R _sa is connected so that the drain potentials V _d5 and V _d6 of the N-channel transistors M5 and M6 are equal. The resistance value of the resistor R _sa is the drain potential V _d5 of the N-channel transistor M5. It is set to be equal to the drain potential V _d6 of the transistor M5. The resistance value of the resistor R _sa is preferably a value equal to the resistance of the resistor R _s.

As described above, the resistance R _sa is connected to the source terminal of the N-channel transistor M5 so that the drain potentials V _d5 and V _{d6 of} the N-channel transistors M5 and M6 are equal to each other. A conductance compensation circuit can be realized.

  FIG. 7 is an explanatory diagram for explaining the configuration of the current mirror circuit 202, which is a second modification of the second embodiment of the present invention. Hereinafter, a current mirror circuit 202 according to a modification of the second embodiment of the present invention will be described with reference to FIG.

The current mirror circuit 202 shown in FIG. 7, the resistor R _s, which is connected to a source terminal of the N-channel transistor M2 in the current mirror circuit 200 shown in FIG. 5, the connection moves to the source terminal of the P-channel transistor M4 It is a thing.

As shown in FIG. 7, the resistor R _s, by connecting the source terminal of the P-channel transistor M4, and combines the mutual conductance compensation amplifier having an input configuration of P-channel transistors, both the resistive load correction A mutual conductance compensation circuit characterized by this can be realized.

(Third embodiment)
In the first embodiment of the present invention, a transconductance compensation circuit with improved accuracy is realized by feedback using N-channel transistors M5 and M6. In the second embodiment of the present invention, feedback by P-channel transistors M7 and M8 is used. A transconductance compensation circuit with improved accuracy was realized. In the third embodiment of the present invention, a mutual conductance compensation circuit whose accuracy is improved by both feedback configurations will be described.

  FIG. 8 is an explanatory diagram illustrating the configuration of a current mirror circuit 300 according to the third embodiment of the present invention. Hereinafter, a current mirror circuit 300 according to a third embodiment of the present invention will be described with reference to FIG.

The current mirror circuit 300 shown in FIG. 8 has a configuration in which N-channel transistors M5, M6, M9, and M10 and P-channel transistors M7, M8, M11, and M12 are added to the mutual conductance compensation circuit 10 shown in FIG. ing. Further, the drain terminal and the gate terminal of the N-channel transistor M5 are connected, and the drain terminal of the N-channel transistor M6 and the gate terminals of the N-channel transistors M1 and M2 are connected. Further, since the drain terminal of the N-channel transistor M5 and the gate terminal of the N-channel transistor M6 are connected, the N-channel transistors M5 and M6 are current mirror connected. Therefore, the current mirror circuit 300 shown in FIG. 3 has a feedback configuration using N-channel transistors. The transistors M9 and M10 are an example of the configuration of the first constant current output unit of the present invention. The transistors M3 and M7 are an example of the configuration of the second constant current output unit of the present invention. The transistors M4 and M8 , M11, M12 are examples of the configuration of the first adjusting means of the present invention, and the transistors M1, M2, M5, M6 are examples of the configuration of the second adjusting means of the present invention.

  Further, the drain terminal of the P-channel transistor M4 and the gate terminals of the P-channel transistors M8 and M12 are connected. Further, since the drain terminal of the P-channel transistor M11 and the gate terminal of the P-channel transistor M4 are connected, the P-channel transistors M4 and M11 are current mirror connected. Therefore, the current mirror circuit 300 shown in FIG. 8 also has a feedback configuration using P-channel transistors.

  In the current mirror circuit 300 shown in FIG. 8, it is considered that the transistors M1, M3, M5, and M7 and the transistors M9, M10, M11, and M12 each constitute an operational amplifier. The transistors M1, M3, M5, and M7 are configured as an N-channel transistor differential input type unity gain buffer, and the transistors M9, M10, M11, and M12 are configured as a P-channel transistor differential input type unity gain buffer. It has become.

なお、Ｖ_ｇ１１、Ｖ_ｇ１２は、それぞれトランジスタＭ１１、Ｍ１２のゲート電位を表している。 First, assuming that A is sufficiently large, where A is the voltage gain of an operational amplifier composed of transistors M9, M10, M11, and M12, the following equation is established.

V _g11 and V _g12 represent the gate potentials of the transistors M11 and M12, respectively.

なお、Ｖ_ｇ１、Ｖ_ｇ５は、それぞれトランジスタＭ１、Ｍ５のゲート電位を表している。 Next, assuming that the voltage gain of the operational amplifier composed of the transistors M1, M3, M5, and M7 is A, and assuming that A is sufficiently large, the following equation is established.

V _g1 and V _g5 represent gate potentials of the transistors M1 and M5, respectively.

  In the current mirror circuit 300 shown in FIG. 8, assuming that the current amplification factors and threshold voltages of the N-channel transistors M9 and M10 are equal and the channel length L is sufficiently large, the N-channel transistors M9 and M10 are connected in a current mirror. Therefore, the relationship between the current values I1 and I2 is I1 = I2.

  Assuming that the N channel transistors M5 and M6 have the same current amplification factor and threshold voltage, and the channel length L is sufficiently large, the N channel transistors M5 and M6 are current mirror-connected. The relationship between I4 and I5 is I4 = I5.

  Next, regarding the P channel transistors M3 and M7, assuming that the current amplification factor and the threshold voltage are equal and the channel length L is sufficiently large, since the P channel transistors M3 and M7 are current mirror connected, The relationship between the values I5 and I6 is I5 = I6.

  Also, assuming that the current amplification factor and the threshold voltage are equal and the channel length L is sufficiently large for the P-channel transistors M4 and M11, the P-channel transistors M4 and M11 are current-mirror connected. The relationship between I2 and I3 is I2 = I3.

  Assuming that the P channel transistors M8 and M12 have the same current amplification factor and threshold voltage, and that the channel length L is sufficiently large, the P channel transistors M8 and M12 are current-mirror connected. As for the relationship between I1 and I4, I1 = I4 holds. Therefore, the current flowing through the current mirror circuit 300 shown in FIG. 8 satisfies the relationship of I1 = I2 = I3 = I4 = I5 = I6.

Source voltage _{V gs1,} the drain - - gate of N-channel transistors M1-source voltage _{V ds1,} the current amplification factor _{β 1 (= μ n × C} ox × (W / L), μ n: the mobility, C _ox : gate capacitance per unit area, W: transistor gate width, L: transistor gate length), N-channel transistor M2 gate-source voltage _Vgs2 , drain-source voltage _Vds2 , current Assuming that the amplification factor is K × β ₁ and the threshold voltages V _th of the N-channel transistors M1 and M2 are equal, the following equation is established.

The following formulas are established by these formulas 18-20.

Formula 21 is the same as Formula 4 described above. Therefore, a current mirror circuit 300 shown in FIG. _8, it can be seen that established as transconductance compensating circuit in _V ds1 ₌ V _ds2. Further, since the current mirror circuit 300 shown in FIG. 8 adopts a double feedback configuration using a P-channel transistor and an N-channel transistor, if the drain potential V _d1 of the N-channel transistor M1 rises due to a change in the power supply voltage VDD. Even so, it operates so as to be equal to the drain potential V _d2 of the N-channel transistor M2.

  Therefore, the current mirror circuit 300 shown in FIG. 8 is more accurate as a current mirror circuit than the conventional current mirror circuit. Therefore, the current mirror circuit 300 according to the third embodiment of the present invention does not adopt a cascode configuration, but uses a double feedback configuration using a P-channel transistor and an N-channel transistor, thereby improving the accuracy even in a low power supply voltage and a fine process. Therefore, a good mutual conductance compensation circuit can be realized.

  Next, a modification of the current mirror circuit according to the third embodiment of the present invention will be described. FIG. 9 is an explanatory diagram for explaining the configuration of a current mirror circuit 302, which is a modification of the third embodiment of the present invention. Hereinafter, a current mirror circuit 302 according to a modification of the second embodiment of the present invention will be described with reference to FIG.

In the current mirror circuit 302 shown in FIG. 9, the resistor R _s connected to the source terminal of the N-channel transistor M2 in the current mirror circuit 300 shown in FIG. 8 is connected to the source terminal of the P-channel transistor M4. It is a thing.

As shown in FIG. 9, the resistor R _s is connected to the source terminal of the P-channel transistor M4, thereby combining both the transconductance of the P-channel transistor input component amplifier and the resistance load correction. Thus, a mutual conductance compensation circuit can be realized.

  As described above, according to the first to third embodiments of the present invention, by using a double feedback configuration with P-channel transistors and / or N-channel transistors, even in a low power supply voltage and a fine process. Thus, a highly accurate mutual conductance compensation circuit can be realized.

  In the prior art, if the transistor characteristics vary, an error has occurred in the drain voltages of the two transistors connected in the current mirror, but the first to third embodiments of the present invention. According to the above, even if the characteristics of the transistors are varied, the drain voltages of the two transistors connected to the current mirror are also relatively shifted if the variations are approximately the same, and no error occurs in the drain voltage. The accuracy as a current mirror circuit can be increased.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

It is explanatory drawing explaining the structure of the current mirror circuit 100 concerning the 1st Embodiment of this invention. FIG. 2 is a circuit diagram in which transistors M1, M3, M5, and M7 are extracted from the current mirror circuit 100 shown in FIG. It is explanatory drawing explaining the structure of the current mirror circuit 101 which is a modification of the 1st Embodiment of this invention. It is explanatory drawing explaining the structure of the current mirror circuit 200 concerning the 2nd Embodiment of this invention. FIG. 5 is a circuit diagram in which transistors M1, M3, M5, and M7 are extracted from the current mirror circuit 200 shown in FIG. FIG. 10 is an explanatory diagram illustrating a configuration of a current mirror circuit 201, which is a first modification of the second embodiment of the present invention. It is explanatory drawing explaining the structure of the current mirror circuit 202 which is the 2nd modification of the 2nd Embodiment of this invention. It is explanatory drawing explaining the structure of the current mirror circuit 300 concerning the 3rd Embodiment of this invention. It is explanatory drawing explaining the structure of the current mirror circuit 302 which is a modification of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the conventional mutual conductance compensation circuit. It is explanatory drawing which shows the characteristic between the drain-source voltage _Vds and the gate-source voltage _Vds of a transistor.

Explanation of symbols

100, 200, 300 Current mirror circuit

Claims (9)

A semiconductor integrated circuit provided between a first potential line for supplying a power supply voltage and a second potential line having a potential lower than the power supply voltage;
First constant current output means for inputting the power supply voltage and outputting a plurality of first currents having a first current value;
Second constant current output means for inputting the power supply voltage and outputting a plurality of second currents having a second current value;
Adjusting means for adjusting the plurality of first currents and the plurality of second currents so that the first current value and the second current value are equal;
Including
It said adjusting means causes equal to the potential of the plurality of second current flows having the plurality of first current flow potential the second current having the first current value by the differential input Thus, the semiconductor integrated circuit is characterized in that the plurality of first currents and the plurality of second currents are adjusted so that the first current value and the second current value are equal. The first constant current output means includes a first transistor and a second transistor having a source terminal connected to the first potential line and a current mirror connection,
The second constant current output means includes a third transistor and a fourth transistor whose source terminals are connected to the first potential line and are current mirror connected,
The adjusting means includes
A fifth transistor having a drain terminal connected to the drain terminal of the third transistor;
A sixth transistor having a drain terminal connected to the drain terminal of the second transistor and a current mirror connection with the fifth transistor;
A seventh transistor having a drain terminal connected to the drain terminal of the first transistor and a gate terminal connected to the drain terminal of the sixth transistor;
An eighth transistor having a drain terminal connected to the drain terminal of the fourth transistor, a gate terminal connected to the drain terminal of the sixth transistor, and forming a differential pair with the fifth transistor;
The semiconductor integrated circuit according to claim 1, comprising:   The semiconductor integrated circuit according to claim 2, further comprising a resistor connected to a source terminal of the fifth transistor. The first constant current output means includes a first transistor and a second transistor connected in a current mirror,
The second constant current output means includes a third transistor and a fourth transistor connected in a current mirror,
The adjusting means includes
A fifth transistor having a source terminal connected to the first potential line and a drain terminal connected to the drain terminal of the third transistor;
A sixth transistor having a source terminal connected to the first potential line, a drain terminal connected to the drain terminal of the second transistor, and a current mirror connected to the fifth transistor;
The source terminal is connected to the first potential line, the drain terminal is connected to the drain terminal of the first transistor, the gate terminal is connected to the drain terminal of the sixth transistor, and is differential from the sixth transistor. A seventh transistor constituting a pair;
An eighth transistor having a source terminal connected to the first potential line, a drain terminal connected to the drain terminal of the fourth transistor, and a gate terminal connected to the drain terminal of the sixth transistor;
The semiconductor integrated circuit according to claim 1, comprising:   5. The semiconductor integrated circuit according to claim 4, further comprising a first resistor connected to a source terminal of the fourth transistor or a source terminal of the eighth transistor.   The semiconductor integrated circuit according to claim 4, further comprising a second resistor connected to a source terminal of the fifth transistor. A semiconductor integrated circuit provided between a first potential line for supplying a power supply voltage and a second potential line having a potential lower than the power supply voltage;
First constant current output means for inputting the power supply voltage and outputting a plurality of first currents having a first current value;
Second constant current output means for inputting the power supply voltage and outputting a plurality of second currents having a second current value;
First adjusting means for outputting a third current having a third current value equal to the first current value;
Second adjusting means for adjusting the second current value and the third current value to be equal;
Including
Said first adjusting means is equal to the potential of said third current flows with the plurality of first current flow potential said third current having a first current value by the differential input By adjusting, the first current value and the third current value are adjusted to be equal,
It said second adjusting means is equal to said third current flow potential having a plurality of second said current flows potential of the third current value with the second current value by the differential input Thus, the semiconductor integrated circuit is adjusted so that the second current value and the third current value are equal to each other. The first constant current output means includes a first transistor and a second transistor having a source terminal connected to the second potential line and a current mirror connection,
The second constant current output means includes a third transistor and a fourth transistor whose source terminals are connected to the first potential line and are current mirror connected,
The first adjusting means includes
A fifth transistor having a source terminal connected to the first potential line and a drain terminal connected to the drain terminal of the first transistor;
A sixth transistor having a source terminal connected to the first potential line and a current mirror connected to the fifth transistor;
A seventh transistor having a source terminal connected to the first potential line, a gate terminal connected to the drain terminal of the sixth transistor, and a drain terminal connected to the drain terminal of the tenth transistor;
The source terminal is connected to the first potential line, the drain terminal is connected to the drain terminal of the second transistor, the gate terminal is connected to the drain terminal of the sixth transistor, and is differential from the fifth transistor. An eighth transistor constituting a pair;
Including
The second adjusting means includes
A ninth transistor having a drain terminal connected to the drain terminal of the third transistor;
A tenth transistor having a drain terminal connected to the drain terminal of the seventh transistor and a current mirror connection with the ninth transistor;
An eleventh transistor having a drain terminal connected to the drain terminal of the sixth transistor and a gate terminal connected to the drain terminal of the tenth transistor;
A drain terminal connected to the drain terminal of the fourth transistor; a gate terminal connected to the drain terminal of the tenth transistor; a twelfth transistor that forms a differential pair with the ninth transistor;
The semiconductor integrated circuit according to claim 7, comprising: The semiconductor integrated circuit according to claim 7, further comprising a resistor connected to a source terminal of the eleventh transistor or a source terminal of the sixth transistor.

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