CN209201035U - Orthogonal and 45 degree of phase generating circuits - Google Patents

Orthogonal and 45 degree of phase generating circuits Download PDF

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Publication number
CN209201035U
CN209201035U CN201821937494.6U CN201821937494U CN209201035U CN 209201035 U CN209201035 U CN 209201035U CN 201821937494 U CN201821937494 U CN 201821937494U CN 209201035 U CN209201035 U CN 209201035U
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phase
output
clock
adjustable
degree
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刘雄
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Guangzhou Chang Yuhang Mdt Infotech Ltd
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Guangzhou Chang Yuhang Mdt Infotech Ltd
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Abstract

The utility model relates to a kind of orthogonal and 45 degree of phase generating circuits, can be according to the differential signal (0/180) of input, while generating eight output phases (0/45/90/135/180/225/270/315).The circuit has input clock cache module, and the output end of the input clock cache module is connected with capacitor adjustable multi-phase position generator, duty ratio adjustable amplifier, clock hybrid circuit module in turn;Series connection square wave conversion module can be exported in clock hybrid circuit module as needed, to increase the rising and falling edges rate of the clock of output.The leggy generator is adjustable by adjusting capacitor, realizes that wideband leggy generates;The utility model has the advantages that this leggy generation circuit output phase noise is small, the direct error of phase is small, and technique requires simple, small power consumption.

Description

Orthogonal and 45 degree of phase generating circuits
Technical field:
The utility model relates to a kind of circuits, more particularly to a kind of orthogonal and 45 degree of phase generating circuits.
Background technique:
Oscillator refers to a kind of circuit, signal (square wave or the sine of exportable one or more relatively fixed frequencies Wave), output individual signals be Single-end output, export two difference 180 degree phases signal be difference output, output frequency it is steady Fixed degree is generally measured with parameters such as such as phase noises or clock jitter.
What leggy generation circuit referred to is also a kind of circuit, according to the differential signal of input, generates multiple and different phase letters Number circuit.Such as generate 0 degree, 90 degree, the signal of the signal or more eight phases of 180 degree and 270 degree of four phases Deng;The signal of multiple phases is widely used in radio-frequency front-end, the fields such as high-speed serial digital communication.
Existing leggy generation circuit commonly relies on oscillator itself to generate multiple phases, such as using annular voltage-controlled Oscillator etc.;But frequency stability or the phase noise that can generate the output of the oscillator of leggy are poor.Another Method be allow oscillator operate in twice perhaps the output of higher frequency by except two or except generated after four equal dividers with Leggy;Its major defect is that oscillator and divider is needed to operate in twice, four times or higher frequency, to technique It is required that high, power consumption is big.
Summary of the invention:
The stable and small phase noise multiphase technical problem to be solved by the utility model is to provide a kind of output frequency Position generation circuit.
In order to solve the above-mentioned technical problem, the utility model is achieved through the following technical solutions: having input clock The output end of cache module (1), the input clock cache module (1) is connected with capacitor adjustable multi-phase position generator (2) in turn / duty ratio adjustable amplifier (3)/clock hybrid circuit module (4) and square wave conversion module (5).
The input signal of the circuit is differential signal I0/I180, after input-buffer, the signal of adjustable output The rising edge of B0/B180 and failing edge time and signal swing.Capacitor adjustable multi-phase position generator (3) passes through resistance-capacitance network Delay coherent signal appropriate realizes that four road phase signals export F0/F90/F180/F270.The four roads phase signal is by accounting for After sky amplifies than adjustable amplifier (3) and corrects duty ratio, four road phase signal P0/P90/P180/ being exaggerated are generated P270.By appropriately arranging the input signal phase of eight groups of clock hybrid circuits, it can produce eight tunnel output phase signal J0/J45/ J90/J135/J180/J225/J270/J315.The output rising edge of the eight roads signal and failing edge time are bigger, Ke Yigen According to needs and circuit load, eight groups of square wave conversion modules of connecting optimize output signal O0/O45/O90/O135/O180/O225/ O270/O315 output rising edge and failing edge time).
It is emphasized that: it is made by the above technical examples according to the technical essence of the present invention any simply to repair Change/equivalent variations and modification, be still within the scope of the technical solutions of the present invention.For example square wave conversion is omitted in Fig. 2 Duty ratio adjustable amplifier (3) and square wave conversion module (5) is omitted in Fig. 3 in module (5),
Compared with prior art, the benificial effect of the utility model is to this its oscillator of leggy generation circuit exports Frequency stabilization, phase noise is small, and technique requires simple, small power consumption.
Detailed description of the invention:
The present invention will be further described with reference to the accompanying drawing.
Fig. 1 is orthogonal and 45 degree of phase generating circuit circuit structure block diagrams.
Fig. 2 is the schematic diagram that square wave conversion module is omitted.
Fig. 3 is the schematic diagram that duty ratio adjustable amplifier and square wave conversion module is omitted.
Fig. 4 is input clock buffer circuit figure.
Fig. 5 is capacitor adjustable multi-phase position generator circuitry figure.
Fig. 6 is the specific implementation exemplary diagram of variable capacitance.
Fig. 7 is the circuit diagram of duty ratio adjustable amplifier and square wave conversion module.
Fig. 8 is clock hybrid circuit figure.
In figure: 1/ input clock cache module, 2/ capacitor adjustable multi-phase position generator, 3/ duty ratio adjustable amplifier, 4/ Clock hybrid circuit module, 5/ square wave conversion module.
Specific embodiment:
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Fig. 4 is input clock buffer circuit, and wherein MP1 and MN1 amplify input signal.The size of MP1 and MN1 pipe Size determines amplification factor and power consumption.In view of the amplification factor under different utilizations and frequency input signal, needed needs It adjusts, therefore, MP2/MN2 pipe can control whether to participate in signal amplification by MPSEL/NSEL pipe.When PENB has to be low Effect, when NEN is high effective, MPSEL and NSEL conducting, MP2/MN2 participate in signal amplification, and amplification factor becomes larger, and power consumption becomes larger.It can Increase the adjustable extent of amplification factor with more MPSEL/MP2/MN2/MNSEL in parallel.
Fig. 5 is capacitor adjustable multi-phase position generator.Input signal A0/A180 generates four tunnels after resistance-capacitance network Phase signal B0/B90/B180/B270.But this four roads phase signal direct phase error is in a specific frequency It is accurate, such as in the case where 2G input clock.If the leggy generation circuit needs to cover certain range, such as 2G-4G can detect according to the input of user or by feedback, adjust the size of capacitor to realize.
The specific implementation of variable capacitance is demonstrated in Fig. 6, and C0 is a fixed capacitor, and C1/C2/C3 can be according to user Input (PSELB<3:0>/NSEL<3:0>) control whether to access, to realize that capacitor can be adjusted from C0 to C0+C1+C2+C3 Section.General C1/C2/C3 is multiple proportion, such as 10f/20f/40f.
Circuit shown in Fig. 7 can be used in duty ratio adjustable amplifier (3) and square wave conversion module (5).Wherein feedback resistance is protected MP1/MN1 work has been demonstrate,proved in automatic biasing state, if the size of MP1/MN1 by PMOS/NMOS it is mobility-optimized after, the circuit 50% duty ratio can be achieved and simultaneously amplify signal.
Circuit shown in Fig. 8 can be used in clock hybrid circuit.Wherein input signal IN drives MP1/MN1, input signal INB Drive MP2/MN2.It is input IN/INB since the output of MP1/MN1/MP2/MN2 is connected together as OUT, output signal OUT The inversion signal of intermediate phase.For example input signal is 0 degree and 90 degree of signals, the reverse phase that output signal is 45 degree.If input Signal IN and INB are the same signals, then output is the reverse phase of the signal, for example input signal is 0 degree and 0 degree, output signal It is 0 degree of reverse phase.Signal connects as shown in connection with fig. 1, the input/output relation of eight groups of clock hybrid circuits are as follows:
WhereinIndicate clock hybrid manipulation.
It is emphasized that: the above is only the preferred embodiment of the present utility model, not appoints to the utility model What formal limitation, any simple modification made by the above technical examples according to the technical essence of the present invention/etc. With variation and modification, it is still within the scope of the technical solutions of the present invention.

Claims (2)

1. a kind of orthogonal and 45 degree of phase generating circuits, it is characterised in that: there is the circuit differential signal to input I0/I180, tool Have input clock cache module (1), the output end of the input clock cache module (1) is connected with capacitor adjustable multi-phase position in turn It is defeated to generate eight roads for generator (2)/duty ratio adjustable amplifier (3)/clock hybrid circuit module (4) and square wave conversion module (5) Phase signal O0/O45/O90/O135/O180/O225/O270/O315 out.
2. according to claim 1 orthogonal and 45 degree of phase generating circuits, it is characterised in that: capacitor adjustable multi-phase position Generator (2) at least capacitor is adjustable to extend the applicable frequency range of the circuit.
CN201821937494.6U 2018-11-26 2018-11-26 Orthogonal and 45 degree of phase generating circuits Active CN209201035U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201821937494.6U CN209201035U (en) 2018-11-26 2018-11-26 Orthogonal and 45 degree of phase generating circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201821937494.6U CN209201035U (en) 2018-11-26 2018-11-26 Orthogonal and 45 degree of phase generating circuits

Publications (1)

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CN209201035U true CN209201035U (en) 2019-08-02

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