CN101924553B

CN101924553B - Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure

Info

Publication number: CN101924553B
Application number: CN2010102818789A
Authority: CN
Inventors: 梅年松; 洪志良
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2010-09-15
Filing date: 2010-09-15
Publication date: 2012-06-13
Anticipated expiration: 2030-09-15
Also published as: CN101924553A

Abstract

The invention belongs to the technical field of clock frequency division, in particular relates to a divide-by-2 frequency divider structure based on a standard complementary metal oxide semiconductor (CMOS) process and suitable for an ultra-wide band. The divide-by-2 frequency divider consists of two primary and secondary differential analog D latches, wherein each D latch is a dynamic bias taking a pair of differential N-channel metal oxide semiconductor (NMOS) tubes as an amplifying part, a pair of crossly coupled positive feedback NMOS tubes as a latching part, a pair of p-channel metal oxide semiconductor (PMOS) tubes as a load and a pair of clocked NMOS tubes as the amplifying part and the latching part respectively; the magnitude of the bias voltage of the PMOS tubes changes along with frequencies; and a frequency-voltage converting circuit provides a bias for the PMOS tube load. The divide-by-2 frequency divider structure can effectively increase the working frequency range of a frequency divider; and the ratio of an upper limit frequency to a lower limit frequency of the divide-by-2 frequency divider structure can reach about 250. The circuit of the invention has the characteristics of low power consumption and noise, high speed and the like.

Description

CMOS ultra-wideband frequency divider structure

Technical Field

The invention belongs to the technical field of clock frequency division, and particularly relates to a frequency divider structure suitable for an ultra wide band based on a standard CMOS (complementary metal oxide semiconductor) process.

Background

With the development of broadband wireless communication technology, high-performance clock circuits are becoming the bottleneck of the deep development of the technology. The high-frequency divider is one of key modules of the high-frequency synthesizer, and has the main functions of dividing the highest clock of the system by two and outputting a quadrature I, Q signal according to requirements. In addition, it may divide the high speed non-50% duty cycle signal by two to a 50% duty cycle signal. It not only determines the highest operating frequency of the system, but its performance will directly affect the phase noise and power consumption of the phase locked loop circuit, etc.

Currently, the mainstream frequency dividers include the following three types: 1) current mode latch type (CML) (otherwise known as Source Coupled Logic (SCL)); 2) injection locking type; 3) a regenerative type. Compared with the other two structures, the CML structure has a relatively wide working frequency band, and not only has a good effect of inhibiting the in-band noise. CML structures are therefore most widely used.

The load of the conventional CML structure is mainly composed of two types: 1) fixed load (resistance, MOS transistor in linear operation); 2) and (4) dynamic loading. It is due to the use of such a load that the CML has a relatively narrow band operation bandwidth and high power consumption.

Disclosure of Invention

The invention aims to provide a binary frequency divider based on a CMOS (complementary metal oxide semiconductor) process and suitable for an ultra-wideband.

The circuit structure of the frequency divider suitable for the ultra-wideband comprises two master-slave structure differential analog D latches, and the two D latches are connected into a negative feedback form, as shown in figure 2. The inputs of which are differential signals, see the figure

Figure 2010102818789100002DEST_PATH_IMAGE001

And

can beThe signal may be a sine wave signal or a square wave signal.

In the invention, two D latches are composed of 8 MOS tubes M1-M8, wherein, the seventh and eighth MOS tubes M7 and M8 form an amplifying tube, which works in the following phase of the clock, namely the positive half period of the signal CK, and the grid electrode of the amplifying tube is connected with the input signal; the fifth MOS tube M5 and the sixth MOS tube M6 form a latch tube, and work in the latch phase of the clock, namely the negative half period of the signal CK; the first MOS tube M1 and the second MOS tube M2 form a pair of dynamic loads changing along with frequency, and form a common source differential amplification circuit together with the amplification tube to provide certain gain; the third MOS transistor M3 forms the dynamic bias of a logic part and works in the following phase of the clock; the fourth MOS transistor M4 constitutes a dynamic bias of the latch part and operates in the latch phase of the clock. The fourth MOS transistor M4 reduces the dynamic range of the output node, and is beneficial to reducing power consumption.

In the invention, a frequency to voltage conversion circuit is also provided. When the frequency-to-voltage conversion circuit works, a voltage is output to the first M1 and the second M2 tubes according to the frequency of an input signal to provide bias, and the magnitude of the output voltage changes along with the frequency.

The frequency-to-voltage conversion circuit consists of a resistor R1, a capacitor C1, a diode D1, a resistor R2, a capacitor C2, a capacitor C3 and a resistor R3; the resistor R1 and the capacitor C1 form a low-pass filter, and the amplitude of the output voltage is related to the frequency of the input signal; the diode D1, the resistor R2 and the capacitor C2 complete the alternating current-direct current conversion function; the capacitor C3 is a DC blocking capacitor, and the resistor R3 is an AC signal blocking resistor, and provides DC voltage.

The RC constant of the output node is reduced by reducing the load at high frequency, so that the highest working frequency of the circuit is improved; and at low frequency, the RC constant of the output node is increased by increasing the load, so that the lowest working frequency of the circuit is reduced. The working frequency range of the frequency divider is effectively increased by the technology, and the upper limit frequency ratio and the lower limit frequency ratio can reach about 250. The circuit of the invention has the performances of low power consumption, low noise, high speed and the like.

The invention has the following beneficial effects:

1. the working frequency range of the frequency halver can be effectively widened;

2. the frequency divider can work in a frequency range from hundred MHz to dozens of GHz;

3. the performance such as power consumption, noise, broadband, speed and the like can be well compromised;

4. the method can bring convenience to the design of a broadband wireless communication system, in particular to an ultra-wideband system.

Drawings

FIG. 1 is a block diagram of a divide-by-two divider of a CML architecture.

FIG. 2 is a timing diagram of a divide-by-two divider of the CML architecture.

FIG. 3 is a specific circuit diagram of the frequency divider of the present invention.

FIG. 4 is a circuit diagram of the follower phase of the frequency divider of the present invention.

FIG. 5 is a circuit diagram of a latch phase of a frequency divider of the present invention.

FIG. 6 is a circuit diagram of the frequency-to-voltage conversion of the divide-by-two frequency divider of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of a CML-structured divide-by-two divider. The structure comprises two master-slave structure differential D latches which are connected into a negative feedback form, and an input clock is a differential signal

Andit may be sinusoidal or square wave signal. Two pairs of quadrature differential signals are output:

Figure 2010102818789100002DEST_PATH_IMAGE003

and

，and

. During the positive half cycle of the clock, the master latch operates in a following state, the output of which

、

Follow-up input

、

(ii) a The slave latch works in a latch state, the output of the slave latch is kept unchanged and is the output of the previous clock phase

、

. In the negative half period of the clock, the main latch works in the latch state, the output of the main latch is kept unchanged and is the output of the previous clock phase

、(ii) a The slave latch operating in a follower state and having its output

、

Follow-up input

、

。

FIG. 2 is a timing diagram of FIG. 1 with output signals

、

And

、

are orthogonal to each other and have frequencies equal to the input signal

、

Half of that.

Fig. 3 is a specific circuit diagram of the novel frequency divider provided by the present invention. The MOS tubes M7 and M8 form a logic part, work in the following phase of a clock, namely the positive half period of a CK signal, and the grid electrodes of the MOS tubes are connected with an input signal; the MOS tubes M5 and M6 form a latch part and work in a latch phase of a clock, namely a negative half period of a CK signal; MOS tubes M1 and M2 form a pair of dynamic loads changing along with frequency, and form a common source differential amplification circuit together with a logic part to provide certain gain; the MOS transistor M3 forms the dynamic bias of a logic part and works in the following phase of the clock; the MOS transistor M4 constitutes the dynamic bias of the latch part and works in the latch phase of the clock. The MOS transistor M4 reduces the dynamic range of the output node, is beneficial to reducing power consumption and improving working frequency.

Fig. 4 is a circuit diagram of the following phase of the novel frequency divider provided by the invention. At the moment, the MOS tube M7 or M8 works, the MOS tubes M1 and M2 work, and the rest of the tubes do not work. This circuit constitutes an amplifier, making the output follow the input.

Fig. 5 is a circuit diagram of a latch phase of the novel frequency divider provided by the present invention. At the moment, the MOS tube M5 or M6 works, the MOS tubes M1 and M2 work, and the rest of the tubes do not work. The circuit forms a positive feedback structure to latch the output signal and keep it unchanged. The MOS transistor M4 is used for adjusting the swing amplitude of the output node, saving power consumption and improving working frequency.

Fig. 6 is a circuit diagram of frequency-to-voltage conversion of the novel frequency divider provided by the present invention. The resistor R1 and the capacitor C1 form a low-pass filter, and the amplitude of the output voltage is related to the frequency of the input signal; the diode D1, the resistor R2 and the capacitor C2 complete the alternating current-direct current conversion function; the capacitor C3 is a DC blocking capacitor, and the resistor R3 is an AC signal blocking resistor, and provides DC voltage.

Claims

1. A CMOS ultra-wideband frequency halver structure is characterized in that the structure comprises two master-slave structure differential analog D latches, and the two D latches are connected into a negative feedback form; its inputs are differential signals:andas a sine wave signal, orA square wave signal; wherein,

the D latch is composed of 8 MOS transistors M1-M8; the seventh MOS transistor M7 and the eighth MOS transistor M8 form an amplifier transistor, which operates in the following phase of the clock, that is, the positive half period of the signal CK, and the gate of the amplifier transistor is connected to the input signal; the fifth MOS transistor M5 and the sixth MOS transistor M6 form a latch transistor, and work in a latch phase of a clock, namely a negative half period of the signal CK; the first MOS transistor M1 and the second MOS transistor M2 form a pair of dynamic loads changing along with frequency, and form a common source differential amplification circuit together with the amplification transistor, so that a certain gain is provided; the third MOS transistor M3 forms the dynamic bias of a logic part and works in the following phase of the clock; the fourth MOS transistor M4 forms the dynamic bias of the latch part and works in the latch phase of the clock;

the CMOS ultra-wideband frequency divider structure also comprises a frequency-to-voltage conversion circuit; when the frequency-to-voltage conversion circuit works, the frequency output voltage of the input signal provides bias for the first MOS transistor M1 and the second MOS transistor M2, and the magnitude of the output voltage changes along with the frequency;

the frequency-to-voltage conversion circuit consists of a resistor R1, a capacitor C1, a diode D1, a resistor R2, a capacitor C2, a capacitor C3 and a resistor R3; wherein, the resistor R1 and the capacitor C1 form a low-pass filter; the diode D1, the resistor R2 and the capacitor C2 complete the alternating current-direct current conversion function; the capacitor C3 is a DC blocking capacitor, and the resistor R3 is an AC signal blocking resistor, and provides DC voltage.