CN115694527A - Four-level pulse amplitude modulation high-speed serial port transmitter structure based on DAC - Google Patents
Four-level pulse amplitude modulation high-speed serial port transmitter structure based on DAC Download PDFInfo
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Abstract
The invention provides a DAC-based four-level pulse amplitude modulation high-speed serial transmitter structure, a high-speed serial transmitter and electronic equipment, and relates to the field of integrated circuit design. The low-speed digital combiner receives the multi-channel parallel low-speed non-return-to-zero code data signals and combines the signals to generate 8 channels of high-speed non-return-to-zero code data signals and transmits the signals to the four-level pulse amplitude modulation module; the four-level pulse amplitude modulation module receives 8 paths of high-speed non-return-to-zero code data signals, converts the signals into 4 paths of four-level pulse amplitude modulation signals and transmits the signals to the analog combining module; the analog combining module receives and combines 4 paths of four-level pulse amplitude modulation signals, and performs 2-tap feed-forward equalization to generate and output 1 path of serial high-speed data signals. The invention adopts the analog combiner to combine data and simultaneously realizes feed-forward balance. The high-speed combiner has the advantages of high working speed, high combining speed, bandwidth expansion, simplified structure, small area and low power consumption, and reduces the parasitic capacitance of the output node.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a DAC (digital-to-analog converter) -based four-level pulse amplitude modulation high-speed serial transmitter structure, a high-speed serial transmitter and electronic equipment.
Background
With the continuous progress of information technology, the demand of users for data transmission rate is increasing. For interfaces between electronic devices, it is desirable to minimize the occupation of physical resources while requiring high transmission rates, and high-speed serial interface (SerDes) technology is a suitable solution.
The design of the transmitting end of the high-speed serial port circuit is always a popular research direction in wired transmission, and in recent years, with the continuous evolution of process nodes and the proposal of a new circuit structure, the single-channel data rate has a trend of doubling every three to four years.
Technically, the circuit structure of the existing high-speed serial port circuit transmitter is relatively uniform, and the transmitter mainly comprises a combiner, an output driving circuit and a feed-forward equalization (FFE) circuit. The transmitter has the main function of combining low-speed parallel data to generate high-speed serial data through a series of combiners, and the general realization mode of the combiners is based on a multiplexer gated by an MOS switch, and different data are gated through a clock signal to complete the function of combining. This is done using digital circuitry and has the disadvantage that it is difficult to operate at very high frequencies due to the MOS switching rate limitations.
Since the output stage operates at the highest speed and needs to drive a large load, the transmitter needs to specially design the output stage circuit, and the general practice is based on the output stage of the DAC, and the specific implementation is mainly divided into CML driving and SST voltage driving. The conventional DAC output stage has the disadvantages that a large number of driving circuit arrays need to be integrated at the output node, a large parasitic capacitance is introduced, and a large area is needed. In order to improve the transmission quality of the output signal in the channel, a feed forward equalization at the transmitter is required.
The conventional method of feed-forward equalization is to retime multiple paths of parallel data into multiple taps, and perform weighted summation on the data of different paths in the DAC of the output stage, so as to obtain and output the equalized signal. This approach requires a large data path and also requires a high linearity requirement for the output stage DAC. With the evolution of process nodes, much work has been done in recent years to put feed-forward equalization into the DSP for implementation. The advantage of this is to put the complicated logic function to realize in the digital domain, reduce the difficulty of the design of the full customization circuit, but the disadvantage is that the data of 1 bit after the equalization will become many bits, will produce a large amount of parallel data links, increase the scale of the circuit.
Disclosure of Invention
In view of the above, the present invention has been made to provide a DAC-based four-level pulse amplitude modulation high-speed serial transmitter structure, a high-speed serial transmitter, and an electronic device that solve the above problems or partially solve the above problems.
The first aspect of the embodiments of the present invention provides a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter structure, where the four-level pulse amplitude modulation high-speed serial port transmitter structure includes: the device comprises a low-speed digital combiner, a four-level pulse amplitude modulation module, an analog combiner module and a clock generation module;
the low-speed digital combiner receives the multi-channel parallel low-speed non-return-to-zero data signals, combines the multi-channel parallel low-speed non-return-to-zero data signals to generate 8 channels of high-speed non-return-to-zero data signals and transmits the signals to the four-level pulse amplitude modulation module;
the four-level pulse amplitude modulation module receives the 8-path high-speed non-return-to-zero code data signal, converts the 8-path high-speed non-return-to-zero code data signal into 4-path four-level pulse amplitude modulation signals and transmits the signals to the analog combining module;
the analog combining module receives the 4 paths of four-level pulse amplitude modulation signals, combines the signals, performs feed-forward equalization of 2-tap, and generates and outputs 1 path of serial high-speed data signals;
the clock generation module is respectively connected with the low-speed digital combiner and the analog combiner module, and is used for providing clock signals for the low-speed digital combiner and the analog combiner module;
and the 1-path serial high-speed data signal output by the analog combining module is output outside the chip after bandwidth expansion by using an inductance peaking technology.
Optionally, the analog combining module includes: a first 2;
the first 2;
the first 2;
the second 2;
the first return-to-zero code generating unit converts the four-level pulse amplitude modulation signal with the higher frequency of the 1 st path into a first return-to-zero code signal and transmits the first return-to-zero code signal to the return-to-zero code summing unit;
the second return-to-zero code generating unit converts the four-level pulse amplitude modulation signal with the higher frequency of the 2 nd path into a second return-to-zero code signal and transmits the second return-to-zero code signal to the return-to-zero code summing unit;
and the return-to-zero code summation unit carries out staggered addition on the first return-to-zero code signal and the second return-to-zero code signal to obtain the 1-path serial high-speed data signal.
Optionally, the 2 paths of four-level pulse amplitude modulation signals are 2 paths of differential data signals;
the first 2: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor;
the first end of the first MOS tube and the first end of the second MOS tube respectively receive one path of differential data signals in the 2 paths of differential data signals, and the first end of the third MOS tube and the first end of the fourth MOS tube respectively receive the other path of differential data signals in the 2 paths of four-level pulse amplitude modulation signals;
the second end of the first MOS tube is connected with the second end of the third MOS tube, and the fourth-level pulse amplitude modulation signal with the higher frequency of the 1 st path is output;
the third end of the first MOS tube is connected with the third end of the second MOS tube, and both the third end of the first MOS tube and the third end of the second MOS tube are connected with the second end of the fifth MOS tube;
the second end of the second MOS tube is connected with the second end of the fourth MOS tube, and outputs a four-level pulse amplitude modulation signal with higher frequency in the 1 st path;
the third end of the third MOS tube is connected with the third end of the fourth MOS tube and both connected with the second end of the sixth MOS tube;
the first end of the fifth MOS tube and the first end of the sixth MOS tube receive the clock signal respectively, and the clock signal is a differential clock signal;
the third end of the fifth MOS tube is connected with the third end of the sixth MOS tube, and both are connected with a first current source and are grounded through the first current source;
after the second end of the first MOS tube is connected with the second end of the third MOS tube, the second end of the first MOS tube is also connected with a first power supply through a group of resistors and inductors which are connected in series;
and after the second end of the second MOS tube is connected with the second end of the fourth MOS tube, the second end of the second MOS tube is also connected with a second power supply through a group of resistors and inductors which are connected in series.
Optionally, both the 1 st path of higher-frequency four-level pulse amplitude modulation signal and the 2 nd path of higher-frequency four-level pulse amplitude modulation signal are differential input signals;
the first return-to-zero code generating unit and the second return-to-zero code generating unit have the same structure, and the first return-to-zero code generating unit includes: a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube; a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube and an eighteenth MOS tube;
the first end of the seventh MOS transistor, the first end of the eighth MOS transistor, the first end of the ninth MOS transistor, the first end of the tenth MOS transistor, the first end of the eleventh MOS transistor, the first end of the twelfth MOS transistor, the first end of the thirteenth MOS transistor, and the first end of the fourteenth MOS transistor all receive the differential input signal;
a second end of the seventh MOS transistor, a second end of the tenth MOS transistor, a second end of the eleventh MOS transistor, and a second end of the fourteenth MOS transistor are all connected, and the first return-to-zero code signal is output;
a second end of the eighth MOS transistor, a second end of the ninth MOS transistor, a second end of the twelfth MOS transistor, and a second end of the thirteenth MOS transistor are all connected, and the first return-to-zero code signal is output;
the third end of the seventh MOS tube is connected with the third end of the eighth MOS tube, and both the third end of the seventh MOS tube and the third end of the eighth MOS tube are connected with the second end of the fifteenth MOS tube;
the third end of the ninth MOS tube is connected with the third end of the tenth MOS tube, and both the third end of the ninth MOS tube and the third end of the tenth MOS tube are connected with the second end of the sixteenth MOS tube;
the third end of the eleventh MOS transistor is connected with the third end of the twelfth MOS transistor, and both the third end of the eleventh MOS transistor and the third end of the twelfth MOS transistor are connected with the second end of the seventeenth MOS transistor;
the third end of the thirteenth MOS tube is connected with the third end of the fourteenth MOS tube, and both the third ends are connected with the second end of the eighteenth MOS tube;
the first end of the fifteenth MOS tube and the first end of the sixteenth MOS tube receive the clock signal respectively;
a first end of the seventeenth MOS tube and a first end of the eighteenth MOS tube respectively receive bias voltage;
the third end of the fifteenth MOS tube is connected with the third end of the sixteenth MOS tube, both the third end of the fifteenth MOS tube and the third end of the sixteenth MOS tube are connected with a second current source, and the fifteenth MOS tube and the sixteenth MOS tube are grounded through the second current source;
the third end of the seventeenth MOS tube is connected with the third end of the eighteenth MOS tube, and both the seventeenth MOS tube and the eighteenth MOS tube are connected with a third current source and grounded through the third current source;
after the second end of the seventh MOS tube, the second end of the tenth MOS tube, the second end of the eleventh MOS tube and the second end of the fourteenth MOS tube are connected, the seventh MOS tube is connected with a third power supply through a group of resistors and inductors which are connected in series;
and after the second end of the eighth MOS tube, the second end of the ninth MOS tube, the second end of the twelfth MOS tube and the second end of the thirteenth MOS tube are connected, the second end of the eighth MOS tube, the second end of the ninth MOS tube and the second end of the thirteenth MOS tube are connected with a fourth power supply through a group of resistors and inductors which are connected in series.
Optionally, the low-speed digital combiner adopts a serial port technology for processing, and a function of combining the multiple parallel low-speed non-return-to-zero data signals into 8 high-speed non-return-to-zero data signals is realized in a multi-stage combiner cascade mode;
the cascade stage number of the cascade of the multistage combiner is determined by the number of the multipath parallel low-speed non-return-to-zero code data signals.
Optionally, the four-level pulse amplitude modulation module includes: the differential amplifier comprises two groups of differential amplifiers with adjustable tail current sources, wherein the tail current of a differential pair corresponding to the MSB is twice as large as that of a differential pair corresponding to the LSB;
and the two groups of differential amplifiers with CML structures are connected to the same output, and the voltage generated by the two paths of current flowing through the load is the converted 4 paths of four-level pulse amplitude modulation signals.
Optionally, the clock generation module includes: the circuit comprises a driver, a frequency divider and a phase interpolator, wherein the frequency divider is used for generating a low-speed clock from a high-speed clock, and the phase interpolator is used for adjusting the relative phase of the clocks between different cascaded combiners.
Optionally, the multiple parallel low-speed non-return-to-zero-code data signals are 160 parallel low-speed non-return-to-zero-code data signals generated by a pseudo-random binary sequence signal source.
A second aspect of the embodiments of the present invention provides a high-speed serial port transmitter, where the high-speed serial port transmitter includes the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter structure according to any one of the first aspect.
A third aspect of an embodiment of the present invention provides an electronic device, where the electronic device includes the DAC-based four-level pulse amplitude modulation high-speed serial transmitter structure according to any one of the first aspect.
The invention provides a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter structure, which comprises: the device comprises a low-speed digital combiner, a four-level pulse amplitude modulation module, an analog combiner module and a clock generation module. The low-speed digital combiner receives the multi-channel parallel low-speed non-return-to-zero data signals, combines the signals, generates 8 channels of high-speed non-return-to-zero data signals and transmits the signals to the four-level pulse amplitude modulation module.
The four-level pulse amplitude modulation module receives 8 paths of high-speed non-return-to-zero code data signals, converts the signals into 4 paths of four-level pulse amplitude modulation signals and transmits the signals to the analog combining module; the analog combining module receives 4 paths of four-level pulse amplitude modulation signals, combines the signals, performs feed-forward equalization of 2-tap, and generates 1 path of serial high-speed data signals for output.
The clock generation module is respectively connected with the low-speed digital combiner and the analog combiner module and is used for providing clock signals for the low-speed digital combiner and the analog combiner module; the 1-channel serial high-speed data signal output by the analog combining module is output outside the chip after bandwidth expansion by using an inductance peaking technology.
The invention discloses a structure of a four-level pulse amplitude modulation high-speed serial port transmitter, and provides a novel PAM4 (four-level pulse amplitude modulation) high-speed serial port transmitter architecture based on a DAC (digital-to-analog converter).
The four-level pulse amplitude modulation high-speed serial port transmitter structure is high in working rate, compared with a traditional digital combiner, the analog combining DAC architecture has the advantages that a CML differential pair is used, the switching speed is increased, and higher combining rate can be achieved. Meanwhile, the simple output stage structure is easier to integrate the inductor at the load end, and the bandwidth can be further expanded by utilizing an inductor peaking technology. Through simulation verification, the framework can realize the output data rate of 144Gb/s under the 65nm CMOS process, and is equivalent to the world advanced result under the FinFET process. The higher transistor cut-off frequency, the faster switch turn-on speed and the shorter routing distance in the advanced process can further improve the highest working speed of the architecture.
The structure of the four-level pulse amplitude modulation high-speed serial transmitter is simplified, the area is small, and a large number of retiming circuits and a large number of parallel data paths are needed in the traditional serial transmitter architecture to realize the function of feed-forward equalization. The feedforward equalization framework based on the analog combiner can reduce the number of parallel data paths, simplify the structure of a transmitter, avoid integrating a large-scale transistor array at an output stage and reduce the parasitic capacitance of an output node.
The four-level pulse amplitude modulation high-speed serial port transmitter structure has low power consumption, and the feed-forward equalization framework reduces the number of parallel data paths, so that the power consumption on the corresponding data paths is saved. At the same time, the smaller data path load reduces the requirements for clock driving, while reducing the power consumption of the clock driving.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive labor.
Fig. 1 is a schematic diagram of a structure of a DAC-based four-level pwm high-speed serial transmitter according to an embodiment of the present invention;
FIG. 2 is a more detailed block diagram of an embodiment of the present invention;
fig. 3 is a detailed modular schematic diagram of an analog combining module ACM according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a preferred first 2;
fig. 5 is a schematic circuit diagram of a preferred first return-to-zero code generating unit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter structure, which comprises: the device comprises a low-speed digital combiner, a four-level pulse amplitude modulation module, an analog combiner module and a clock generation module.
The low-speed digital combiner receives a plurality of paths of parallel low-speed non-return-to-zero (NRZ) data signals, combines the NRZ data signals to generate 8 paths of high-speed NRZ data signals and transmits the NRZ data signals to the four-level pulse amplitude modulation module; and then the four-level pulse amplitude modulation module receives the 8-path high-speed NRZ data signal, converts the 8-path high-speed NRZ data signal into 4-path four-level pulse amplitude modulation (PAM 4) signals and transmits the signals to the analog combining module.
And finally, the analog combining module receives 4 paths of PAM4 signals, combines the signals, performs feed-forward equalization of 2-tap, and generates and outputs 1 path of serial high-speed data signals. The 1-channel serial high-speed data signal output by the analog combining module can be output outside the chip after bandwidth expansion by using an inductance peaking technology. The clock generating module is respectively connected with the low-speed digital combiner and the analog combiner module, and is used for providing clock signals for the low-speed digital combiner and the analog combiner module.
Referring to fig. 1, a modular schematic diagram of a structure of a DAC-based four-level pwm high-speed serial transmitter according to the present invention is shown schematically. The low-speed digital combiner LSDC in fig. 1 receives multiple parallel low-speed NRZ data signals (in fig. 1, the multiple parallel low-speed NRZ data signals are represented by NRZ), combines the multiple parallel low-speed NRZ data signals, generates 8 high-speed NRZ data signals, and transmits the data signals to the four-level pulse amplitude modulation module PAM4.
The four-level pulse amplitude modulation module PAM4 receives 8-path high-speed NRZ data signals, converts the 8-path high-speed NRZ data signals into 4-path PAM4 signals, and transmits the signals to the analog combining module ACM. The analog combining module ACM receives the 4 paths of PAM4 signals, combines the 4 paths of PAM4 signals, performs feed-forward equalization of 2-tap, generates 1 path of serial high-speed data signals, and outputs the 1 path of serial high-speed data signals, which is denoted by OUT in fig. 1. The clock generation module CGM is connected to the low-speed digital combiner LSDC and the analog combining module ACM, respectively, receives an input of a reference clock CLK, and generates a clock signal for supplying to the low-speed digital combiner LSDC and the analog combining module ACM.
In the embodiment of the invention, the low-speed digital combiner LSDC can realize the functions thereof in various ways, and a better method is to adopt a serial port technology for processing, and the function of synthesizing 8-way high-speed NRZ data signals from a plurality of paths of parallel low-speed NRZ data signals can be realized in a multi-stage combiner cascading way; the cascade stage number of the cascade of the multi-stage combiner is determined by the number of the multi-path parallel low-speed NRZ data signals.
The four-level pulse amplitude modulation module PAM4 can also implement its functions in a variety of ways, one preferred way being: the four-level pulse amplitude modulation module PAM4 is composed of two groups of differential amplifiers with adjustable tail current sources, wherein the tail current of a differential pair corresponding to the MSB is twice as large as the tail current of a differential pair corresponding to the LSB; and the two groups of differential amplifiers with CML structures are connected to the same output, and the voltage generated by the two paths of current flowing through the load is the converted 4 paths of PAM4 signals.
The clock generation module CGM can also implement its function in multiple ways, one preferred way is: the clock generation module CGM includes: the circuit comprises a driver, a frequency divider and a phase interpolator, wherein the frequency divider is used for generating a low-speed clock from a high-speed clock, and the phase interpolator is used for adjusting the relative phase of the clock between different cascaded combiners.
In the embodiment of the present invention, the multiple parallel low-speed NRZ data signals may be 160 parallel low-speed NRZ data signals generated by a Pseudo-Random Binary Sequence (PRBS) signal source. Taking this type of multi-path parallel low speed NRZ data signal as an example, assuming that the frequency of the reference clock CLK received by the clock generation module CGM is 36GHz, referring to fig. 2, a more detailed modular diagram is exemplarily shown. In fig. 2, the clock generation module CGM generates clock signals of 900MHz, 9GHz, 18GHz, and 36GHz, respectively, and provides the clock signals to the pseudo random binary sequence signal source PRBS, the low speed digital combiner LSDC, and the analog combining module ACM, respectively, where the analog combining module ACM receives the clock signals of 18GHz and 36 GHz.
The pseudo-random binary sequence signal source PRBS is capable of generating 160 parallel PRBS31 sequences in NRZ mode with data rate of 900Mb/s as multiple parallel low speed NRZ data input signals for the low speed digital combiner LSDC. Then, 160 paths of 900Mb/s parallel low-speed NRZ data signals are converted into 8 paths of 18Gb/s high-speed NRZ data signals by 8 parallel 20.
The four-level pulse amplitude modulation module PAM4 receives 8 paths of high-speed NRZ data signals with 18Gb/s, converts the signals and converts the signals into 4 paths of PAM4 signals with 36 Gb/s. The analog combining module ACM receives 4 paths of 36Gb/s PAM4 signals, combines the signals, performs 2-tap feed-forward equalization, generates 1 path of 144Gb/s serial high-speed data signals and outputs the signals.
The analog combining module ACM of the embodiment of the invention has the function of combining 4-1 paths of PAM4 signals and outputting the combined signals. Because the data rate of the part is high, and the traditional serial port technology based on a digital circuit is difficult to work at the rate, the analog combining module ACM in the embodiment of the invention is different from the output-stage circuit and the feedforward equalization mode in the prior art, directly processes the data of the 4 paths of PAM4 signals in an analog domain, adopts the analog combining technology, realizes the feedforward equalization of 2-tap while combining, and replaces the output-stage circuit and the feedforward equalization mode in the prior art.
The analog combining module ACM of the embodiment of the present invention includes: a first 2. The first 2.
A first 2; and the second 2.
The first return-to-zero code generating unit converts the PAM4 signal with higher frequency in the 1 st path into a first return-to-zero code signal and transmits the first return-to-zero code signal to the return-to-zero code summing unit; the second return-to-zero code generating unit converts the 2 nd path of PAM4 signal with higher frequency into a second return-to-zero code signal and transmits the second return-to-zero code signal to the return-to-zero code summing unit.
And the return-to-zero code summation unit carries out staggered addition on the first return-to-zero code signal and the second return-to-zero code signal to obtain 1 path of serial high-speed data signals.
Taking the example that the analog combining module ACM receives 4 paths of 36Gb/s PAM4 signals and combines them, fig. 3 shows a detailed modular schematic diagram of the analog combining module ACM in the embodiment of the present invention. In fig. 3, the first 2: the first 2.
Since the functions of the first return-to-zero code generating unit RZ10 and the second return-to-zero code generating unit RZ20 are completely the same, taking the first return-to-zero code generating unit RZ10 as an example: the first return-to-zero code generation unit RZ10 receives 1 path of 72Gb/s PAM4 signals, converts the 1 path of 72Gb/s PAM4 signals into 72Gb/s RZ signals (i.e., first return-to-zero code signals) based on a 36GHz clock signal, and transmits to the return-to-zero code summation unit RZ +.
The return-to-zero code summation unit RZ + receives 2 paths of RZ signals (namely a first return-to-zero code signal and a second return-to-zero code signal) of 72Gb/s, and performs staggered addition on the 2 paths of RZ signals of 72Gb/s to obtain 1 path of 144Gb/s serial high-speed data signals, thereby completing a combining function and outputting the signals through an output end OUT. In the embodiment of the invention, the final combined path is processed in the analog domain, so that a large-scale array of an output stage circuit is avoided, the parasitic capacitance of the output stage circuit is reduced, and the bandwidth can be expanded by using an inductance peaking technology. In order to expand the bandwidth, a large amount of peaking inductors are used in the clock path in this example, and the inductors are stacked to reduce the area of the chip by taking advantage of the practice in the radio frequency circuit, so as to achieve the compromise between the chip area and the speed.
Taking the detailed structures shown in fig. 2 and fig. 3 as an example, through simulation verification, the output data rate in the 65nm CMOS process can be covered to a low frequency from 144Gb/s, which is equivalent to the world advanced result in the FinFET process. The higher cut-off frequency of the transistor, the faster switch conduction speed and the shorter wiring distance in the advanced process can further improve the highest working speed of the transmitter structure in the embodiment of the invention.
In order to more clearly explain the specific structure of the analog combining module ACM in the embodiment of the present invention, referring to fig. 4 and 5, the circuit structures of the first 2. Since the structures of the first 2.
In fig. 4, a first 2: the MOS transistor comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5 and a sixth MOS transistor M5. The NMOS is shown in fig. 4 as an example, and the junction corresponding to the PMOS transistor can be obtained through simple transformation, which is not described again. The PAM4 signal is a differential data signal.
The first end of the first MOS transistor M1 and the first end of the second MOS transistor M2 respectively receive one of the 2 differential data signals D1P and D1N, and the first end of the third MOS transistor M3 and the first end of the fourth MOS transistor M4 respectively receive the other of the differential data signals D2P and D2N.
The second end of the first MOS transistor M1 is connected to the second end of the third MOS transistor M3, and outputs a PAM4 signal with a higher frequency in the 1 st path, where the PAM4 signal with a higher frequency in the 1 st path is output by the OUTN in fig. 4.
The third end of the first MOS transistor M1 is connected with the third end of the second MOS transistor M2, and both the third end and the third end are connected with the second end of the fifth MOS transistor M5; the second end of the second MOS transistor M5 is connected to the second end of the fourth MOS transistor M4, and outputs the PAM4 signal with the 1 st path higher frequency, and what is output by OUTP in fig. 4 is the PAM4 signal with the 1 st path higher frequency, so that it is known that the PAM4 signal with the 1 st path higher frequency is also a differential signal.
The third end of the third MOS transistor M3 is connected with the third end of the fourth MOS transistor M4, and both the third end and the third end are connected with the second end of the sixth MOS transistor M6; the first end of the fifth MOS transistor M5 and the first end of the sixth MOS transistor M6 receive clock signals CLKP and CLKN, respectively, and the clock signals are also differential clock signals.
The third end of the fifth MOS transistor M5 and the third end of the sixth MOS transistor M6 are connected, and both are connected to the first current source I1, and are grounded through the first current source I1. In addition, after the second end of the first MOS transistor M1 is connected to the second end of the third MOS transistor M3, the first MOS transistor M1 is further connected to a first power supply VDD1 through a set of resistors and inductors connected in series; after the second end of the second MOS transistor M2 and the second end of the fourth MOS transistor M4 are connected, the second MOS transistor M2 is further connected to a second power supply VDD2 through a group of resistors and inductors connected in series.
The differential clock signals CLKP and CLKN control the switches of the two data branches through the two MOS tubes M5 and M6 at the lower side, and the left branch and the right branch are sequentially and alternately conducted. When the left branch is conducted, one path of differential data signals D1P and D1N are transmitted to output through the differential pair, and when the right branch is conducted, the other path of differential data signals D2P and D2N are transmitted to output through the differential pair, so that 2-1 combination is completed.
Fig. 5 shows that the first return-to-zero code generating unit includes: a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, and a twelfth MOS transistor M12; a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, and an eighteenth MOS transistor M18.
The first end of the seventh MOS transistor M7, the first end of the eighth MOS transistor M8, the first end of the ninth MOS transistor M9, the first end of the tenth MOS transistor M10, the first end of the eleventh MOS transistor M11, the first end of the twelfth MOS transistor M12, the first end of the thirteenth MOS transistor M13, and the first end of the fourteenth MOS transistor M14 all receive differential input signals NRZP and NRZN, where the differential input signals NRZP and NRZN are signals output by OUTN and OUTP in fig. 4.
A second end of the seventh MOS transistor M7, a second end of the tenth MOS transistor M10, a second end of the eleventh MOS transistor M11, and a second end of the fourteenth MOS transistor M14 are all connected to output a first return-to-zero code signal.
A second end of the eighth MOS transistor M8, a second end of the ninth MOS transistor M9, a second end of the twelfth MOS transistor M10, and a second end of the thirteenth MOS transistor M13 are all connected to each other, and output a first return-to-zero code signal, where RZN and RZP in fig. 5 jointly form a differential first return-to-zero code signal.
The third end of the seventh MOS transistor M7 is connected with the third end of the eighth MOS transistor M8, and both the third ends are connected with the second end of the fifteenth MOS transistor M15; the third end of the ninth MOS transistor M9 is connected to the third end of the tenth MOS transistor M10, and both are connected to the second end of the sixteenth MOS transistor M16.
A third end of the eleventh MOS transistor M11 is connected with a third end of the twelfth MOS transistor M12, and both the third ends are connected with a second end of the seventeenth MOS transistor M17; the third end of the thirteenth MOS transistor M13 is connected to the third end of the fourteenth MOS transistor M14, and both are connected to the second end of the eighteenth MOS transistor M18.
A first end of a fifteenth MOS transistor M15 and a first end of a sixteenth MOS transistor M16 respectively receive the clock signals CLKP and CLKN; the first end of the seventeenth MOS transistor M17 and the first end of the eighteenth MOS transistor M18 respectively receive the signal V of the bias voltage BIASP And V BIASN 。
The third end of the fifteenth MOS tube M15 is connected with the third end of the sixteenth MOS tube M16, and both are connected with the second current source I2 and are grounded through the second current source I2; the third end of the seventeenth MOS transistor M17 and the third end of the eighteenth MOS transistor M18 are connected, and both are connected to the third current source I3 and grounded through the third current source I3.
In addition, after the second end of the seventh MOS transistor M7, the second end of the tenth MOS transistor M10, the second end of the eleventh MOS transistor M11, and the second end of the fourteenth MOS transistor M14 are all connected, the seventh MOS transistor M7 is further connected to the third power supply VDD3 through a set of resistors and inductors connected in series; after the second end of the eighth MOS transistor M8, the second end of the ninth MOS transistor M9, the second end of the twelfth MOS transistor M12, and the second end of the thirteenth MOS transistor M13 are all connected, the eighth MOS transistor M8 is further connected to a fourth power supply VDD4 through a set of resistors and inductors connected in series.
Where NRZN and NRZP are input differential data signals, which are in NRZ format. The RZ signal can be generated by adding the signal generated by the right half circuit to the signal mixed by the clock signals CLKP and CLKN on the left side. The bias voltages VBIASP and VBIASN are used to adjust the weight and sign of the added original signal, thereby implementing a 2-tap feed forward equalization function. rZP and RZN are output differential data signals, namely return-to-zero code signals, and the format is RZ.
The specific structures of fig. 4 and 5 are exemplarily shown for better explaining the structure of the analog combining module ACM, and do not represent that the analog combining module ACM can only be the above structure, and all components and combinations thereof that can achieve the above functions can be replaced correspondingly.
On the basis of the structure of the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter, the embodiment of the invention also provides a high-speed serial port transmitter, and the high-speed serial port transmitter comprises any one of the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter structures.
On the basis of the DAC-based four-level pulse amplitude modulation high-speed serial transmitter structure, an embodiment of the present invention further provides an electronic device, where the electronic device includes any one of the DAC-based four-level pulse amplitude modulation high-speed serial transmitter structures described above.
Through the example, the structure of the DAC-based four-level pulse amplitude modulation high-speed serial port transmitter provides a novel DAC-based PAM4 (four-level pulse amplitude modulation) high-speed serial port transmitter architecture, the data combination is performed by adopting the analog combiner, and the feed-forward balance can be realized while the combination is performed.
The four-level pulse amplitude modulation high-speed serial port transmitter structure is high in working rate, and compared with a traditional digital combiner, the analog combining DAC architecture has the advantages that a CML differential pair is used, the switching speed is increased, and higher combining rate can be achieved. Meanwhile, the simple output stage structure is easier to integrate the inductor at the load end, and the bandwidth can be further expanded by utilizing an inductor peaking technology. Through simulation verification, the framework can realize the output data rate of 144Gb/s under the 65nm CMOS process, and is equivalent to the world advanced result under the FinFET process. The higher transistor cut-off frequency, the faster switch turn-on speed and the shorter routing distance in the advanced process can further improve the highest working speed of the architecture.
The structure of the four-level pulse amplitude modulation high-speed serial port transmitter is simplified, the area is small, and a large number of retiming circuits and a large number of parallel data paths are needed in the traditional serial port transmitter framework to realize the function of feed-forward equalization. The feedforward equalization framework based on the analog combiner can reduce the number of parallel data paths, simplify the structure of a transmitter, avoid integrating a large-scale transistor array at an output stage and reduce the parasitic capacitance of an output node.
The four-level pulse amplitude modulation high-speed serial port transmitter structure has low power consumption, and the feed-forward equalization framework reduces the number of parallel data paths, so that the power consumption on the corresponding data paths is saved. At the same time, the smaller data path load reduces the requirements for clock driving, while reducing the power consumption of the clock driving.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. The utility model provides a four level pulse amplitude modulation high speed serial ports transmitter structure based on DAC which characterized in that, four level pulse amplitude modulation high speed serial ports transmitter structure includes: the device comprises a low-speed digital combiner, a four-level pulse amplitude modulation module, an analog combiner module and a clock generation module;
the low-speed digital combiner receives a plurality of paths of parallel low-speed non-return-to-zero data signals, combines the low-speed parallel low-speed non-return-to-zero data signals to generate 8 paths of high-speed non-return-to-zero data signals and transmits the signals to the four-level pulse amplitude modulation module;
the four-level pulse amplitude modulation module receives the 8-path high-speed non-return-to-zero code data signal, converts the 8-path high-speed non-return-to-zero code data signal into 4-path four-level pulse amplitude modulation signals and transmits the signals to the analog combining module;
the analog combining module receives the 4 paths of four-level pulse amplitude modulation signals, combines the signals, performs feed-forward equalization of 2-tap, and generates and outputs 1 path of serial high-speed data signals;
the clock generation module is respectively connected with the low-speed digital combiner and the analog combiner module, and is used for providing clock signals for the low-speed digital combiner and the analog combiner module;
and the 1-path serial high-speed data signal output by the analog combining module is output outside the chip after bandwidth expansion by using an inductance peaking technology.
2. The structure of a four-level pulse amplitude modulation high-speed serial port transmitter of claim 1, wherein the analog combining module comprises: a first 2;
the first 2;
the first 2;
the second 2;
the first return-to-zero code generating unit converts the four-level pulse amplitude modulation signal with the higher frequency of the 1 st path into a first return-to-zero code signal and transmits the first return-to-zero code signal to the return-to-zero code summing unit;
the second return-to-zero code generating unit converts the four-level pulse amplitude modulation signal with the higher frequency of the 2 nd path into a second return-to-zero code signal and transmits the second return-to-zero code signal to the return-to-zero code summing unit;
and the return-to-zero code summation unit carries out staggered addition on the first return-to-zero code signal and the second return-to-zero code signal to obtain the 1-path serial high-speed data signal.
3. The four-level pulse amplitude modulation high-speed serial port transmitter structure according to claim 2, wherein the 2-path four-level pulse amplitude modulation signal is a 2-path differential data signal;
the first 2: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor;
the first end of the first MOS tube and the first end of the second MOS tube respectively receive one path of differential data signals in the 2 paths of differential data signals, and the first end of the third MOS tube and the first end of the fourth MOS tube respectively receive the other path of differential data signals in the 2 paths of four-level pulse amplitude modulation signals;
the second end of the first MOS tube is connected with the second end of the third MOS tube, and the fourth-level pulse amplitude modulation signal with the higher frequency in the 1 st path is output;
the third end of the first MOS tube is connected with the third end of the second MOS tube, and both the third end of the first MOS tube and the third end of the second MOS tube are connected with the second end of the fifth MOS tube;
the second end of the second MOS tube is connected with the second end of the fourth MOS tube, and outputs a four-level pulse amplitude modulation signal with higher frequency in the 1 st path;
the third end of the third MOS tube is connected with the third end of the fourth MOS tube and both connected with the second end of the sixth MOS tube;
the first end of the fifth MOS tube and the first end of the sixth MOS tube receive the clock signal respectively, and the clock signal is a differential clock signal;
the third end of the fifth MOS tube is connected with the third end of the sixth MOS tube, and both are connected with a first current source and are grounded through the first current source;
after the second end of the first MOS tube is connected with the second end of the third MOS tube, the second end of the first MOS tube is also connected with a first power supply through a group of resistors and inductors which are connected in series;
and after the second end of the second MOS tube is connected with the second end of the fourth MOS tube, the second end of the second MOS tube is also connected with a second power supply through a group of resistors and inductors which are connected in series.
4. The structure of a four-level pulse amplitude modulation high-speed serial port transmitter according to claim 3, wherein the 1 st path of higher frequency four-level pulse amplitude modulation signal and the 2 nd path of higher frequency four-level pulse amplitude modulation signal are both differential input signals;
the first return-to-zero code generating unit and the second return-to-zero code generating unit have the same structure, and the first return-to-zero code generating unit includes: a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a twelfth MOS tube; a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube and an eighteenth MOS tube;
the first end of the seventh MOS transistor, the first end of the eighth MOS transistor, the first end of the ninth MOS transistor, the first end of the tenth MOS transistor, the first end of the eleventh MOS transistor, the first end of the twelfth MOS transistor, the first end of the thirteenth MOS transistor, and the first end of the fourteenth MOS transistor all receive the differential input signal;
a second end of the seventh MOS transistor, a second end of the tenth MOS transistor, a second end of the eleventh MOS transistor, and a second end of the fourteenth MOS transistor are all connected, and the first return-to-zero code signal is output;
a second end of the eighth MOS transistor, a second end of the ninth MOS transistor, a second end of the twelfth MOS transistor, and a second end of the thirteenth MOS transistor are all connected, and the first return-to-zero code signal is output;
the third end of the seventh MOS tube is connected with the third end of the eighth MOS tube, and both the third end of the seventh MOS tube and the third end of the eighth MOS tube are connected with the second end of the fifteenth MOS tube;
the third end of the ninth MOS tube is connected with the third end of the tenth MOS tube, and both the third end of the ninth MOS tube and the third end of the tenth MOS tube are connected with the second end of the sixteenth MOS tube;
the third end of the eleventh MOS tube is connected with the third end of the twelfth MOS tube, and both the third end of the eleventh MOS tube and the third end of the twelfth MOS tube are connected with the second end of the seventeenth MOS tube;
a third end of the thirteenth MOS tube is connected with a third end of the fourteenth MOS tube, and both the third ends are connected with a second end of the eighteenth MOS tube;
the first end of the fifteenth MOS tube and the first end of the sixteenth MOS tube receive the clock signal respectively;
a first end of the seventeenth MOS tube and a first end of the eighteenth MOS tube respectively receive bias voltage;
the third end of the fifteenth MOS tube is connected with the third end of the sixteenth MOS tube, and both the third end of the fifteenth MOS tube and the third end of the sixteenth MOS tube are connected with a second current source and grounded through the second current source;
the third end of the seventeenth MOS tube is connected with the third end of the eighteenth MOS tube, and both are connected with a third current source and are grounded through the third current source;
after the second end of the seventh MOS tube, the second end of the tenth MOS tube, the second end of the eleventh MOS tube and the second end of the fourteenth MOS tube are connected, the seventh MOS tube is connected with a third power supply through a group of resistors and inductors which are connected in series;
and after the second end of the eighth MOS tube, the second end of the ninth MOS tube, the second end of the twelfth MOS tube and the second end of the thirteenth MOS tube are connected, the second end of the eighth MOS tube, the second end of the ninth MOS tube and the second end of the thirteenth MOS tube are connected with a fourth power supply through a group of resistors and inductors which are connected in series.
5. The structure of a four-level pulse amplitude modulation high-speed serial port transmitter according to claim 1, wherein the low-speed digital combiner adopts a serial port technology for processing, and the function of combining the multiple parallel low-speed non-return-to-zero code data signals into 8 high-speed non-return-to-zero code data signals is realized in a multi-stage combiner cascade mode;
the cascade stage number of the cascade of the multistage combiner is determined by the number of the multi-path parallel low-speed non-return-to-zero data signals.
6. The structure of the four-level pulse amplitude modulation high-speed serial port transmitter of claim 1, wherein the four-level pulse amplitude modulation module comprises: the differential amplifier comprises two groups of differential amplifiers with adjustable tail current sources, wherein the tail current of a differential pair corresponding to the MSB is twice as large as that of a differential pair corresponding to the LSB;
and the two groups of differential amplifiers with CML structures are connected to the same output, and the voltage generated by the two paths of current flowing through the load is the converted 4 paths of four-level pulse amplitude modulation signals.
7. The four-level pulse amplitude modulation high-speed serial port transmitter structure according to claim 1, wherein the clock generation module comprises: the circuit comprises a driver, a frequency divider and a phase interpolator, wherein the frequency divider is used for generating a low-speed clock from a high-speed clock, and the phase interpolator is used for adjusting the relative phase of the clocks between different cascaded combiners.
8. The structure of a four-level pulse amplitude modulation high-speed serial port transmitter of claim 6, wherein the multiple parallel low-speed non-return-to-zero data signals are 160 parallel low-speed non-return-to-zero data signals generated by a pseudo-random binary sequence signal source.
9. A high-speed serial transmitter, characterized in that the high-speed serial transmitter comprises a DAC-based four-level pulse amplitude modulation high-speed serial transmitter structure according to any one of claims 1 to 8.
10. An electronic device, characterized in that it comprises a DAC-based four-level pulse amplitude modulation high-speed serial port transmitter architecture according to any of claims 1-8.
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| CN117453605A (en) * | 2023-12-26 | 2024-01-26 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
| CN117453605B (en) * | 2023-12-26 | 2024-04-12 | 深圳市芯波微电子有限公司 | Signal output buffer, signal chip and printed circuit board |
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