CN105187342B - For the 3 tap decision feedback equalizer of low-power consumption of HSSI High-Speed Serial Interface receiving terminal - Google Patents
For the 3 tap decision feedback equalizer of low-power consumption of HSSI High-Speed Serial Interface receiving terminal Download PDFInfo
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- CN105187342B CN105187342B CN201510497808.XA CN201510497808A CN105187342B CN 105187342 B CN105187342 B CN 105187342B CN 201510497808 A CN201510497808 A CN 201510497808A CN 105187342 B CN105187342 B CN 105187342B
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Abstract
The invention belongs to technical field of data transmission, more particularly to a kind of 3 tap decision feedback equalizer of low-power consumption for HSSI High-Speed Serial Interface receiving terminal is respectively odd data road, even data road including the identical data path of two-strip structure；Include 1 gain stage, 1 imbalance elimination unit, 1 dynamic combining summer, 1 dynamic latch summer, 1 buffer, 1 dynamical feedback grade and 1 splitter per data access；Gain stage and imbalance in odd, even data road eliminate the balanced front end of unit composition；Dynamic latch summer, dynamical feedback grade and buffer in odd, even data road form the 1st tap circuit；Dynamic combining summer, splitter in odd, even data road form the 2nd, 3 tap circuits；The sum unit of entire 3 tap module is clock realization method.The present invention has the characteristics that low in energy consumption, high workload rate and the ability of equalization are strong.
Description
Technical field
The invention belongs to technical field of data transmission, more particularly to a kind of low-power consumption for HSSI High-Speed Serial Interface receiving terminal
3 tap decision feedback equalizer.
Background technology
The data transfer rate of High Speed Serial transceiver transmission in recent years constantly rises, and current single pass data transfer rate can reach
Under more than 40Gbps, so high data transfer rate, channel can generate serious attenuation to signal, at this time the design face of receiver
Face serious ISI problems.Common balanced device mainly has continuous time linear equalizer (Continuous Time Linear
Equalizer, CTLE) and decision feedback equalizer (Decision Feedback Equalizer, DFE).Decision feedback equalization
Device is widely used in the design of HSSI High-Speed Serial Interface receiving terminal, and decision feedback equalizer is placed in receiver front end, to carrying out self-channel
Serial data carry out time domain compensation, eliminate its intersymbol interference (Inter-Symbol Interference, ISI), ensure to receive
Machine correctly works.Decision feedback equalizer is a kind of nonlinear equalizer, it can provide more smaller than general linear equalizer
The bit error rate (Bit Error Rates, BER), linear equalizer are also exaggerated noise while ISI is reduced, and decision-feedback
Balanced device can not introduce noise gain while ISI is eliminated.
The design of multi-tap Direct-type decision feedback equalizer is mainly limited by the sequential of the 1st tap critical path, and 1 takes out
The principle that head decision feedback equalizer eliminates ISI is within the unit data cycle (Unit Interval, UI), is completed to elder generation
The judgement of preceding 1 (bit) data simultaneously backs into sum unit, eliminates the ISI to current bit data.Fig. 1 is typical 1 pumping
Head Direct-type decision feedback equalizer schematic diagram, the input analog signal on odd number road, which is adjudicated by trigger into digital signal, to be fed back to
The mutual conductance sum unit on even number road, and then body (1 after elimination the 1ststPost cursor, post 1) ISI.Entire critical path
Sequential limitation limited by formula (1)：
Tckq+Tsettle+Tsetup<1UI (1)
Wherein, Tckq, TsetupPropagation delay and the settling time of trigger, T are represented respectivelysettleRepresentative simulation summing junction
Stabilization time.If timing optimization, under the data transfer rate of 40Gbps, T are not carried out to critical pathckq+Tsettle+TsetupHold very much
Easily more than 1UI.
In order to solve the problems, such as that the 1st tap key path time sequence is nervous, a kind of method is as shown in Fig. 2, using congenial type
Structure carries out the design of the 1st tap, and the sequential of this stylish loop is：
Tckq+Ts,MX+Tsetup<1UI (2)
Wherein, Tckq, TsetupPropagation delay and the settling time of trigger, T are represented respectivelys,MXRepresent data selector
Digital signal propagation delay, usual Ts,MXIt is less than Tsettle.It is taken out although the structure design of this congenial type can be loosened to the 1st
The timing requirements of head critical path, but it is unfavorable for the design of the 2nd and later tapped loop, reason is data selector meeting
A large amount of loads are introduced, increase additional time delay, the quantity of another aspect data selector also can be exponential with tap number
Increase.
With the rising of data transfer rate, HSSI High-Speed Serial Interface receiving terminal power consumption --- the compromise between data transfer rate also becomes very
It is nervous.
The content of the invention
The shortcomings that in order to overcome the above-mentioned prior art, connects it is an object of the invention to provide one kind for HSSI High-Speed Serial Interface
The 3 tap decision feedback equalizer of low-power consumption of receiving end, it is characterised in that：Including the identical data path odd data road of two-strip structure
With even data road；It is moved per data access including 1 gain stage, 1 imbalance elimination unit, 1 dynamic combining summer, 1
State latches summer, 1 buffer, 1 dynamical feedback grade and 1 splitter；
Odd data road and the gain stage in even data road and the balanced front end of imbalance elimination unit composition, lack of proper care and eliminate unit
Be placed between gain stage output and ground, the gain stage output on odd data road and even data road be connected respectively to odd data road and
The dynamic combining summer output terminal on the dynamic combining summer input terminal on even data road, odd data road and even data road connects respectively
It is connected to the dynamic latch summer input terminal on odd data road and even data road in the 1st tap circuit；
1st tap circuit merges realization with the 1st tap on even data road by the 1st tap on odd data road, odd data road
1st tap is connected to the dynamic latch summer output terminal and odd number on odd data road by the dynamical feedback grade output terminal on even data road
It is formed after being connected to the buffer input on odd data road according to the dynamic latch summer output terminal on road, the 1st of even data road takes out
Head is connected to the dynamic latch summer output terminal on even data road and even data road by the dynamical feedback grade output terminal on odd data road
Dynamic latch summer output terminal be connected to the buffer input on even data road and form, odd data road and even data road it is slow
Rush the splitter input that device output terminal is connected respectively to odd data road and even data road；
Even circuit-switched data reduction of speed is 1/4 speed data of two-way by the splitter on even data road, and defeated by even data road splitter
Outlet is sent to the dynamic combining summer input terminal on even data road and odd data road, respectively constitutes the 2nd of even data road
Strange circuit-switched data reduction of speed is 1/4 speed data of two-way by tap and the 3rd tap on odd data road, odd data road splitter, and by strange
Data road splitter output is sent to odd data road and even data road dynamic is combined the input terminal of summer, respectively constitutes
2nd tap on odd data road and the 3rd tap on even data road；2nd tap circuit is by the 2nd tap on even data road and odd data road
The 2nd tap merge realize, the 3rd tap circuit merges realization by the 3rd tap on even data road with the 3rd tap on odd data road；
The sum unit of entire 3 tap module is clock realization method.
In the 1st tap circuit, the dynamic latch summer on odd data road and even data road is all by the mutual of a pair of 1/2 rate
Complement clock controls respectively, it is made to switch between summation and latch mode；In the 2nd, 3 tapped loops, odd data road and even number
According to the splitter on road respectively there are two clock control, and this four clocks are shared by dynamic combining summer.
The gain stage and imbalance eliminate unit and use current mode logic circuit.
The dynamic latch summer merges realization with dynamic latch by summer, including one by just along clock CLKP
The the first NMOS tube M0 for playing tail current source of control, a pair of the second NMOS tube M1, the 3rd NMOS driven by input data
Pipe M2, a pair of the first PMOS tube M3, the second PMOS tube M4 controlled by negative edge clock CLKN, there are one by just along clock CLKP
The 3rd PMOS tube M6 of pull-up of control；The source electrode of first PMOS tube M3 is connected with power vd D, and drain electrode is connected to the second NMOS tube
The drain electrode of M1, the drain electrode of the 3rd NMOS tube M2 are connected to the drain electrode of the second PMOS tube M4, and the source electrode of the second PMOS tube M4 is connected to
The source electrode of power vd D, the 3rd PMOS tube M6 are connected to power vd D, the source electrode ground connection of the first NMOS tube M0；Second NMOS tube M1's
Source electrode, the source electrode of the 3rd NMOS tube M2, the drain electrode of the 3rd PMOS tube M6 and the drain electrode of the first NMOS tube M0 are connected to the 3rd node
VP；First node VA is in the junction of the drain electrode and the drain electrode of the second PMOS tube M4 of the 3rd NMOS tube M2, first node VA connections
To differential data positive output end OUTP；Section point VB is in the company of the drain electrode and the drain electrode of the second NMOS tube M1 of the first PMOS tube M3
Place is met, section point VB is connected to differential data negative output terminal OUTN；The grid of first PMOS tube M3 and the second PMOS tube M4 connect
The grid for being connected to negative edge clock CLKN, the second NMOS tube M1 is connected to differential data positive input terminal INP, the grid of the 3rd NMOS tube M2
The grid that pole is connected to differential data negative input end INN, the first NMOS tube M0 and the 3rd PMOS tube M6 is connected to just along clock
CLKP。
The buffer uses current mode logic circuit.
Even data road splitter is by a pair of 1/4 speed difference quadrature clock：First differential clocks CKE10 and during the second difference
Clock CKEX10 is controlled, and odd data road splitter is by a pair of 1/4 speed difference quadrature clock：3rd differential clocks CKO10 and the 4th
Differential clocks CKOX10 is controlled；First differential clocks CKE10, the 3rd differential clocks CKO10, the second differential clocks CKEX10,
Four differential clocks CKOX10 differ 90 degree of phases successively.
Dynamic combining summer realized by combiner insertion sum unit, including 2 pairs of differential clocks input terminals, 4 pairs
Differential data input terminal and 1 pair of differential data output terminal.
Advantageous effect
Compared with prior art, decision feedback equalizer proposed by the present invention can guarantee that the sequential of the 1st tapped loop is abundant,
2nd, the feedback of 3 taps is realized under a quarter rate, and all tap sum units are clock mode, and balanced device is using dynamic
State mode realizes that the structure of 3 taps has the characteristics that low in energy consumption, high workload rate and the ability of equalization are strong.
Description of the drawings
Fig. 1 is typical 1 tap Direct-type Structure of Decision-feedback Equalization schematic diagram.
Fig. 2 is that typical 1 tap speculates type Structure of Decision-feedback Equalization schematic diagram.
Fig. 3 a~3b are that typical 1 tap Direct-type decision feedback equalizer its sum unit merges with main latch, from
The schematic diagram that latch merges with feedback stage.
Fig. 4 is 1 tap Direct-type decision-feedback receiver architecture schematic diagram in the present invention.
Fig. 5 is the 2nd, the 3rd tap circuit realization method schematic diagram in the present invention.
Fig. 6 is a kind of 3 tap decision feedback equalizer of low-power consumption for HSSI High-Speed Serial Interface receiving terminal of the present invention
Structure diagram.
Fig. 7 is the dynamic latch summer circuit in the present invention.
Fig. 8 is the demultiplexer circuit figure in the present invention.
Fig. 9 is the dynamic combining summer circuit figure in the present invention.
Figure 10 is the eye pattern of input data.
Figure 11 is the eye pattern of even data road output data.
Specific embodiment
Below in conjunction with the accompanying drawings with embodiment, elaborate to preferred embodiment.
In order to solve the problems, such as that the 1st tapped loop sequential is nervous, " dynamic latch summer " and " dynamical feedback grade " are proposed
Circuit structure, while key path time sequence requirement is met, moreover it is possible to significantly decrease power consumption.It, will as shown in Fig. 3 a~3b
The sum unit of typical 1 tap Direct-type decision feedback equalizer merges with main latch in Fig. 1, from latch and feedback stage
Merge, so that " summation is stablized " process occurs simultaneously with " signal amplification " process.After sum unit is merged with main latch
Unit be referred to as " dynamic latch summer ", from latch merge with feedback stage after unit referred to as " dynamical feedback
Grade ", utilizes " dynamic latch summer ", " dynamical feedback grade ", and the timing requirements of critical path can be reduced to：
Tdq<1UI (3)
Here, TdqRepresent the settling time T of the propagation delay of " dynamic latch summer ", size and triggersetupDifference
It is not much.After this one-step optimization, the sequential of critical path is significantly loosened, the 1st tap circuit after optimization
As shown in Figure 3b.Since " dynamic latch summer " will promote parasitic capacitance between " dynamical feedback grade ", splitter and line,
Load is equivalent to the minimum dimension phase inverter being fanned out to as 4, so added first-level buffer device below at " dynamic latch summer ", with
Enhance its impetus, the Direct-type Structure of Decision-feedback Equalization figure of entire 1 tap is as shown in Figure 4.
2nd, 3 tap circuits propose using " branch-combining " structure type of splitter and " dynamic be combined summer " come
It realizes, significantly reduces power consumption.It realizes as described below：As shown in figure 5, odd even the two paths of data D_O, D_E of 1/2 data transfer rate
Generated under the control of clock CKE10, CKEX10, CKO10, CKOX10 after splitter 4 tunnel, 1/4 data transfer rate data D00,
D01, D0, D03, the data of 4 tunnel, 1/4 rate under the control of clock CKE10, CKEX10, CKO10, CKOX10, pass through again
" dynamic combining combining summer " realizes combining and summation.
Fig. 6 illustrates decision feedback equalizer structure proposed by the invention, including the identical data of two-strip structure
Access is followed successively by odd data road, even data road；Include 1 gain per data access and improve grade, 1 imbalance elimination unit, 1
A dynamic combining summer, 1 dynamic latch summer, 1 dynamical feedback grade, 1 buffer and 1 splitter.
Gain stage and imbalance in odd, even data road eliminate the balanced front end of unit composition；Dynamic in odd, even data road
It latches summer, dynamical feedback grade and buffer and forms the 1st tap circuit；In odd, even data road dynamic combining summer,
Splitter forms the 2nd, 3 tap circuits；
The gain stage of balanced front end includes a differential input end, a difference output end；Differential input end is used to receive
By the data-signal Din of fading channel, difference output end will be sent to imbalance by the data-signal of amplification and eliminate unit
The input terminal of output terminal and the summer of dynamic combining thereafter；
In the 1st tap circuit, the dynamic latch summer output terminal connection even data road buffer input on even data road
End, odd data road dynamical feedback grade output terminal, and clock CK20 is shared with the dynamical feedback grade on odd data road, form even data road
The 1st tap；And the dynamic latch summer output terminal connection odd number on the output terminal connection odd data road of even data road buffer
Clock is shared according to road buffer input, even data road dynamical feedback grade output terminal, and with the dynamical feedback grade on even data road
CKX20 forms the 1st tap on even data road；1st tap on odd, even data road by 1 couple of 1/2 rate complementary clock CKX20,
CK20 is controlled respectively, and the dynamic latch summer of odd even two-way is made to switch respectively between latch and summation state；
Fig. 7 is the dynamic latch summer circuit schematic diagram in odd, even data road.The dynamic latch used in the present invention is asked
It is realized with device by the dynamic latch with pull-up PMOS tube, including one by just along clock CLKP tail current source having been controlled to act on
NMOS tube M0, a pair of NMOS tube M1, M2 driven by input data, a pair of PMOS load pipe controlled by negative edge clock CLKN
M3, M4, there are one the pull-up PMOS tube M6 controlled by CLKP；When CLKP is high level, the execution of dynamic latch summer is asked
And function, when CLKN is high level, dynamic latch summer performs latch function；
In the 2nd, 3 tap circuits, splitter input receives the data from buffer output end, even data road branch
Even circuit-switched data D_E reductions of speed are D00 and 1/4 speed data of D02 two-way by device, and are sent to even data Lu Yuqi by output terminal
The input terminal of the dynamic combining summer on data road, respectively constitutes the 2nd tap on even data road and the 3rd tap on odd data road；
Strange circuit-switched data D_O reductions of speed are D01 and 1/4 speed data of D03 two-way by odd data road splitter, and are sent to by output terminal
Odd data road and the input terminal of the dynamic combining summer on even data road respectively constitute the 2nd tap and even data on odd data road
3rd tap on road；The splitter on even data road is controlled by 1/4 speed difference quadrature clock CKE10, CKEX10 of a pair, odd data road
Splitter is controlled by 1/4 speed difference quadrature clock CKO10, CKOX10 of a pair, and CKE10, CKO10, CKEX10, CKOX10 are differed successively
90 degree of phases；
Fig. 8 is the demultiplexer circuit figure in odd, even data road, which is made of two parts, and prime sampling switch is with after
Grade positive feedback pair.Sampling switch is controlled by complementary clock CK10, CKX10 of a pair of 1/4 rate, to the odd data road of 1/2 rate
Or even data circuit-switched data carries out alternating sampling, realizes branch function.Positive feedback is to the complementary clock by similary a pair of 1/4 rate
CK10, CKX10 are controlled, in each access, the clock of sampling switch and the complementary clock of positive feedback pair, to ensure sampling switch
During keeping data level, positive feedback is to can be amplified data-signal, and the degree of data-signal amplification is then by positive feedback
The bias voltage BIAS in tail current source is controlled.
Fig. 9 is the dynamic combining summer circuit figure in odd, even data road, and dynamic is combined summer circuit by four structures
Identical dynamic sum unit is realized.By taking the combining summation of the 2nd tap as an example, two identical dynamic sum units are by a pair 1/
Complementary clock CKE10, CKEX10 control of 4 rates, when CKE10, CKEX10 are alternately high level, sum unit just will come from
The data of 1/4 rate of splitter are combined, and the combining summation of the 3rd tap is identical with the combining summation of the 2nd tap.2nd
Tap, the 3rd tap summation weight size respectively by sum unit tail current source capsule bias voltage Tap2_B, TAP3_B into
Row control.
Figure 10 and Figure 11 is input, the eye pattern comparison of output data respectively.When the PRBS31 numbers that data rate is 40Gbps
According to by one section at nyquist frequency (20GHz) to signal decay 22dB channel after, be input to system as shown in Figure 1
In, the eye pattern of input data is as shown in Figure 10, it is seen that eyes are almost closed；And the eye pattern in Figure 11 is shown in Fig. 6
The even data road output data eye pattern of DFE, by the comparison of left and right two figure it is apparent that the portfolio effect of DFE.
The present invention is compared with existing technologies, and in addition to gain stage eliminates unit as the realization of CML structures with imbalance, rest part is equal
For clock realization method, this dynamic processing mode can significantly decrease the power consumption of decision feedback equalizer.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims
Subject to.
Claims (1)
1. a kind of 3 tap decision feedback equalizer of low-power consumption for HSSI High-Speed Serial Interface receiving terminal, it is characterised in that：Including two
The identical data path odd data road of structure and even data road；Include 1 gain stage per data access, 1 imbalance eliminates
Unit, 1 dynamic combining summer, 1 dynamic latch summer, 1 buffer, 1 dynamical feedback grade and 1 branch
Device；
Odd data road and gain stage in even data road and imbalance eliminate the balanced front end of unit composition, and imbalance eliminates unit and is placed in
Between gain stage output and ground, the gain stage output on odd data road and even data road is connected respectively to odd data road and even number
According to the dynamic combining summer input terminal on road, the dynamic combining summer output terminal on odd data road and even data road is connected respectively to
1st odd data road in tap circuit and the dynamic latch summer input terminal on even data road；
1st tap circuit merges realization with the 1st tap on even data road by the 1st tap on odd data road, and the 1st of odd data road takes out
Head is connected to the dynamic latch summer output terminal on odd data road and odd data road by the dynamical feedback grade output terminal on even data road
Dynamic latch summer output terminal be connected to the buffer input on odd data road after form, the 1st tap on even data road by
The dynamical feedback grade output terminal on odd data road is connected to the dynamic latch summer output terminal on even data road and moving for even data road
State latches the buffer of the buffer input composition that summer output terminal is connected to even data road, odd data road and even data road
Output terminal is connected respectively to the splitter input on odd data road and even data road；
Even circuit-switched data reduction of speed is 1/4 speed data of two-way by the splitter on even data road, and by even data road splitter output
The dynamic combining summer input terminal on even data road and odd data road is sent to, respectively constitutes the 2nd tap on even data road
With the 3rd tap on odd data road, strange circuit-switched data reduction of speed is 1/4 speed data of two-way by odd data road splitter, and by odd data
Road splitter output is sent to odd data road and even data road dynamic is combined the input terminal of summer, respectively constitutes odd number
According to the 2nd tap on road and the 3rd tap on even data road；2nd tap circuit by even data road the 2nd tap and odd data road the
2 taps, which merge, to be realized, the 3rd tap circuit merges realization by the 3rd tap on even data road with the 3rd tap on odd data road；Entire 3
The sum unit of tap module is clock realization method, which is characterized in that the dynamic locking on the odd data road and even data road
It deposits summer all to be controlled respectively by the complementary clock of a pair of 1/2 rate, it is made to switch between summation and latch mode；It is described strange
The splitter on data road and even data road is respectively there are two clock control, and this four clocks are shared by dynamic combining summer,
It is characterized in that, the gain stage and imbalance eliminate unit using current mode logic circuit, and the dynamic latch summer is by asking
Merge realization with dynamic latch with device, including one by just controlling the first of tail current source effect along clock (CLKP)
NMOS tube (M0), a pair of the second NMOS tube (M1) and the 3rd NMOS tube (M2) driven by input data, a pair is by negative edge clock
(CLKN) the first PMOS tube (M3) of control and the second PMOS tube (M4), there are one the pull-up by just being controlled along clock (CLKP)
3rd PMOS tube (M6)；The source electrode of first PMOS tube (M3) is connected with power supply (VDD), and drain electrode is connected to the second NMOS tube (M1)
Drain electrode, the drain electrode of the 3rd NMOS tube (M2) is connected to the drain electrode of the second PMOS tube (M4), and the source electrode of the second PMOS tube (M4) connects
Power vd D is connected to, the source electrode of the 3rd PMOS tube (M6) is connected to power vd D, the source electrode ground connection of the first NMOS tube (M0)；Second
The source electrode of NMOS tube (M1), the source electrode of the 3rd NMOS tube (M2), the drain electrode of the 3rd PMOS tube (M6) and the first NMOS tube (M0)
Drain electrode is connected to the 3rd node (VP)；First node (VA) is in the drain electrode of the 3rd NMOS tube (M2) and the leakage of the second PMOS tube (M4)
On the connecting line of pole, first node (VA) is connected to differential data positive output end (OUTP)；Section point (VB) is in the first PMOS
On the connecting line for managing the drain electrode of (M3) and the drain electrode of the second NMOS tube (M1), section point (VB) is connected to differential data negative output
It holds (OUTN)；The grid of first PMOS tube (M3) and the second PMOS tube (M4) is connected to negative edge clock (CLKN), the second NMOS tube
(M1) grid is connected to differential data positive input terminal (INP), the grid of the 3rd NMOS tube (M2) be connected to differential data bear it is defeated
Enter to hold (INN), the grid of the first NMOS tube (M0) and the 3rd PMOS tube (M6) is connected to just along clock (CLKP), the buffer
Using current mode logic circuit, even data road splitter is by a pair of 1/4 speed difference quadrature clock：First differential clocks
(CKE10) controlled with the second differential clocks (CKEX10), odd data road splitter is by a pair of 1/4 speed difference quadrature clock：The
Three differential clocks (CKO10) and the control of the 4th differential clocks (CKOX10)；First differential clocks (CKE10), the 3rd differential clocks
(CKO10), the second differential clocks (CKEX10), the 4th differential clocks (CKOX10) differ 90 degree of phases successively, and the dynamic is closed
Road summer is realized by combiner insertion sum unit, including 2 pairs of differential clocks input terminals, 4 pairs of differential data input terminals and 1
To differential data output terminal.
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| WO2019155582A1 (en) | 2018-02-08 | 2019-08-15 | 株式会社ソシオネクスト | Amplification circuit, addition circuit, reception circuit and integrated circuit |
| CN112422461B (en) * | 2020-11-05 | 2022-04-19 | 硅谷数模(苏州)半导体有限公司 | Decision feedback equalizer and data acquisition and correction method |
| US11044124B1 (en) * | 2020-12-21 | 2021-06-22 | Faraday Technology Corporation | Dynamic module and decision feedback equalizer |
| CN113364711B (en) * | 2021-05-13 | 2022-07-19 | 北京大学（天津滨海）新一代信息技术研究院 | Decision feedback equalizer |
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