CN105187342A - Three-tap decision feedback equalizer having low power dissipation and used for receiving end of high-speed serial interface - Google Patents
Three-tap decision feedback equalizer having low power dissipation and used for receiving end of high-speed serial interface Download PDFInfo
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Abstract
The invention belongs to the technical field of data transmission, and in particular relates to a three-tap decision feedback equalizer having low power dissipation and used for a receiving end of a high-speed serial interface. The three-tap decision feedback equalizer comprises two data paths, respectively an odd data path and an even data path same in structure; each data path comprises a gain stage, an offset cancelling unit, a dynamic combiner summator, a dynamic latch summator, a buffer, a dynamic feedback stage and a splitter; the gain stages and the offset cancelling units in the odd and even data paths form a front equalizing end; the dynamic latch summators, the dynamic feedback stages and the buffers in the odd and even data paths form a first tap loop; the dynamic combiner summators and the splitters in the odd and even data paths form a third and third tap loops; and summation units of whole three tap modules are in a clock control implementation manner. The three-tap decision feedback equalizer disclosed by the invention has the characteristics of being low in power consumption, high in working rate and strong in equalizing capability.
Description
Technical field
The invention belongs to technical field of data transmission, particularly a kind of low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal.
Background technology
The data transfer rate of High Speed Serial transceiver transmission in recent years constantly rises, current single pass data transfer rate can reach more than 40Gbps, under so high data transfer rate, channel can produce serious attenuation to signal, and the now design of receiver is faced with serious ISI problem.Conventional equalizer mainly contains continuous time linear equalizer (ContinuousTimeLinearEqualizer, CTLE) and DFF (DecisionFeedbackEqualizer, DFE).DFF is widely used in the design of HSSI High-Speed Serial Interface receiving terminal, DFF is placed in receiver front end, time domain compensation is carried out to the serial data carrying out self-channel, eliminate its intersymbol interference (Inter-SymbolInterference, ISI), ensure that receiver correctly works.DFF is a kind of nonlinear equalizer, it can provide the error rate (BitErrorRates less than general linear equalizer, BER), linear equalizer is also exaggerated noise while reduction ISI, and DFF can not introduce noise gain while elimination ISI.
The design of many taps Direct-type DFF mainly limits by the sequential of the 1st tap critical path, the principle that 1 tap DFF eliminates ISI is at unit data cycle (UnitInterval, UI) within, complete the judgement of previous 1 (bit) data and sent back to sum unit, eliminating the ISI to current bit data.Fig. 1 is typical 1 tap Direct-type DFF schematic diagram, and the mutual conductance sum unit that digital signal feeds back to even number road adjudicated into by the input analog signal on the odd number road device that is triggered, and then body (1 after eliminating the 1st
stpostcursor, post1) ISI.The sequential restriction of whole critical path limit by formula (1):
T
ckq+T
settle+T
setup<1UI(1)
Wherein, T
ckq, T
setuprepresent propagation delay and the settling time of trigger respectively, T
settlethe stabilization time of representative simulation summing junction.If do not carry out timing optimization to critical path, under the data transfer rate of 40Gbps, T
ckq+ T
settle+ T
setupcan easily exceed 1UI.
In order to solve the problem of the 1st tap key path time sequence anxiety, as shown in Figure 2, adopt the structure speculating type to carry out the 1st tap design, the sequential of this stylish loop is a kind of method:
T
ckq+T
s,MX+T
setup<1UI(2)
Wherein, T
ckq, T
setuprepresent propagation delay and the settling time of trigger respectively, T
s, MXthe digital signal propagation delay of representative data selector, usual T
s, MXbe less than T
settle.Although the structural design of this congenial type can loosen the timing requirements to the 1st tap critical path, but be unfavorable for the design of the 2nd and later tapped loop, its reason is that data selector can introduce a large amount of load, increase extra time delay, the quantity of data selector also can along with the exponential increase of tap number on the other hand.
Along with the rising of data transfer rate, HSSI High-Speed Serial Interface receiving terminal power consumption---the compromise between data transfer rate also becomes at full stretch.
Summary of the invention
In order to overcome the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal, it is characterized in that: comprise the identical data path odd data road of two-strip structure and even data road; Every bar data path comprises 1 gain stage, unit, 1 dynamic conjunction road summer, 1 dynamic latch summer, 1 buffer, 1 dynamical feedback level and 1 splitter are eliminated in 1 imbalance;
Gain stage in odd data road and even data road and imbalance are eliminated unit and are formed balanced front end, imbalance is eliminated unit and is placed between gain stage output and ground, the gain stage output on odd data road and even data road is connected respectively to the dynamic conjunction road summer input on odd data road and even data road, and the dynamic conjunction road summer output on odd data road and even data road is connected respectively to the dynamic latch summer input on odd data road and even data road in the 1st tap loop;
1st tap loop is merged by the 1st tap on odd data road and the 1st tap on even data road and realizes, form after the dynamic latch summer output of dynamic latch summer output and odd data road that the 1st tap on odd data road is connected to odd data road by the dynamical feedback level output on even data road is connected to the buffer input on odd data road, the buffer input that the dynamic latch summer output of dynamic latch summer output and even data road that the 1st tap on even data road is connected to even data road by the dynamical feedback level output on odd data road is connected to even data road is formed, the buffer output end on odd data road and even data road is connected respectively to the splitter input on odd data road and even data road,
Even circuit-switched data reduction of speed is two-way 1/4 speed data by the splitter on even data road, and the dynamic conjunction road summer input on even data road and odd data road is sent to by even data road splitter output, form the 2nd tap on even data road and the 3rd tap on odd data road respectively, strange circuit-switched data reduction of speed is two-way 1/4 speed data by odd data road splitter, and be sent to by odd data road splitter output the input that road summer is dynamically closed on odd data road and even data road, form the 2nd tap on odd data road and the 3rd tap on even data road respectively; 2nd tap loop is merged by the 2nd tap on even data road and the 2nd tap on odd data road and realizes, and the 3rd tap loop is merged by the 3rd tap on even data road and the 3rd tap on odd data road and realizes; The sum unit of whole 3 tap modules is clock implementation.
In the 1st tap loop, the dynamic latch summer on odd data road and even data road is all controlled respectively by the complementary clock of a pair 1/2 speed, makes it switch between summation and latch mode; The 2nd, in 3 tapped loop, the splitter on odd data road and even data road respectively has two clock controls, and these four clocks are dynamically closed road summer shares.
Described gain stage and imbalance are eliminated unit and are all adopted current mode logic circuit.
Described dynamic latch summer is merged by summer and dynamic latch and realizes, comprise one by the first NMOS tube M0 just having controlled tail current source effect along clock CLKP, a pair by the second NMOS tube M1, the 3rd NMOS tube M2 that input data-driven, a pair by negative edge clock CLKN control the first PMOS M3, the second PMOS M4, also have one by just along clock CLKP control pull-up the 3rd PMOS M6; The source electrode of the first PMOS M3 is connected with power vd D, its drain electrode is connected to the drain electrode of the second NMOS tube M1, the drain electrode of the 3rd NMOS tube M2 is connected to the drain electrode of the second PMOS M4, the source electrode of the second PMOS M4 is connected to power vd D, the source electrode of the 3rd PMOS M6 is connected to power vd D, the source ground of the first NMOS tube M0; The source electrode of the second NMOS tube M1, the source electrode of the 3rd NMOS tube M2, the drain electrode of the 3rd PMOS M6 and the drain electrode of the first NMOS tube M0 are connected to the 3rd node VP; First node VA is in the junction of the drain electrode of the 3rd NMOS tube M2 and the drain electrode of the second PMOS M4, and first node VA is connected to differential data positive output end OUTP; Section Point VB is in the junction of the drain electrode of the first PMOS M3 and the drain electrode of the second NMOS tube M1, and Section Point VB is connected to differential data negative output terminal OUTN; The grid of the first PMOS M3 and the second PMOS M4 is connected to negative edge clock CLKN, the grid of the second NMOS tube M1 is connected to differential data positive input terminal INP, the grid of the 3rd NMOS tube M2 is connected to differential data negative input end INN, and the grid of the first NMOS tube M0 and the 3rd PMOS M6 is connected to just along clock CLKP.
Described buffer adopts current mode logic circuit.
Described even data road splitter is by a pair 1/4 speed difference quadrature clocks: the first differential clocks CKE10 and the second differential clocks CKEX10 controls, and described odd data road splitter is by a pair 1/4 speed difference quadrature clocks: the 3rd differential clocks CKO10 and the 4th differential clocks CKOX10 controls; First differential clocks CKE10, the 3rd differential clocks CKO10, the second differential clocks CKEX10, the 4th differential clocks CKOX10 differ 90 degree of phase places successively.
Described dynamic conjunction road summer embeds sum unit by mixer and realizes, and comprises 2 pairs of differential clocks inputs, 4 pairs of differential data input terminal and 1 pair of differential data output.
Beneficial effect
Compared with prior art, the DFF that the present invention proposes can ensure that the sequential of the 1st tapped loop is abundant, 2nd, the feedback of 3 taps realizes under 1/4th speed, all tap sum unit are clock mode, equalizer adopts dynamical fashion to realize, the structure of 3 taps, has low in energy consumption, high workload speed and the strong feature of the ability of equalization.
Accompanying drawing explanation
Fig. 1 is typical 1 tap Direct-type Structure of Decision-feedback Equalization schematic diagram.
Fig. 2 is that type Structure of Decision-feedback Equalization schematic diagram is speculated in typical 1 tap.
Fig. 3 a ~ 3b is that typical 1 its sum unit of tap Direct-type DFF and main latch merge, from the schematic diagram that latch and feedback stage merge.
Fig. 4 is 1 tap Direct-type decision-feedback receiver architecture schematic diagram in the present invention.
Fig. 5 is the 2nd in the present invention, the 3rd tap loop implementation schematic diagram.
Fig. 6 is the structural representation of a kind of low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal of the present invention.
Fig. 7 is the dynamic latch summer circuit in the present invention.
Fig. 8 is the demultiplexer circuit figure in the present invention.
Fig. 9 is the dynamic conjunction road summer circuit figure in the present invention.
Figure 10 is the eye pattern of input data.
Figure 11 is the eye pattern that even data road exports data.
Embodiment
Below in conjunction with accompanying drawing and embodiment, preferred embodiment is elaborated.
In order to solve the problem of the 1st tapped loop sequential anxiety, proposing " dynamic latch summer " and the circuit structure of " dynamical feedback level ", while meeting key path time sequence requirement, power consumption can also be reduced significantly.As shown in Fig. 3 a ~ 3b, the sum unit of 1 tap Direct-type DFF typical in Fig. 1 and main latch are merged, merges from latch and feedback stage, occur with " signal amplifies " process to make " summation is stable " process simultaneously.Unit after sum unit and main latch being merged is referred to as " dynamic latch summer ", unit after latch and feedback stage merge is referred to as " dynamical feedback level ", utilize " dynamic latch summer ", " dynamical feedback level ", the timing requirements of critical path can be reduced to:
T
dq<1UI(3)
Here, T
dqthe propagation delay of representative " dynamic latch summer ", T settling time of its size and trigger
setupsimilar large.After this one-step optimization, the sequential of critical path is loosened significantly, and the 1st tap loop after optimization as shown in Figure 3 b.Because " dynamic latch summer " will promote parasitic capacitance between " dynamical feedback level ", splitter and line, its load is equivalent to the minimum dimension inverter that fan-out is 4, so added first-level buffer device below at " dynamic latch summer ", to strengthen its impetus, the Direct-type Structure of Decision-feedback Equalization figure of whole 1 tap as shown in Figure 4.
2nd, 3 tap loops propose to adopt " along separate routes-close road " version of splitters and " dynamically closing road summer " to realize, and significantly reduce power consumption.It realizes as described below: as shown in Figure 5, the odd even two paths of data D_O of 1/2 data transfer rate, D_E generates data D00, D01, D0, D03 of 4 tunnel 1/4 data transfer rates under the control of clock CKE10, CKEX10, CKO10, CKOX10 after splitter, the data of this 4 tunnel 1/4 speed, again under the control of clock CKE10, CKEX10, CKO10, CKOX10, realize closing road and summation by " dynamically closing Lu Helu summer ".
Fig. 6 illustrates decision feedback equalizer structure proposed by the invention, comprises the data path that two-strip structure is identical, is followed successively by odd data road, even data road; Every bar data path comprises 1 gain and improves level, 1 imbalance elimination unit, 1 dynamic conjunction road summer, 1 dynamic latch summer, 1 dynamical feedback level, 1 buffer and 1 splitter.
Gain stage in odd, even data road and imbalance are eliminated unit and are formed balanced front end; Dynamic latch summer in odd, even data road, dynamical feedback level and buffer composition the 1st tap loop; Dynamic conjunction road summer in odd, even data road, splitter composition the 2nd, 3 tap loops;
The gain stage of balanced front end comprises a differential input end, a difference output end; Differential input end is for receiving the data-signal Din through fading channel, and the data-signal through amplifying is sent to imbalance and eliminates the output of unit and dynamically close thereafter the input of road summer by difference output end;
In the 1st tap loop, the dynamic latch summer output on even data road connects even data road buffer input, odd data road dynamical feedback level output, and shares clock CK20 with the dynamical feedback level on odd data road, forms the 1st tap on even data road; And the dynamic latch summer output that the output of even data road buffer connects odd data road connects odd data road buffer input, even data road dynamical feedback level output, and share clock CKX20 with the dynamical feedback level on even data road, form the 1st tap on even data road; 1st tap on odd, even data road controls 1/2 speed complementary clock CKX20, CK20 respectively by 1, and the dynamic latch summer of odd even two-way is switched respectively between latch and summation state;
Fig. 7 is the dynamic latch summer circuit schematic diagram in odd, even data road.The dynamic latch summer adopted in the present invention is realized by the dynamic latch with pull-up PMOS, comprise one by the NMOS tube M0 just having controlled tail current source effect along clock CLKP, a pair by the NMOS tube M1, the M2 that input data-driven, PMOS load pipe M3, M4 of being controlled by negative edge clock CLKN for a pair, also have a pull-up PMOS M6 controlled by CLKP; When CLKP is high level, dynamic latch summer performs summation function, and when CLKN is high level, dynamic latch summer performs latch function;
In the 2nd, 3 tap loops, splitter input receives the data from buffer output end, even circuit-switched data D_E reduction of speed is D00 and D02 two-way 1/4 speed data by even data road splitter, and the input of the dynamic conjunction road summer on even data road and odd data road is sent to by output, form the 2nd tap on even data road and the 3rd tap on odd data road respectively; Strange circuit-switched data D_O reduction of speed is D01 and D03 two-way 1/4 speed data by odd data road splitter, and the input of the dynamic conjunction road summer on odd data road and even data road is sent to by output, form the 2nd tap on odd data road and the 3rd tap on even data road respectively; The splitter on even data road is controlled by a pair 1/4 speed difference quadrature clocks CKE10, CKEX10, and the splitter on odd data road is controlled by a pair 1/4 speed difference quadrature clocks CKO10, CKOX10, and CKE10, CKO10, CKEX10, CKOX10 differ 90 degree of phase places successively;
Fig. 8 is the demultiplexer circuit figure in odd, even data road, and this circuit is made up of two parts, prime sampling switch and rear class positive feedback pair.Sampling switch is controlled by complementary clock CK10, CKX10 of a pair 1/4 speed, carries out alternating sampling to the odd data road of 1/2 speed or even data circuit-switched data, realizes function along separate routes.Positive feedback controls complementary clock CK10, the CKX10 by same a pair 1/4 speed, in each path, the clock of sampling switch and the right complementary clock of positive feedback, during guaranteeing that sampling switch keeps data level, positive feedback is to amplifying data-signal, and the degree that data-signal amplifies then is controlled by the bias voltage BIAS of positive feedback to tail current source.
Fig. 9 is the dynamic conjunction road summer circuit figure in odd, even data road, dynamically closes road summer circuit and is realized by the dynamic sum unit that four structures are identical.Example is summed to the conjunction road of the 2nd tap, two identical dynamic sum unit are controlled by complementary clock CKE10, CKEX10 of a pair 1/4 speed, when CKE10, CKEX10 are alternately for high level, the data of 1/4 speed from splitter are just carried out conjunction road by sum unit, and the 3rd tap is closed road summation and sued for peace identical with the conjunction road of the 2nd tap.The weight size of the 2nd tap, the 3rd tap summation is controlled by bias voltage Tap2_B, TAP3_B of the tail current source capsule of sum unit respectively.
Figure 10 and Figure 11 is input respectively, exports the eye pattern contrast of data.When data rate be the PRBS31 data of 40Gbps by one section after nyquist frequency (20GHz) place is to the channel of signal attenuation 22dB, be input in system as shown in Figure 1, as shown in Figure 10, visible eyes are almost completely closed for the eye pattern of input data; And the even data road that the eye pattern in Figure 11 is DFE shown in Fig. 6 exports data eye, the portfolio effect of DFE can be found out significantly by the contrast of left and right two figure.
The present invention is compared with existing technologies, and eliminating unit except gain stage with imbalance is that except CML structure realizes, remainder is clock implementation, and this dynamic process mode can reduce the power consumption of DFF significantly.
The above; be only the present invention's preferably embodiment, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (7)
1. for a low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal, it is characterized in that: comprise the identical data path odd data road of two-strip structure and even data road; Every bar data path comprises 1 gain stage, unit, 1 dynamic conjunction road summer, 1 dynamic latch summer, 1 buffer, 1 dynamical feedback level and 1 splitter are eliminated in 1 imbalance;
Gain stage in odd data road and even data road and imbalance are eliminated unit and are formed balanced front end, imbalance is eliminated unit and is placed between gain stage output and ground, the gain stage output on odd data road and even data road is connected respectively to the dynamic conjunction road summer input on odd data road and even data road, and the dynamic conjunction road summer output on odd data road and even data road is connected respectively to the dynamic latch summer input on odd data road and even data road in the 1st tap loop;
1st tap loop is merged by the 1st tap on odd data road and the 1st tap on even data road and realizes, form after the dynamic latch summer output of dynamic latch summer output and odd data road that the 1st tap on odd data road is connected to odd data road by the dynamical feedback level output on even data road is connected to the buffer input on odd data road, the buffer input that the dynamic latch summer output of dynamic latch summer output and even data road that the 1st tap on even data road is connected to even data road by the dynamical feedback level output on odd data road is connected to even data road is formed, the buffer output end on odd data road and even data road is connected respectively to the splitter input on odd data road and even data road,
Even circuit-switched data reduction of speed is two-way 1/4 speed data by the splitter on even data road, and the dynamic conjunction road summer input on even data road and odd data road is sent to by even data road splitter output, form the 2nd tap on even data road and the 3rd tap on odd data road respectively, strange circuit-switched data reduction of speed is two-way 1/4 speed data by odd data road splitter, and be sent to by odd data road splitter output the input that road summer is dynamically closed on odd data road and even data road, form the 2nd tap on odd data road and the 3rd tap on even data road respectively; 2nd tap loop is merged by the 2nd tap on even data road and the 2nd tap on odd data road and realizes, and the 3rd tap loop is merged by the 3rd tap on even data road and the 3rd tap on odd data road and realizes; The sum unit of whole 3 tap modules is clock implementation.
2. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, it is characterized in that, the dynamic latch summer on described odd data road and even data road is all controlled respectively by the complementary clock of a pair 1/2 speed, makes it switch between summation and latch mode; The splitter on described odd data road and even data road respectively has two clock controls, and these four clocks are dynamically closed road summer shares.
3. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, is characterized in that, described gain stage and imbalance are eliminated unit and all adopted current mode logic circuit.
4. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, it is characterized in that, described dynamic latch summer is merged by summer and dynamic latch and realizes, comprise one by the first NMOS tube (M0) just having controlled tail current source effect along clock (CLKP), a pair by the second NMOS tube (M1) and the 3rd NMOS tube (M2) that input data-driven, the first PMOS (M3) controlled by negative edge clock (CLKN) for a pair and the second PMOS (M4), also has one by the pull-up the 3rd PMOS (M6) just controlled along clock (CLKP), the source electrode of the first PMOS (M3) is connected with power supply (VDD), its drain electrode is connected to the drain electrode of the second NMOS tube (M1), the drain electrode of the 3rd NMOS tube (M2) is connected to the drain electrode of the second PMOS (M4), the source electrode of the second PMOS (M4) is connected to power vd D, the source electrode of the 3rd PMOS (M6) is connected to power vd D, the source ground of the first NMOS tube (M0), the source electrode of the second NMOS tube (M1), the source electrode of the 3rd NMOS tube (M2), the drain electrode of the 3rd PMOS (M6) and the drain electrode of the first NMOS tube (M0) are connected to the 3rd node (VP), first node (VA) is on the connecting line of the drain electrode of the 3rd NMOS tube (M2) and the drain electrode of the second PMOS (M4), and first node (VA) is connected to differential data positive output end (OUTP), Section Point (VB) is on the connecting line of the drain electrode of the first PMOS (M3) and the drain electrode of the second NMOS tube (M1), and Section Point (VB) is connected to differential data negative output terminal (OUTN), the grid of the first PMOS (M3) and the second PMOS (M4) is connected to negative edge clock (CLKN), the grid of the second NMOS tube (M1) is connected to differential data positive input terminal (INP), the grid of the 3rd NMOS tube (M2) is connected to differential data negative input end (INN), and the grid of the first NMOS tube (M0) and the 3rd PMOS (M6) is connected to just along clock (CLKP).
5. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, is characterized in that, described buffer adopts current mode logic circuit.
6. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, it is characterized in that, described even data road splitter is by a pair 1/4 speed difference quadrature clocks: the first differential clocks (CKE10) and the second differential clocks (CKEX10) control, and described odd data road splitter is by a pair 1/4 speed difference quadrature clocks: the 3rd differential clocks (CKO10) and the 4th differential clocks (CKOX10) control; First differential clocks (CKE10), the 3rd differential clocks (CKO10), the second differential clocks (CKEX10), the 4th differential clocks (CKOX10) differ 90 degree of phase places successively.
7. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, it is characterized in that, described dynamic conjunction road summer embeds sum unit by mixer and realizes, comprise 2 pairs of differential clocks inputs, 4 pairs of differential data input terminal and 1 pair of differential data output.
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| JP7181470B2 (en) | 2018-02-08 | 2022-12-01 | 株式会社ソシオネクスト | Summing circuits, receiving circuits and integrated circuits |
| CN111684715B (en) * | 2018-02-08 | 2023-05-02 | 株式会社索思未来 | Amplifying circuit, adding circuit, receiving circuit and integrated circuit |
| US11901868B2 (en) | 2018-02-08 | 2024-02-13 | Socionext Inc. | Amplifier circuit, adder circuit, reception circuit, and integrated circuit |
| CN112422461A (en) * | 2020-11-05 | 2021-02-26 | 硅谷数模(苏州)半导体有限公司 | Decision feedback equalizer and data acquisition and correction method |
| TWI776437B (en) * | 2020-11-05 | 2022-09-01 | 大陸商硅谷數模半導體(蘇州)有限公司 | Decision feedback equalizer and data acquisition and correction method |
| CN114650200A (en) * | 2020-12-21 | 2022-06-21 | 智原科技股份有限公司 | Dynamic module and decision feedback equalizer |
| CN114650200B (en) * | 2020-12-21 | 2023-08-18 | 智原科技股份有限公司 | Dynamic module and decision feedback equalizer |
| CN113364711A (en) * | 2021-05-13 | 2021-09-07 | 北京大学（天津滨海）新一代信息技术研究院 | Decision feedback equalizer |
| CN113364711B (en) * | 2021-05-13 | 2022-07-19 | 北京大学（天津滨海）新一代信息技术研究院 | Decision feedback equalizer |
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