CN114650200B

CN114650200B - Dynamic module and decision feedback equalizer

Info

Publication number: CN114650200B
Application number: CN202110517696.5A
Authority: CN
Inventors: 帕提·库马尔·哥雅
Original assignee: Faraday Technology Corp
Current assignee: Faraday Technology Corp
Priority date: 2020-12-21
Filing date: 2021-05-12
Publication date: 2023-08-18
Anticipated expiration: 2041-05-12
Also published as: TWI751017B; CN114650200A; US11044124B1; TW202226770A

Abstract

The invention relates to a dynamic module and a decision feedback equalizer. The decision feedback equalizer comprises two dynamic modules with symmetrical circuits and connection modes. The dynamic module comprises a first domino circuit, a second domino circuit and a storage circuit. The first multiplexed output and the second multiplexed output are generated in response to the first previous decision bit and the second previous decision bit. With the variation of the clock signal, the dynamic module runs alternately between the evaluation period and the precharge period. During the evaluation period, the first multiplexing output and the second multiplexing output are updated by the first domino circuit and the second domino circuit. During precharge, the memory circuit maintains the first multiplexed output and the second multiplexed output.

Description

Dynamic module and decision feedback equalizer

Technical Field

The present invention relates to a dynamic module and a decision feedback equalizer, and more particularly, to a dynamic module and a decision feedback equalizer capable of alleviating a time margin of a speculative first-tap (tap 1).

Background

Please refer to fig. 1, which is a schematic diagram of a transmission path between a transmitter and a receiver. The data transmitted by the transmitter 11 to the receiver 13 is distorted in the transmission path 12. Therefore, the receiver 13 needs to restore the distorted data. The causes of the data distortion are not the same, one of which is inter-symbol interference (inter-symbol interference, abbreviated ISI) caused by the previous symbol.

To reduce ISI, a continuous-time linear equalizer (CTLE) 131 and a decision feedback equalizer (decision feedback equalizer, DFE) 133 are currently used and applied to the receiver 13. In short, CTLE can adjust the gain in the frequency domain, while DFE 13 can process ISI-derived signals without amplifying noise. Thus, the CTLE 131 and DFE 133 can be collocated to remove ISI and enhance signal-to-noise ratio (SNR). Then, the DFE outputs D _out Will be passed to a Serializer/Jie Chuanlie device (Serializer/Deserializer, simply SerDes) 135.

Please refer to fig. 2, which is a schematic diagram of the DFE structure. DFE 133 includes adder 133a, sense amplifier 133b, and RS latch 133c. Adder 133a receives input data D _in After the first tap (tap 1) is presumed, the input data D _in The result of the addition with the speculative first tap (tap 1) is sent to the sense amplifier 133b. The clock signal CLK triggers the sense amplifier 133b and the RS latch 133.

SensingThe amplifier 133b outputs the amplified signal to the RS-latch 133c, and the RS-latch 133c generates the DFE output D _out . Since DFE 133 is associated with multiple steps, and DFE 133 must adjust its operation in real-time and in a recursive manner, the design of DFE 133 is complicated. In high frequency (e.g., above 10 GHz) applications, the speed of the taps is quite critical, making the design of DFE 133 challenging.

Disclosure of Invention

The present disclosure relates to a dynamic module and a decision feedback equalizer. By effectively integrating the multiplexer and the dynamic latch as a dynamic block, the propagation delay can be reduced and the operating margin of the speculative first-order tap (tap 1) can be mitigated.

According to a first aspect of the invention, a dynamic module is presented. The dynamic module comprises a first domino circuit and a second domino circuit. The first domino circuit generates a first multiplexed output. The first domino circuit includes: the first multiplexer, at least one first phase setting circuit and the first decision selecting stage circuit. The first multiplexer receives two of the first monorail output, the second monorail output, the third monorail output, and the fourth monorail output. At least one first phase setting circuit receives a first clock signal. The first decision selecting stage circuit is electrically connected to the first multiplexer and the at least one first phase setting circuit. A first decision selection stage circuit receiving a first previous decision bit and a second previous decision bit. Wherein the first predetermined bit and the second predetermined bit are complementary to each other. The second domino circuit is electrically connected with the first domino circuit and generates a second multiplexing output. The second domino circuit includes: the second multiplexer, at least one second phase setting circuit and the second decision selecting stage circuit. The second multiplexer receives the other two of the first monorail output, the second monorail output, the third monorail output, and the fourth monorail output. The at least one second phase setting circuit receives a second clock signal. Wherein the first clock signal and the second clock signal are complementary. The second decision selecting stage circuit is electrically connected to the second multiplexer and the at least one second phase setting circuit. The second decision selecting stage receives the first and second previous decision bits. During the review, the first multiplexed output and the second multiplexed output are selectively updated with the first single track output, the second single track output, the third single track output, and the fourth single track output. The first multiplexed output and the second multiplexed output remain unchanged during the precharge.

According to a second aspect of the present invention, a decision feedback equalizer is presented. The decision feedback equalizer comprises a first speculative path and a second speculative path. The first speculative path provides a first previous decision bit and a second previous decision bit during the evaluation. Wherein the first predetermined bit and the second predetermined bit are complementary to each other. The second speculative path is electrically connected to the first speculative path. The second speculative path comprises: the first sense amplifier, the second sense amplifier, and the dynamic module. The first sense amplifier output comprises a first rail-to-rail output pair of a first monorail output and a second monorail output. The second sense amplifier output comprises a second rail-to-rail output pair of a third monorail output and a fourth monorail output. The dynamic module is electrically connected to the first sense amplifier and the second sense amplifier. The dynamic module comprises a first domino circuit and a second domino circuit which are electrically connected with each other. The first domino circuit generates a first multiplexed output and the second domino circuit generates a second multiplexed output. The first domino circuit includes: the first multiplexer, at least one first phase setting circuit and a first decision selecting stage circuit. The first multiplexer receives two of the first monorail output, the second monorail output, the third monorail output, and the fourth monorail output. At least one first phase setting circuit receives a first clock signal. The first decision selecting stage circuit is electrically connected to the first multiplexing and at least one first phase setting circuit. The first decision selecting stage receives a first previous decision bit and a second previous decision bit. The second domino circuit includes: the second multiplexer, at least one second phase setting circuit and the second decision selecting stage circuit. A second multiplexer receives the first monorail output, the second monorail output, the third monorail output, and the other two of the four monorail outputs. The at least one second phase setting circuit receives a second clock signal. Wherein the first clock signal and the second clock signal are complementary to each other. The second decision selecting stage circuit is electrically connected to the second multiplexer and the at least one second phase setting circuit. The second decision selecting stage receives the first and second previous decision bits. During the evaluation, the first multiplexed output and the second multiplexed output are selectively updated with one of the first rail-to-rail output pair and the second rail-to-rail output pair. The first multiplexed output and the second multiplexed output remain unchanged during the precharge.

For a better understanding of the above and other aspects of the invention, reference will now be made in detail to the following examples, examples of which are illustrated in the accompanying drawings.

Drawings

Fig. 1 is a schematic diagram of a conveyance path.

Fig. 2 is a schematic diagram of a DFE structure.

Fig. 3 is a schematic diagram of a speculative DFE.

FIG. 4 is a waveform diagram during an operation where even and odd speculative paths are interleaved with each other.

Fig. 5A is a schematic diagram of an example of a speculative DFE.

Fig. 5B is a schematic diagram of another example of a speculative DFE.

Fig. 6 is a schematic diagram for comparing the delay causes in the speculative DFE of fig. 5A and 5B.

Fig. 7 is a general block diagram of a dynamic module contemplated in accordance with the present disclosure.

Fig. 8A is a block diagram of a dynamic module according to a first embodiment of the present disclosure.

Fig. 8B is a schematic diagram of a circuit design of a dynamic module according to a first embodiment of the present disclosure.

FIG. 9 is a diagram illustrating how a dynamic module according to a first embodiment of the present disclosure is during a precharge period T _pre Schematic representation of the operation.

FIG. 10A, which is a block of bits S in the forward direction _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the dynamic module according to the first embodiment of the present disclosure is in the evaluation period T _eva Schematic representation of the operation.

FIG. 10B, which is a block of bits S in the forward direction _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the dynamic module according to the first embodiment of the present disclosure is in the evaluation period T _eva Schematic representation of the operation.

FIG. 11 is a schematic diagram showing a dynamic module according to a first embodiment of the present disclosure, T during precharge _pre And evaluation period T _eva Summary table of signal states at that time.

Fig. 12 is a waveform diagram illustrating how a speculative DFE according to a first embodiment of the present disclosure processes a data stream, for example.

Fig. 13A is a block diagram of a dynamic module according to a second embodiment of the present disclosure.

Fig. 13B is a schematic diagram of a circuit design of a dynamic module according to a second embodiment of the present disclosure.

FIG. 14 is a dynamic module according to a second embodiment of the present disclosure, during a precharge period T _pre Schematic representation of the operation.

FIG. 15A, which is a block of bits S in the forward direction _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the dynamic module according to the second embodiment of the disclosed concept is in the evaluation period T _eva Schematic representation of the operation.

FIG. 15B, which is a forward direction prior to determining the bits S _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the dynamic module according to the second embodiment of the disclosed concept is during the evaluation period T _eva Schematic representation of the operation.

FIG. 16 is a schematic diagram of a second embodiment of an upper bone plate circuit according to the present disclosure, during review period T _eva A flow chart of operation.

FIG. 17 is a schematic diagram showing the precharge period T _pre And evaluation period T _eva Dynamic module according to a second embodiment of the present disclosureA summary table of signal states of (a).

Fig. 18 is a waveform diagram of an example processing a data stream according to a speculative DFE of a second embodiment contemplated by the present disclosure.

Fig. 19A is a block diagram of a dynamic module according to a third embodiment contemplated by the present disclosure.

Fig. 19B is a schematic diagram of a circuit design of a dynamic module according to a third embodiment of the present disclosure.

FIG. 20 is a dynamic module according to a third embodiment contemplated by the present disclosure, during precharge period T _pre Schematic of how to operate.

FIG. 21A, which is a block of bits S in the forward direction _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the dynamic module according to the third embodiment of the present disclosure is in the evaluation period T _eva Schematic representation of the operation.

FIG. 21B, which is a forward direction prior to determining the bits S _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the dynamic module according to the third embodiment of the present disclosure is in the evaluation period T _eva Schematic representation of the operation.

FIG. 22 is a schematic diagram of a third embodiment of an upper bone plate circuit according to the present disclosure, during review period T _eva A flow chart of operation.

FIG. 23, which is a program during precharge period T _pre And evaluation period T _eva Summary table of signal states of dynamic modules according to a third embodiment contemplated by the present disclosure.

Fig. 24 is a schematic diagram of a speculative DFE with a quarter-rate structure.

Wherein reference numerals are as follows:

11: conveyor

12: transmission path

13: receiver with a receiver body

131: continuous time linear equalizer

133: decision feedback equalizer

135: serializer/Jie Chuanlie device

133a,211 b,231a,231b,311a,311b: adder device

D _in In (a), in (B), in (C), in (D), in (E), in (F): input data

Tap1: first order tap

133b,213a,213b,233a,233b,313a,313b, 313a, 333b: sense amplifier

CLK: clock signal

133c: RS latch

D _out : DFE output

15：DFE

151, 21: even number speculative paths

153, 23: odd number of speculative paths

D _{out_evn} : even path determination

D _{out_odd} : odd path determination

Clk_l (even): even-path forward latch clock signal

Clk_l (odd): odd path forward latch clock signal

Clkb_l (even): even path reverse latch clock signal

Clkb_l (odd): odd path reverse latch clock signal

T _eva : during the evaluation period

T _pre : during precharge

T (n), T (n+1), T (n+2), T (n+3), T1, T2, T3, T4, T5: during the period of time

APevn: positive monorail output of first even path

ANevn: negative monorail output of first even path

BPevn: positive monorail output of second even path

BNevn: negative monorail output of second even path

215a,215b,235a,235b: latch device

MUX _{evn_in1} ，MUX _{evn_in2} ，MUX _{odd_in1} ，MUX _{odd_in2} : multiplex input

217, 237, 611, 631, 711, 731, 811, 831: multiplexer

MUX _{evn_out} ，MUX _{odd_out} : multiplex output

219, 239: trigger device

2,3, 90: speculative DFE

APodd, ANodd, BPodd, BNodd: monorail output

31: even number speculative paths

315: even number dynamic module

315a,335a,51, 61, 71, 81: upper bone plate circuit

315b,335b,53, 63, 73, 83: lower bone plate circuit

315c,335c,55, 65, 75, 85: memory circuit

MXOPevn, mx (C): forward multiplexed output of even paths

MXONevn, mxb (C): inverse multiplexing output of even paths

317a,317b: reverser

SB _evn ，SB _odd ，SB _po : reverse previous decision bits

S _evn ，S _odd ，S _po : forward previous decision bits

33: odd number of speculative paths

331a,331b: adder device

335: odd number dynamic module

MXOPodd, mx (B), mx (D): forward multiplexed output of odd paths

MXONodd, mxb (B), mxb (D): inverse multiplexing output of odd paths

337a,337b, sinv1, sinv2, uinv1, uinv2, linv1, linv2: reverser

Clkb_l: reverse latching clock signal

UI: data unit interval

t1 to t7: time point

T _clk2sa : clock transfer delay

T _suSA : setting time

T _latch ，T _dyn ，T _mux : transfer delay

C1 C2: virtual coil selection

ΔT _tap1 ，ΔT _tap1 ': operation margin

Clk_l: forward latch clock signal

AP: first positive monorail output

AN: first negative monorail output

BP: second positive monorail output

BN: second negative monorail output

Clkb_l: reverse latching clock signal

5,6,7,8: dynamic module

N _mxop : forward multiplexing output terminal

N _mxon : inverse multiplexing output terminal

MXOP: forward multiplexed output

MXON: inverse multiplexing output

613, 633, 713, 733, 813, 833: dynamic latch

313 a,633a, 313 c, 7333 c, 803 c, 8333 c: decision selection stage circuit

313 a, 313 b,733a,733b, 313 a, 803 b,833a,833b: phase setting circuit

N _m1 ，N _m2 : intermediate endpoint

Vcc: supply voltage terminal (supply voltage)

Gnd: grounding endpoint (grounding voltage)

uP, lP1, lP2, llatP1, llatP2, lP, unoP1, unoP2, upoP1, upoP2, upP, uinP, unP, lnoP1, lnoP2, lpoP1, lpoP2, lpP, linP, lnP, upoP, unoP, lpoP, lnoP: PMOS transistor

uN, ultN 1, ultN2, uN1, uN2, lN, unoN2, unoN1, upoN2, upoN1, upN, uin, unN, lnoN2, lnoN1, lpoN2, lpoN1, lpoN, linN, lnN, upoN, unoN, lpoN, lnoN: NMOS transistor

Clk_sys: system clock signal

sa (A), sa (B), sa (C), sa (D), sa (E), sa (F): sampling data

sa (A) +, sa (C) +, sa (E) +. Rail-to-rail output pair of second even path

sa (B) +, sa (D) +: rail-to-rail output pair of second odd path

sa (A) -, sa (C) -, sa (E) -: rail-to-rail output pair of first even path

sa (B) -, sa (D) -: rail-to-rail output pair of first odd path

611 b,831b: negative electrode output circuit

611 a,831a: positive electrode output circuit

sa_p, sa_n, sb_p, sb_n: selection signal

N _ap ，N _an ，N _bp ，N _bn : selecting an endpoint

S71, S71a, S71b, S73a, S73b, S75a, S75b, S77, S81a, S81b, S83a, S83b, S85a, S85b, S87: steps 91, 92, 93, 94: speculative path

D _{out_p1} ，D _{out_p2} ，D _{out_p3} ，D _{out_p4} : path determination

Detailed Description

Of all the taps, the time limit of the first tap (tap 1) is most severe, i.e., one Unit Interval (UI). To relax the time constraint of the first tap (tap 1), the DFE may be designed in a speculative (loop-unrolling) manner. With the speculative structure, the speculative DFE includes even and odd speculative paths, and the time limit of the speculative first tap (tap 1) can be extended to twice the data unit interval (2 ui).

Please refer to fig. 3, which is a schematic diagram of the speculative DFE. DFE 15 includes even speculation paths 151 and odd speculation paths 153. Even speculation path 151 receives input data D _in And generates an even path decision D _{out_evn} . Wherein the even path determines D _{out_evn} Further feed into odd number presumption path153 are referenced by an odd numbered speculative path 153. Odd speculation path 153 receives input data D _in And generates an odd path decision D _{out_odd} . Wherein the odd path determines D _{out_odd} Further fed into even speculation path 151 for reference by even speculation path 151. DFE output D _out Determining D by alternately adopting even paths _{out_evn} And odd path decision D _{out_odd} 。

Please refer to fig. 4, which is a waveform diagram during an operation of interleaving even-numbered speculative paths and odd-numbered speculative paths. The horizontal axis is time, and the vertical axis is waveforms of the forward latch clock signal clk_l (even) of the even path and the forward latch clock signal clk_l (odd) of the odd path. The even-path forward latch clock signal clk_l (even) is provided to the even-speculation path 151, and the odd-path forward latch clock signal clk_l (odd) is provided to the odd-speculation path 153.

When the forward latch clock signal clk_l (even) of the even path is at a high logic level (clk_l (even) =1), the even speculative path 151 operates in the evaluation phase. The period during which even-numbered speculative path 151 runs in the review phase is defined as a review period T corresponding to even-numbered speculative path 151 _eva . When the forward latch clock signal clk_l (even) of the even path is at a low logic level (clk_l (even) =0), the even speculative path 151 operates in the precharge phase. The period during which even-numbered speculative path 151 operates in the precharge phase is defined as precharge period T corresponding to even-numbered speculative path 151 _pre 。

When the positive latch clock signal clk_l (odd) of the odd path is at a high logic level (clk_l (odd) =1), the odd speculative path operates in the evaluate phase. The period during which the odd speculative path 153 runs in the review phase is defined as the review period T corresponding to the odd speculative path 153 _eva . When the positive latch clock signal clk_l (odd) of the odd path is at a low logic level (clk_l (odd) =0), the odd speculative path 153 operates in the precharge phase. The period during which the odd speculative path 153 operates in the precharge phase is defined as a precharge period T corresponding to the odd speculative path 153 _pre 。

Even path forward latch clock signalThe phases of the positive clk_l (odd) and the negative clk_l (odd) of the odd paths are complementary to each other, and the operation phases of the even-numbered speculative path 151 and the odd-numbered speculative path 153 are switched alternately with each other. During T (n), T (n+2), even speculative path 151 runs in the evaluate phase and odd speculative path 153 runs in the precharge phase. During T (n+1), T (n+3), even speculative path 151 runs in the precharge phase and odd speculative path 153 runs in the evaluate phase. Accordingly, when even speculative path 151 is in comment period T _eva When the odd speculative path 153 is in the precharge period T _pre And vice versa.

Fig. 5A and 5B show two examples of speculative DFEs having a loop expansion structure. Fig. 5A, 5B illustrate that even speculative path 151 has a similar and symmetrical design to odd speculative path 153.

Please refer to fig. 5A, which is a schematic diagram of an example of a speculative DFE. The speculative DFE 2 includes an even speculative path 21 and an odd speculative path 23. Even-numbered speculation path 21 includes adders 211a, 211b, sense amplifiers 213a, 213b, latches 215a, 215b, multiplexer 217, and flip-flop 219. Odd speculation path 23 includes adders 231a, 231b, sense amplifiers 233a, 233b, latches 235a, 235b, multiplexer 237, and flip-flop 239.

The sense amplifiers 213a, 213b, 233a, 233b each operate based on a corresponding latch clock signal clk_l, and each sense amplifier 213a, 213b, 233a, 233b has a differential input and a dual rail output. The operation of the sense amplifiers 213a, 213b in the even-numbered speculation path 21 and the operation of the sense amplifiers 233a, 233b in the odd-numbered speculation path 23 are symmetrical to each other. For example, when the forward latch clock signal clk_l (even) of the even-numbered path is at a high logic level, the sense amplifiers 213a, 213b located in the even-numbered speculative path 21 continue to perform the sample-and-hold operation, and the sense amplifiers 233a, 233b located in the odd-numbered speculative path 23 stop their operation. And vice versa. When the sense amplifiers 213a, 213b, 233a, 233b continue the sample and hold operation, one of the two outputs belonging to the same sense amplifier 213a, 213b, 233a, 233b (depending on the polarity of the input differential voltage) is set to the amplifier supply voltage level; the other is maintained at the amplifier ground voltage level (low logic level).

Even speculative path 21 alternates with odd speculative path 23 to receive input data D _in And decides D in response to generating even paths corresponding to it _{out_evn} Odd path determination D _{out_odd} . Odd speculative path 23 receives even path decision D from even speculative path 21 _{out_evn} And even speculative path 21 receives odd path decision D from odd speculative path 23 _{out_odd} 。

Next, the operation of the even-numbered speculative path 21 in DFE 2 will be described. The adders 211a, 211b simultaneously receive the input data D _in And a speculative first tap (tap 1). Adder 211a receives input data D _in After subtracting the speculative first tap (tap 1), the adder output (D _in Tap 1) to sense amplifier 213a. Adder 211b combines the speculative first-order tap (tap 1) with the input data D _in Adding (D) _in After +tap 1), the adder output (D _in +tap 1) to sense amplifier 213b.

The sense amplifier 213a outputs (D _in Tap 1), producing an positive monorail output APevn of the first even path and a negative monorail output ANevn of the first even path. The sense amplifier 213b outputs (D) according to the adder output of the adder 211b _in +tap 1), producing a positive monorail output BPevn of the second even path and a negative monorail output BNevn of the second even path.

Latch 215a receives the positive monorail output APevn of the first even path and the negative monorail output ANevn of the first even path from sense amplifier 213a and generates an even path multiplexed input MUX therefrom _{evn_in1} . Latch 215b receives the positive single-rail output BPevn of the second even path and the negative single-rail output BNEVn of the second even path from sense amplifier 213b and generates an even path multiplexed input MUX accordingly _{evn_in2} . The multiplexer 217 outputs D according to the odd path determination _{out_odd} Selecting a multiplexed input MUX _{evn_in1} 、MUX _{evn_in2} One of (2) as a multiplexed output MUX _{evn_out} . Will multiplex to output MUX _{evn_out} Further to trigger 219. Flip-flop 219 provides even path decision output D _{out_evn} To the odd speculative path 23.

Since the operation of the odd speculative path 23 is similar to that of the even speculative path 21, details thereof will not be described in detail. Note that the source and weight of the speculative first-order tap (tap 1) need not be limited herein, and the speculative DFE may have multiple taps.

Please refer to fig. 5B, which is a schematic diagram of another example of the speculative DFE. The speculative DFE 3 includes an even speculative path 31 and an odd speculative path 33. Even speculation path 31 includes adders 311a and 311b, sense amplifiers 313a and 313b, even dynamic block 315, and inverters 317a and 317b. The odd speculation path 33 includes adders 331a, 331b, sense amplifiers 333a, 333b, an odd dynamics module 335, and inverters 337a, 337b.

The even dynamic module 315 is similar in design to the odd dynamic module 335. The even dynamic block 315 includes an upper tile circuit 315a, a lower tile circuit 315b, and a memory circuit 315c. Odd dynamic block 335 includes an upper tile circuit 335a, a lower tile circuit 335b, and a memory circuit 335c. Table 1 summarizes the operation of the elements of the speculative DFE 3.

TABLE 1

As can be seen from Table 1, the even and odd speculative paths 31 and 33 operate similarly and symmetrically with respect to each other, so that the even and odd dynamic modules 315 and 335 can be implemented in the same manner. The even dynamic block 315 and the odd dynamic block 335 differ in their sources of input signals and use multiplexed outputs of each other.

In FIG. 5B, even dynamic block 315 integrates the functions of latches 215a, 215B and multiplexer 217, and odd dynamic block 335 integrates the functions of latches 235a, 235B and multiplexer 237. The even dynamic block 315 and the odd dynamic block 335 are designed in a dynamic logic manner to perform the latching and multiplexing operations efficiently.

Please refer to fig. 6, which is a diagram comparing the delay causes in the speculative DFE of fig. 5A and 5B. The horizontal axis of fig. 6 is time. The period from the time t1 to the time t7 corresponds to the time limit of the first-order tap (tap 1). I.e. two data unit intervals (2 ui). The upper graph of fig. 6 shows the cause of the delay of the speculative DFE 2, and the lower graph of fig. 6 shows the cause of the delay of the speculative DFE 3.

The delay causes of the speculative DFE 2 include: clock transfer delay (between time T1 and time T2) of the sense amplifiers 213a and 213b, and set time T of the sense amplifiers 213a and 213b _suSA (between time T2 and time T3), the transfer delay T of the multiplexer latches 215a, 215ba _latch (between time T3 and time T4), and the transfer delay T of the multiplexer 217 _mux (between time t4 and time t 6). The difference between the two times data unit interval (2 UI) and the sum of the delay factors of the speculative DFE 2 (i.e., time T6 to time T7) is the operational margin DeltaT of the first tap (tap 1) when the speculative DFE 2 is used _tap1 。

The delay causes of the speculative DFE 3 include: clock transfer delay T of sense amplifiers 313a, 313b _clk2sa (between time T1 and time T2), the set time T of the sense amplifiers 313a, 313b _suSA (between time T2 and time T3), and the propagation delay T of the odd/even dynamic blocks 315, 335 _dyn (between time t3 and time t 5). The difference between the two times data unit interval (2 UI) and the sum of delay causes of the speculative DFE 3 (i.e., the period from time T5 to time T7) is the operational margin DeltaT of the first tap (tap 1) when the speculative DFE 3 is selected _tap1 ’。

Virtual circle choice C1 is the propagation delay along the odd/even speculative paths in FIG. 5A. Virtual circle choice C2 is the propagation delay along the odd/even speculative path in FIG. 5B. Comparing the virtual coil choices C1 and C2, the dotted line can be found The period of the circled position C1 is longer than that of the circled position C2 with a broken line. And, the operation margin DeltaT of the speculative first-order tap (tap 1) of FIG. 5B _tap1 ' is smaller than the operation margin DeltaT of the speculative first-order tap (tap 1) in FIG. 5A _tap1 Longer. Thus, the speculative DFE 3 of fig. 5B may provide a speculative first-order tap (tap 1) with better tolerance.

Referring to fig. 7, a generalized block diagram of a dynamic module contemplated in accordance with the present disclosure is shown. The dynamic module 5 includes an upper bone plate circuit 51, a lower bone plate circuit 53, and a memory circuit 55. The dynamic module 5 may be either the even dynamic module 315 or the odd dynamic module 335 in fig. 5B. Table 2 shows the correspondence of the signals in fig. 5B and 7.

TABLE 2

The upper bone plate circuit 51 and the lower bone plate circuit 53 receive three input signals, including: the forward/reverse latch clock signals (CLK_L, CLKB_L), the first rail-to-rail output pair (AP, AN), the second rail-to-rail output pair (BP, BN), and the previous decision bits (S _po ，SB _po ). Previously determined bits (S) _po ，SB _po ) Is received from other dynamic blocks, and the forward latch clock signal clk_l, the reverse latch clock signal clkb_l is received from other circuits (e.g., PLL) in the system.

The memory circuit 55 is electrically connected to the forward multiplexing output node N _mxop And an inverse multiplexing output terminal N _mxon To bridge the upper domino circuit 51 and the lower domino circuit 53. The forward multiplexing output MXOP is at the forward multiplexing output node N _mxop Generates an inverse multiplexing output MXON at an inverse multiplexing output terminal N _mxon And (3) generating.

Some symbols are used herein to represent the state of a signal. Herein, the symbol "X" indicates that a variation in the signal does not affect the operation of the circuit; the signal is represented by the symbol "Z" as floating (high impedance).

According to an embodiment of the present disclosure, the dynamic module 5 operates in a dual phase. During the evaluation period T _eva The dynamic module 5 determines the bits S based on the forward previous bits _po Reverse previous decision bit SB _po The forward multiplexed output MXOP and the inverse multiplexed output MXON are updated with one of the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN). During the precharge period T _pre The dynamic module 5 maintains the forward multiplexed output MXOP and the inverse multiplexed output MXON unchanged without updating.

The present disclosure illustrates the practice of the dynamic module 5 in three embodiments. Fig. 8A, 8B, 9, 10A, 10B, 11, and 12 show a first embodiment. Fig. 13A, 13B, 14, 15A, 15B, 16, 17, and 18 show a second embodiment. Fig. 19A, 19B, 20, 21A, 21B, 22, and 23 show a third embodiment. These embodiments will be presented in a comparison table of block diagrams, circuit designs, signal states, and illustrate the operation of dynamic modules based on these embodiments. Note that the implementation of the present disclosure is not limited to the following embodiments.

First embodiment

Fig. 8A and 8B are a block diagram and a circuit design of the dynamic module 6 according to the first embodiment of the present disclosure, respectively. FIG. 9 illustrates dynamic module 6 during precharge period T _pre Is a function of the operation of (a). FIGS. 10A and 10B illustrate the dynamic module 6 during the review period T _eva Is a function of the operation of (a). FIG. 11 illustrates dynamic module 6 during precharge period T _pre And evaluation period T _eva A summary table of signal states of (a). Fig. 12 illustrates how the dynamic module 6 is applied to the speculative DFE 3.

Referring to fig. 8A, a block diagram of a dynamic module according to a first embodiment of the present disclosure is shown. The dynamic module 6 includes an upper bone plate circuit 61, a lower bone plate circuit 63, and a memory circuit 65. The memory circuit 65 is connected to the forward multiplexer node N _mxop Electrically connected to the upper bone plate circuit 61 and via the inverse multiplexer terminal N _mxon And is electrically connected to the lower partDomino circuit 63.

The upper card circuit 61 further includes a multiplexer 611 and a dynamic latch 613, and the lower card circuit 63 further includes a multiplexer 631 and a dynamic latch 633. The dynamic latch 613 includes a decision selecting stage circuit 613a and a phase setting circuit 613b, and the dynamic latch 633 includes a decision selecting stage circuit 633a and a phase setting circuit 633b.

Please refer to fig. 8B, which is a schematic diagram of a circuit design of the dynamic module according to the first embodiment of the present disclosure. In the above bone plate circuit 61, the multiplexer 611 includes NMOS transistors uN1 and uN2, the decision selecting stage circuit 613a includes NMOS transistors ultn 1 and ultn 2, and the phase setting circuit 613b includes PMOS transistors uP and uN. In the lower bone plate circuit 63, the multiplexer 631 includes PMOS transistors lP1 and lP2, the decision selecting stage circuit 633a includes PMOS transistors llatP1 and llatP2, and the phase setting circuit 633b includes PMOS transistors lP and NMOS transistors lN. The memory circuit 65 includes inverters sinv1, sinv2.

Next, the signals and connection relations of the multiplexer 611, the decision selecting stage circuit 613a, and the phase setting circuit 613b in the upper bone plate circuit 61 will be described. In the multiplexer 611, the drains of the NMOS transistors uN1, uN2 are electrically connected to the decision stage circuit 613a; the sources of the NMOS transistors uN1, uN2 are electrically connected to a ground terminal (Gnd). The gate of NMOS transistor uN1 receives the first positive monorail output AP and the gate of NMOS transistor uN2 receives the second positive monorail output BP.

In the decision stage 613a, the drains of the NMOS transistors ultN 1 and ultN 2 are electrically connected to the intermediate node N _m1 And the sources of the NMOS transistors ultn 1, ultn 2 are electrically connected to the drains of the NMOS transistors uN1, uN2 in the multiplexer 611, respectively. The gate of NMOS transistor ultN 1 receives the forward previous decision bit Spo and the gate of NMOS transistor ultN 2 receives the backward previous decision bit SB _po 。

In the phase setting circuit 613b, the source of the PMOS transistor uP is electrically connected to the supply voltage terminal (Vcc), and the source of the NMOS transistor uN is electrically connected to the intermediate terminal N _m1 . The gates of the PMOS transistor uP and the NMOS transistor uN are electrically connected to each other,to receive the forward latch clock signal clk_l. The drains of the PMOS transistor uP and the NMOS transistor uN are electrically connected to the forward multiplexing output terminal N _mxop 。

Next, the signals and connection relationships of the multiplexer 631, the decision selection stage 633a and the phase setting 633b in the lower bone plate circuit 63 will be described. In the multiplexer 631, the drains of the PMOS transistors lP1 and lP2 are electrically connected to the decision selection stage circuit 633a. The sources of the PMOS transistors lP1, lP2 are electrically connected to a supply voltage terminal (Vcc). The gate of PMOS transistor lP1 receives the first negative monorail output AN and the gate of PMOS transistor lP2 receives the second negative monorail output BN.

In the decision selection stage 633a, the drains of the PMOS transistors, llatP1 and llatP2, are electrically connected to the intermediate node N _m2 And the sources of the PMOS transistors llatP1 and llatP2 are respectively electrically connected to the drains of the PMOS transistors lP1 and lP 2. The gate of PMOS transistor llatP1 receives the inverse previous decision bit SB _po The gate of the PMOS transistor llatP2 receives the forward previous decision bit S _po 。

In the phase setting circuit 633b, the source of the NMOS transistor lN is electrically connected to the ground terminal (Gnd), and the source of the PMOS transistor lP is electrically connected to the middle terminal N _m2 . The gates of the PMOS transistor lP and the NMOS transistor lN are electrically connected to each other for receiving the inverted latch clock signal ckb_l. The drains of the PMOS transistor lP and the NMOS transistor lN are electrically connected to the inverse multiplexing output terminal N _mxon 。

In the memory circuit 65, the input terminal and the output terminal of the inverter sin v1 are electrically connected to the forward multiplexing output terminal N _mxop And an inverse multiplexing output terminal N _mxon . The input and output terminals of the inverter sin v2 are electrically connected to the inverse multiplexing output terminal N _mxon And forward multiplexing output terminal N _mxop 。

Please refer to fig. 9, which illustrates how the dynamic module according to the first embodiment of the present disclosure is during the precharge period T _pre Schematic representation of the operation. The operation of the upper bone plate circuit 61 and the lower bone plate circuit 63 will be described below.

Next, description is given aboveThe elements in domino circuit 61 during precharge period T _pre Is a function of the operation of (a). In the phase setting circuit 613b, the PMOS transistor uP is turned on, and the NMOS transistor uN is turned off. Therefore, the forward multiplexing output MXOP is equal to the supply voltage Vcc (mxop=1), and the decision selecting stage 613a and the multiplexer 61 do not affect the forward multiplexing output terminal N _mxop . Accordingly, the forward multiplexed output MXOP is independent of the input of the upper bone plate circuit 61 (i.e., the first positive monorail output AP and the second positive monorail output AP). The disabled multiplexer 611 and the decision selection stage 613a are shown at the bottom of the dot.

The following describes the elements in the underlying bone plate circuit 63 during the precharge period T _pre Is a function of the operation of (a). In the phase setting circuit 633b, the PMOS transistor lP is turned off, and the NMOS transistor lN is turned on. Therefore, the inverse multiplexing output MXON is equal to the ground voltage Gnd (mxon=0), and the selection stage 633a and the multiplexer 631 are determined not to affect the inverse multiplexing output terminal N _mxon . Accordingly, the inverse multiplex output MXON is independent of the input of the underlying bone plate circuit 63 (i.e., the first negative monorail output AN and the second negative monorail output BN). The disabled multiplexer 631 and the decision selection stage 633a are shown at the bottom of the dot.

FIGS. 10A and 10B illustrate the dynamic module 6 during the review period T _eva In operation, the signals and element states of the dynamic module 6. In the dynamic module 6, the PMOS transistors and the NMOS transistors in the decision selection stage 613a, 633a and the multiplexers 611, 631 can be divided into four branches according to their positions and connection modes. These four branches comprise: lower left branch (NMOS transistors ultn 1, uN 1), lower right branch (NMOS transistors ultn 2, uN 2), upper left branch (PMOS transistors lP1, llatP 1), and upper right branch (PMOS transistors lP2, llatP 2).

Please refer to fig. 10A, which illustrates determining the bit S in the forward direction _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the dynamic module according to the first embodiment of the present disclosure is in the evaluation period T _eva Schematic representation of the operation. Please refer to fig. 10B, which illustrates determining the bit S in the forward direction _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the dynamic module according to the first embodiment of the present disclosure is in the evaluation period T _eva Schematic representation of the operation.

With the previous decision of the bit (S) _po ，SB _po ) The forward multiplexed output MXOP, the reverse multiplexed output MXON of fig. 10A, 10B may remain unchanged or be updated with one of the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN).

Next, a description will be given of how the phase setting circuit 613b, the decision selecting stage circuit 613a, and the multiplexer 611 in the upper bone plate circuit 61 are in the evaluation period T _eva And (5) running. Since the forward latch clock signal clk_l is at a high logic level (clk_l=1), the PMOS transistor uP in the phase setting circuit 613b is turned off and the NMOS transistor uN is turned on. The forward multiplexing output MXOP is determined by the decision select stage 613a and the multiplexer 611.

When forward determining the bit S _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1) (as shown in fig. 10A), the NMOS transistor ultn 1 in the selection stage 613a is determined to be turned off, and the NMOS transistor ultn 2 is determined to be turned on. In connection, because the NMOS transistor ultn 1 in the decision stage 613 is turned off, the NMOS transistor uN1 in the multiplexer 611 is turned off, and the NMOS transistor uN2 in the multiplexer 611 is turned on or off according to the change of the second positive monorail output BP. In fig. 10A, NMOS transistors ultn 1, uN1 in the lower left branch are shown with dot-like bottoms, representing that they are independent of the forward multiplexed output MXOP.

In fig. 10A, the NMOS transistor uN2 in the multiplexer 611 may be turned on or off in response to the variation of the second positive monorail output BP. If the second positive monorail output BP is at a low logic level (bp=0), the NMOS transistor uN2 located in the multiplexer 611 is turned off and the forward multiplexed output MXOP is not updated. If the second positive monorail output BP is at a high logic level (bp=1), the NMOS transistor uN2 of the multiplexer 611 is turned on to make the forward multiplexed output MXOP equal to the ground voltage Gnd (mxop=0). In brief, in fig. 10A, the forward multiplexed output MXOP is determined by the lower right branch.

When forward determining the bit S _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0) (as shown in fig. 10B), the NMOS transistor ultn 1 in the selection stage 613a is determined to be turned on, and the NMOS transistor ultn 2 is determined to be turned off. In connection, the NMOS transistor uN1 in the multiplexer 611 may be turned on or off according to the change of the first positive monorail output AP, and the NMOS transistor uN2 in the multiplexer 611 is turned off by determining that the NMOS transistor ultn 2 in the selection stage circuit 613 is turned off. In fig. 10B, the NMOS transistors ultn 2, uN2 in the lower right branch are shown with dot-like bottoms, representing that they are independent of the forward multiplexed output MXOP.

In fig. 10B, the NMOS transistor uN1 in the multiplexer 611 may be turned on or off in response to the variation of the first positive monorail output AP. If the first positive monorail output AP is at a low logic level (ap=0), the NMOS transistor uN1 located in the multiplexer 611 will be turned off and the forward multiplexed output MXOP will not be updated. If the first positive monorail output AP is at a high logic level (ap=1), the NMOS transistor uN1 of the multiplexer 611 is turned on, and the forward multiplexed output MXOP is equal to the ground voltage Gnd (mxop=0). In brief, in fig. 10B, the forward multiplexed output MXOP is determined by the lower left branch.

When the dynamic module 6 is in the evaluation period T _eva In this case, the phase setting circuit 613b, the decision selecting circuit 613a and the multiplexer 611 in the upper tile circuit 61 are sequentially operated. The phase setting circuit 613b first determines whether the forward multiplexed output MXOP is associated with the decision stage 613a and the multiplexer 611. Then, the decision stage 613a determines which of the NMOS transistors uN1, uN2 in the multiplexer 611 will affect the forward multiplexed output MXOP.

The phase setting circuit 633b, the decision selecting circuit 633a, and the multiplexer 631 of the lower bone plate circuit 63 are respectively connected to the phase setting circuit _eva Is similar to the above bone plate circuit 61. If the inverted latch clock signal clkb_l is at a low logic level (clkb_l=0), the phase setting circuit 633bThe PMOS transistor lP is on and the NMOS transistor lN is off. The inverse multiplexing output MXON is determined by the decision selector 633a and the multiplexer 631.

When forward determining the bit S _po At a low logic level (S _po =0), the previous decision bit SB is inverted _po Is at a high logic level (SB _po =1) (as shown in fig. 10A). At this time, the PMOS transistor llatP1 is turned off and the PMOS transistor llatP2 is turned on, so that the inverse multiplexing output MXON is determined by the upper right branch. Fig. 10A shows the PMOS transistors llatP1, lP1 in the upper left branch with a dot-like bottom, which is independent of the inverse multiplexing output MXON.

Alternatively, bit S is determined when forward _po At a high logic level (S _po When=1), the previous decision bit SB is inverted _po Is of low logic level (SB _po =0) (as shown in fig. 10B). At this time, the PMOS transistor llatP1 is on and the PMOS transistor llatP2 is off, so that the inverse multiplexing output MXON is determined by the upper left branch. Fig. 10B shows the PMOS transistors llatP2, lP2 in the upper right branch with a dot-like bottom, which is independent of the inverse multiplex output MXON.

When the dynamic module 6 is in the evaluation period T _eva In this case, the phase setting circuit 633b, the decision selecting circuit 633a and the multiplexer 631 in the lower tile circuit 63 are sequentially operated. The phase setting circuit 633b first determines whether the inverse multiplexing output MXON is associated with the decision selecting stage circuit 633a and the multiplexer 631. Then, the decision stage 633a determines which of the PMOS transistors lP1, lP2 in the multiplexer 631 will affect the inverse multiplexing output MXON.

Details of how the dynamic module 6 operates in response to different input signals are described above. For convenience of illustration, fig. 11 shows a combination of different input signals of the dynamic module 6, and the corresponding forward multiplexing output MXOP and the inverse multiplexing output MXON.

Please refer to fig. 11, which illustrates a dynamic module during a precharge period T according to a first embodiment of the present disclosure _pre And evaluation period T _eva A summary table of signal states of (a). According to the description of fig. 9, the dynamic module 6 is assembled here during the precharge period T _pre Is of (1)Number status. In accordance with the description of FIGS. 10A and 10B, the integration dynamics module 6 is here shown during the evaluation period T _eva Is a signal state of (a).

During the precharge period T _pre Because the forward latch clock signal clk_k is at a low logic level clk_l=0 and the reverse latch clock signal clkb_l is at a high logic level (clkb_l=1), the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN) do not affect the forward multiplexed output MXOP, the reverse multiplexed output MXON. Accordingly, the memory circuit 65 outputs the forward hold multiplexed output MXOP and the inverse multiplexed output MXON.

During the evaluation period T _eva When determining the bit S in the forward direction _po Is at a low logic level (spo=0) and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the dynamic module 6 selectively updates the forward multiplexed output MXOP, the inverse multiplexed output MXON with the second rail-to-rail output pair (BP, BN). On the other hand, during the review period T _eva When determining the bit S in the forward direction _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the dynamic module 6 selectively updates the forward multiplexed output MXOP, the inverse multiplexed output MXON to the first rail-to-rail output pair (AP, AN).

As shown in fig. 3, speculative DFE 15 operates in a recursive manner, and even speculative path 31 and odd speculative path 33 interact. To illustrate how dynamic module 6 is applied to speculative DFE 3 of fig. 5B, the signal relationships when speculative DFE 3 employs dynamic module 6 are then illustrated in a waveform diagram.

Referring to fig. 12, a waveform diagram illustrating how a speculative DFE according to a first embodiment of the present disclosure processes a data stream is shown. The upper part of fig. 12 shows waveforms of the system clock signal clk_sys, the input data in (a) to in (F), the even-path forward latch clock signal clk_l (even), and the odd-path forward latch clock signal clk_l (odd).

The even dynamic block 315 and the odd dynamic block 335 receive the system clock signal CLK_sys and the input data in (A) through in (F) simultaneously. The even dynamic block 315 receives the even path of the forward latch clock signal clk_l (even), and the odd dynamic block 335 receives the odd path of the forward latch clock signal clk_l (odd). The system clock signal clk_sys may be provided by a phase-locked loop (PLL for short).

Herein, it is assumed that the sense amplifiers 313a, 313b in the even-numbered speculation path 31 perform a sample-and-hold operation and the sense amplifiers 333a, 333b of the odd-numbered speculation path 33 suspend operation during the period in which the forward latch clock signal clk_l (even) of the even-numbered path is at a high logic level (clk_l (even) =1). Further, it is assumed here that the sense amplifiers 333a, 333b in the odd-numbered speculative path 31 perform a sample and hold operation when the positive latch clock signal clk_l (odd) of the odd-numbered path is at a high logic level (clk_l (odd) =1); sense amplifiers 313a, 313b in even speculation path 33 pause operation. However, in practical applications, the logic level of the latch clock signal used to trigger the sense amplifiers 313a, 313b, 333a, 333b is not limited to this description.

Fig. 12 shows two dashed boxes. The waveform in the upper dashed box is a signal associated with the even-numbered speculative path 31; the waveform in the dashed box below is the signal associated with the odd speculative path 33.

Fig. 12 shows input data in (a) -in (F) varying with rising and falling edges of the system clock signal clk_sys. The even-numbered estimation path 31 interleaves the input data in (a) to in (F) with the odd-numbered estimation path 33. The even-numbered estimation path 31 is triggered by the even-numbered latch clock signal clk_l (even), and processes the input data in (a), in (C), and in (E). The odd numbered speculative path 33 processes the input data in (B), in (D), in (F) after being triggered by the odd numbered path's forward latch clock signal clk_l (odd).

Due to clock transfer delay T _clk2sa For this reason, the rising edge of the even-path forward latch clock signal clk_l (even) is slightly behind the rising edge of the system clock signal clk_sys, and the falling edge of the odd-path forward latch clock signal clk_l (odd) is slightly behind the rising edge of the system clock signal clk_sys.

In the even-numbered speculative path 31, when the even-numbered path's forward latch clock signal clk_l (even) is at a high logic level (clk_l (even) =1), the sense amplifiers 313a, 313b sample the input data in (a), in (C), in (E) and generate sampled data sa (a), sa (C), sa (E). On the other hand, when the forward latch clock signal clk_l (even) of the even path is at a low logic level (clk_l (even) =0), the sense amplifiers 313a, 313b suspend operation.

In the odd-numbered speculation path 33, when the odd-numbered path's forward latch clock signal clk_l (odd) is at a high logic level (clk_l (odd) =1), the sense amplifiers 333a, 333B sample the input data in (B), in (D) and generate sampled data sa (B), sa (D). When the positive latch clock signal clk_l (odd) of the odd path is at a low logic level (clk_l (odd) =0), the sense amplifiers 333a, 333b suspend operation.

For each sample data sa (a) - (E), the speculative DFE 3 will correspondingly generate two sets of rail-to-rail output pairs. The two sets of rail-to-rail output pairs in the even speculative path 31 include: the first even path's rail-to-rail output pair (APevn, ANevn), and the second even path's rail-to-rail output pair (BPevn, BNevn). The two sets of rail-to-rail output pairs in the odd speculative path 33 include: a first odd path rail-to-rail output pair (APodd, andd), and a second odd path rail-to-rail output pair (bpod, bnod).

When the clock level of the latch clock signal clk_l (even) of the even path is equal to the high logic level (clk_l (even) =1), in the even speculative path 31, the sense amplifier 313a generates a pair of rail-to-rail outputs (APevn, ANevn) of the first even path according to the sampling data sa (a), sa (C), sa (E), and the sense amplifier 313b generates a pair of second rail-to-rail outputs (BPevn, BNevn) according to the sampling data sa (a), sa (C), sa (E). During T1, T3, T5, the rail-to-rail output pairs (APevn) of the first even path generated by the sense amplifier 313a are sa (a) -, sa (C) -, sa (E) -, respectively, corresponding to the sampled data sa (a), sa (C), sa (E); the second even path pair of rail-to-rail outputs (BPevn, BNevn) generated by the sense amplifier 313b are, respectively, sa (a) +, sa (C) +, sa (E) +, corresponding to the sampled data sa (a), sa (C), sa (E). At the same time, the clock level of the positive latch clock signal clk_l (odd) of the odd path is equal to the low logic level (clk_l (odd) =0), so the sense amplifiers 331a, 331b in the odd speculative path 33 do not sample and hold any input data.

When the clock level of the forward latch clock signal clk_l (odd) of the odd path is equal to the high logic level (clk_l (odd) =1), the clock level of the latch clock signal clk_l (even) of the even path is equal to the low logic level (clk_l (even) =0), so the sense amplifiers 311a, 311b in the even speculative path 31 do not sample and hold any input data. At this time, in the odd number estimation path 33, the sense amplifier 333a generates a rail-to-rail output pair (APodd, andd) of the first odd number path from the sampling data sa (B), sa (D), and the sense amplifier 333B generates a rail-to-rail output pair (BPodd, BNodd) of the second odd number path from the sampling data sa (B), sa (D). During T2, T4, the first odd path rail-to-rail output pair (APodd, andd) generated by sense amplifier 333a is sa (B) -, sa (D) -, respectively, corresponding to the sampled data sa (B), sa (D); the second odd path rail-to-rail output pair (BPodd, BNodd) generated by sense amplifier 333B is sa (B) +, sa (D) +, respectively, corresponding to the sampled data sa (B), sa (D).

During evaluation period T corresponding to even speculative path 31 _eva In this regard, the even dynamic block 315 generates an even path forward multiplexed output MXOPevn, an even path inverse multiplexed output MXONevn. The forward multiplexed outputs MXOPevn of the even paths corresponding to the sample data sa (C), sa (E) are mx (C), mx (E), and the reverse multiplexed outputs MXONevn of the even paths corresponding to the sample data sa (C), sa (E) are mxb (C), mxb (E).

During evaluation period T corresponding to odd speculative path 33 _eva The odd dynamic module 335 generates an odd path forward multiplexed output MXOPodd, an odd path inverse multiplexed output MXONodd. The forward multiplexed outputs MXOPodd of the odd paths corresponding to the sample data sa (B), sa (D) are mx (B), mx (D), and the inverse multiplexed outputs MXONodd of the odd paths corresponding to the sample data sa (B), sa (D) are mxb (B), mxb (D).

Next, a processing procedure of a part of input data will be described. Please refer to fig. 5B and fig. 12. First, in the even-numbered estimation path 31, the input data in (a) is sampled to generate sampled data sa (a). Since the input data in (a) is the first input data, the odd dynamic module 335 directly selects the track-to-track output pair (APodd, andd) of the first odd path or the track-to-track output pair (BPodd, BNodd) of the second odd path corresponding to the sampling data sa (B) according to the sampling data sa (a).

In the odd numbered speculation path 33, input data in (B) is sampled to produce sampled data sa (B). Next, sense amplifier 333a generates a first odd path rail-to-rail output pair sa (B) -, and sense amplifier 333B generates a second odd path rail-to-rail output pair sa (B) +. After referencing the sampled data sa (a), the odd dynamic module 335 selects one of the pair of rail-to-rail outputs sa (B) in the first odd path and the pair of rail-to-rail outputs sa (B) +in the second odd path as the forward multiplexed output MXOPodd in the odd path and the inverse multiplexed output MXONodd in the odd path (i.e., mx (B), mxb (B)) corresponding to the sampled data sa (B).

If the odd dynamic module 335 selects the track-to-track output pair sa (B) -for the first odd path, the forward multiplexed output mx (B) for the odd path is equal to the positive monorail output APodd for the first odd path and the reverse multiplexed output mxb (B) for the odd path is equal to the negative monorail output arodd for the first odd path. If the odd dynamic module 335 selects the second odd path rail-to-rail output pair sa (B) +, the odd path forward multiplexed output mx (B) is equal to the second odd path positive monorail output BPodd and the odd path reverse multiplexed output mxb (B) is equal to the second odd path negative monorail output BNodd. The inverters 337a and 337B further convert the odd-path forward multiplexed output mx (B) and the odd-path inverse multiplexed output mxb (B) into the odd-path decision D _{out_odd} 。

In the even-numbered speculation path 31, input data in (C) is sampled to produce sampled data sa (C). Next, sense amplifier 313a produces a first even path rail-to-rail output pair sa (C) -, and sense amplifier 313b produces a second even path rail-to-rail output pair sa (C) +. Determining D in reference to odd paths _{out_odd} Thereafter, the even dynamic module 315 selects the rail-to-rail output pair in the first even pathsa (C) -one of the pair of rail-to-rail outputs sa (C) +of the second even path, generates a forward multiplexed output MXOPevn of the even path and an inverse multiplexed output MXONevn of the even path corresponding to the sampled data sa (C). Namely mx (C), mxb (C).

If the even dynamic module 315 selects the track-to-track output pair sa (C) -of the first even path, the forward multiplexed output mx (C) of the even path corresponds to the positive monorail output APevn of the first even path, and the reverse multiplexed output mxb (C) corresponds to the negative monorail output ANevn of the first even path. If the even dynamic module 315 selects the second even path rail-to-rail output pair sa (C) +, the even path forward multiplexed output mx (C) corresponds to the second even path positive monorail output BPevn and the even path reverse multiplexed output mxb (C) corresponds to the second even path negative monorail output BNEvn. The inverters 317a, 317b further convert the even-path forward multiplexed output mx (C) and the even-path inverse multiplexed output mxb (C) to an even-path decision D _{out_evn} 。

The processing of the input data in (D), in (F) is similar to the processing of the input data in (B); also, the processing of the input data in (E) is similar to the processing of the input data in (C). Therefore, the processing of the input data in (D), in (E), in (F) will not be described here.

The delay causes related to the input data in (B) are listed below in fig. 12. Please refer to fig. 5B, fig. 6 and fig. 12. Clock transfer delay T of sense amplifiers 333a, 333b _clk2sa The set time T of the sense amplifiers 333a, 333b between time T1 and time T2 _suSA Between time T2 and time T3, and the transfer delay T of the odd dynamic block 335 _dyn Between time t3 and time t 5. Therefore, the processing and transfer delays of the odd-numbered speculative path 33 are between time T1 and time T4, and the operation margin Δt of the speculative first-order tap (tap 1) _tap1 ' between time t4 and time t 5.

Second embodiment

Fig. 13A and 13B are a block diagram and a circuit design of a dynamic module 7 according to a second embodiment of the present disclosure, respectively. FIG. 14 illustrates dynamic module 7 during precharge period T _pre Is a function of the operation of (a).Fig. 15A, 15B, 16 illustrate the dynamic module 7 during the review period T _eva Is a function of the operation of (a). Fig. 17 lists a combination of different signal states of the dynamic module 7. Fig. 18 further illustrates how the dynamic module 7 is applied to the speculative DFE 3.

Referring to fig. 13A, a block diagram of a dynamic module according to a second embodiment of the present disclosure is shown. The dynamic module 7 includes an upper bone plate circuit 71, a lower bone plate circuit 73, and a memory circuit 75. The memory circuit 75 outputs the terminal N through multiplexing _mxop 、N _mxon And is electrically connected to the upper bone plate circuit 71 and the lower bone plate circuit 73. The upper tile circuit 71 includes a dynamic latch 713 and a multiplexer 711, and the lower tile circuit 73 includes a dynamic latch 733 and a multiplexer 731.

In the above bone plate circuit 71, the dynamic latch 713 includes phase setting circuits 713a and 713b and a decision selection stage circuit 713c, and the multiplexer 711 includes a positive output circuit 711a and a negative output circuit 711b. In the lower tile circuit 73, the dynamic latch 733 includes phase setting circuits 733a and 733b and a decision selecting stage circuit 733c, and the multiplexer 731 includes a positive output circuit 731a and a negative output circuit 731b.

Please refer to fig. 13B, which is a schematic diagram of a circuit design of a dynamic module according to a second embodiment of the present disclosure. Please refer to fig. 13A and fig. 13B.

The elements and connections of the above bone plate circuit 71 are described next. In the dynamic latch 713, the phase setting circuit 713a includes a PMOS transistor upP and an NMOS transistor upN, the phase setting circuit 713b includes a PMOS transistor unP and an NMOS transistor unN, and the decision selecting stage 713c includes a PMOA transistor uinP, an NMOS transistor uinN, and inverters uinv1, uinv2 coupled alternately.

In the phase setting circuit 713a, the gates of the PMOS transistor lpP and the NMOS transistor lpN are electrically connected to each other for receiving the forward latch clock signal CLK_L, and the drains of the PMOS transistor lpP and the NMOS transistor lpN are electrically connected to the selection terminal N _bp . The source of the PMOS transistor upP is electrically connected to the supply voltage Vcc, and the source of the NMOS transistor upN is electrically connected to the decision select stage circuit 713c. In the phase setting circuit 713b, the PMOS transistor unP andthe gates of the NMOS transistor unN are electrically connected to each other for receiving the latch clock signal CLK_L, and the drains of the PMOS transistor unP and the NMOS transistor unN are electrically connected to the selection terminal N _an . The source of the PMOS transistor unP is electrically connected to the decision stage 713c, and the source of the NMOS transistor unN is electrically connected to the ground terminal Gnd.

In the decision selecting stage circuit 713c, the source of the PMOS transistor uinP is electrically connected to the supply voltage terminal Vcc, and the drain of the PMOS transistor uinP is electrically connected to the phase setting circuit 713b. The source of the NMOS transistor uin is electrically connected to the ground terminal Gnd, and the drain of the NMOS transistor uin is electrically connected to the phase setting circuit 713a. The gate of the PMOS transistor uinP receives the forward previous decision bit S _po And the gate of PMOS transistor uinN receives the inverted previous decision bit SB _po . Inverters uinv1 and uinv2 cross-coupled to each other are electrically connected to selection terminal N _ap 、N _an And (3) the room(s). The input terminal of the inverter uinv1 and the output terminal of the inverter uinv2 are electrically connected to the selection terminal N _ap . The output terminal of the inverter uinv1 and the input terminal of the inverter uinv2 are electrically connected to the selection terminal N _an 。

In the multiplexer 711, the positive output circuit 711a includes PMOS transistors upoP1 and upoP2 and NMOS transistors upoN1 and upoN2; the negative output circuit 711b includes PMOS transistors unoP1 and unoP2 and NMOS transistors unoN1 and unoN2. In short, the positive output circuit 711a is associated with a forward multiplexed output MXOP, and the negative output circuit 711b is associated with an inverse multiplexed output MXON.

In the positive output circuit 711a, the gate of the PMOS transistor upoP2 is electrically connected to the selection terminal N _ap And the gate of NMOS transistor upoN2 is electrically connected to the selection terminal N _an . The gates of the PMOS transistor upoP1 and the NMOS transistor upoP1 are electrically connected to each other for receiving the first negative monorail output AN. The source of the PMOS transistor upoP1 is electrically connected to the supply voltage terminal Vcc, and the drain of the PMOS transistor upoP1 is electrically connected to the source of the PMOS transistor upoP 2. The source of the NMOS transistor upoN1 is electrically connected to the ground terminal Gnd, and the drain of the NMOS transistor lnON1 is electrically connected to the source of the NMOS transistor upoN 2. Furthermore, PMOS transistor upoP2Are electrically connected with the drain electrode of the NMOS transistor upoN2 at the forward multiplexing output terminal N _mxop 。

In the negative output circuit 711b, the gate of the PMOS transistor unoP2 is electrically connected to the selection terminal N _ap And the gate of NMOS transistor upoN2 is electrically connected to the selection terminal N _an . The gates of the PMOS transistor unoP1 and the NMOS transistor unoN1 are electrically connected to each other for receiving the first positive monorail output AP. The source of the PMOS transistor unoP1 is electrically connected to the supply voltage terminal Vcc, and the drain of the PMOS transistor unoP1 is electrically connected to the source of the PMOS transistor unoP 2. The source of the NMOS transistor unoN1 is electrically connected to the ground terminal Gnd, and the drain of the NMOS transistor unoN1 is electrically connected to the source of the NMOS transistor unoN 2. In addition, the drains of the PMOS transistor unoP2 and the NMOS transistor unoN2 are electrically connected to the inverse multiplexing output terminal N _mxon 。

The following describes the elements and connection relationships of the underlying bone plate circuit 73. In the dynamic latch 733, the phase setting circuit 733a includes a PMOS transistor lpP and an NMOS transistor lpN; the phase setting circuit 733b includes a PMOS transistor lnP and an NMOS transistor lnN; and the selection stage 733c includes PMOS transistors linP, NMOS transistors linN and inverters linv1, linv2 coupled alternately.

In the phase setting circuit 733b, the gates of the PMOS transistor lpP and the NMOS transistor lpN are electrically connected to each other for receiving the forward latch clock signal CLK_L, and the drains of the PMOS transistor lpP and the NMOS transistor lpN are electrically connected to the selection terminal N _bp . The source of the PMOS transistor lpP is electrically connected to the supply voltage Vcc and the source of the NMOS transistor lpN is electrically connected to the decision stage 733c. In the phase setting circuit 733b, the gates of the PMOS transistor lnP and the NMOS transistor lnN are electrically connected to each other for receiving the latch clock signal CLKB_L, and the drains of the PMOS transistor lnP and the NMOS transistor lnN are electrically connected to the selection terminal N _bn . The source of the PMOS transistor lnP is electrically connected to the decision stage 7333 c and the source of the nmos transistor lpN is electrically connected to the ground terminal Gnd.

In the decision stage 733c, the source of the PMOS transistor linP is electrically connected to the supply voltage Vcc, and the drain of the PMOS transistor linP is electrically connected to the phaseThe bit setting circuit 733b. The source of the NMOS transistor linN is electrically connected to the ground terminal Gnd, and the drain of the NMOS transistor linN is electrically connected to the phase setting circuit 733a. Gate receiving inverse previous decision bit SB of PMOS transistor linP _po And the gate of NMOS transistor linN receives the forward previous determination bit S _po . The inverters linv1, linv2 cross-coupled to each other are electrically connected to the selection terminal N _bp 、N _bn And (3) the room(s). The input terminal of the inverter linv1 and the output terminal of the inverter linv2 are electrically connected to the selection terminal N _bp . The output terminal of the inverter linv1 and the input terminal of the inverter linv2 are electrically connected to the selection terminal N _bn 。

In the multiplexer 731, the positive output circuit 731a includes PMOS transistors lpoP1 and lpoP2 and NMOS transistors lpoN1 and lpoN2; the negative output circuit 731b includes PMOS transistors lnoP1 and lnoP2 and NMOS transistors lnoP1 and lnoP 2. Basically, the positive output circuit 731a is associated with the forward multiplexed output MXOP, and the negative output circuit 711b is associated with the inverse multiplexed output MXON.

In the positive output circuit 731a, the gate of the PMOS transistor lpoP2 is electrically connected to the selection terminal N _bp The gate of the NMOS transistor lpON2 is electrically connected to the selection terminal N _bn . The gates of the PMOS transistor lpoP1 and the NMOS transistor lpoN1 are electrically connected to each other for receiving the second negative monorail output BN. The source of the PMOS transistor lpoP1 is electrically connected to the supply voltage terminal Vcc; the drain of the PMOS transistor lpoP1 is electrically connected to the source of the PMOS transistor lpoP 2. The source of the NMOS transistor lpoN1 is electrically connected to the ground terminal Gnd, and the drain of the NMOS transistor lpoN1 is electrically connected to the source of the NMOS transistor lpoN 2. In addition, the drains of the PMOS transistor lpoP2 and the NMOS transistor lpoP N2 are electrically connected to the forward multiplexing output node N _mxop 。

In the negative output circuit 731b, the gate of the PMOS transistor lnoP2 is electrically connected to the selection terminal N _bp And the gate of NMOS transistor lnan 2 is electrically connected to the selection terminal N _bn . The gates of the PMOS transistor lnoP1 and the NMOS transistor lnoP1 are electrically connected to each other for receiving the second positive monorail output BP. The source of the PMOS transistor lpoP1 is electrically connected to the supply voltage terminal Vcc, and the PMOS transistorThe drain of the body transistor lnoP1 is electrically connected to the source of the PMOS transistor lnoP 2. The source of NMOS transistor lnoN1 is electrically connected to ground terminal Gnd, and the drain of NMOS transistor lnoN1 is electrically connected to the source of NMOS transistor lnoN 2. In addition, the drains of the PMOS transistor lnoP2 and the NMOS transistor lnoN2 are electrically connected to the inverse multiplexing output terminal N _mxon 。

The memory circuit 75 comprises cross-coupled inverters sinv1, sinv2. The input and output terminals of the inverter sin v1 are electrically connected to the forward multiplexing output terminal N _mxop And an inverse multiplexing output terminal N _mxon . The input and output terminals of the inverter sin v2 are electrically connected to the inverse multiplexing output terminal N _mxon And forward multiplexing output terminal N _mxop 。

Please refer to fig. 14, which is a dynamic module according to a second embodiment of the present disclosure, during the precharge period T _pre Schematic representation of the operation. The operation of the upper bone plate circuit 71 and the lower bone plate circuit 73 will be described below.

Next, operations of the phase setting circuits 713a and 713b, the decision selecting stage circuit 713c, and the multiplexer 711 in the above bone plate circuit 711 are sequentially described. Since the forward latch clock signal clk_l is at a low logic level (clk_l=0), the PMOS transistor upP in the phase setting circuit 713a is turned on and the NMOS transistor upN is turned off. Since the inverted latch clock signal clkb_l is at a high logic level (clkb_l=1), the PMOS transistor unP is turned off and the NMOS transistor unN is turned on. Thus, in the upper bone plate circuit 71, the selection signal sa_p is equal to the supply voltage Vcc (sa_p=1), and the selection signal sa_n is equal to the ground voltage Gnd (sa_n=0).

Since the selection signal sa_p is equal to the supply voltage Vcc (sa_p=1), the PMOS transistor upoP2 in the positive output circuit 711a is turned off, and the PMOS transistor unoP2 in the negative output circuit 731b is turned off. Since the selection signal sa_n is equal to the ground voltage Gnd (sa_n=0), the NMOS transistor upoN2 in the positive output circuit 711a is turned off, and the NMOS transistor unoN2 in the negative output circuit 731b is turned off. In connection with, multiplexer 711, is connected to multiplexing output node N _mxon 、N _mxop Related PMOS transistors unoP2, upoP2 and NMOS transistor unoN2,The upoN2 is all turned off and the upper bone plate circuit 7 is in the precharge period T _pre The forward multiplexing output MXOP and the reverse multiplexing output MXON are not affected.

In short, when the dynamic module 7 is in the precharge period T _pre The upper bone plate circuit 71 does not update the forward multiplexed output MXOP and the inverse multiplexed output MXON. In fig. 14, the multiplexer 711 is shown with a dot-shaped bottom, for illustrating the multiplexer 711 during the precharge period T _pre The forward multiplexing output MXOP and the reverse multiplexing output MXON are not affected.

The phase setting circuits 733a, 733b, the decision selecting stage circuit 733c and the multiplexer 731 in the lower bone plate circuit 73 operate in a similar manner to their corresponding elements in the upper bone plate circuit 71. The selection signal sb_p is equal to the supply voltage Vcc (sb_p=1) because the PMOS transistor loP is turned on by the forward latch clock signal clk_l (clk_l=0). Because the inverted latch clock signal clkb_l (clkb_l=1) turns on the NMOS transistor lnN, the selection signal sb_n is equal to the ground voltage Gnd (sb_n=0). In conjunction with, in multiplexer 731, multiplexed output node N _mxon 、N _mxop The associated PMOS transistors lnoP2, lpoP2 are all turned off from the NMOS transistors lnoP2, lpoN2, and the underlying bone plate circuit 73 is turned off during the precharge period T _pre The forward multiplexing output MXOP and the reverse multiplexing output MXON are not affected. Fig. 14 shows the multiplexer 731 with a dot-shaped bottom, which means that the multiplexer 731 does not affect the forward multiplexing output MXOP and the inverse multiplexing output MXON.

The dynamic latches 713, 813 and multiplexers 811, 831 are described as during evaluation T _eva Is a function of the operation of (a). Fig. 15A, 15B illustrate the operation of the dynamic block 7 when the forward latch clock signal clk_l is at a high logic level (clkl=1) and the reverse latch clock signal clkb_l is at a low logic level (clkb_l=0).

FIG. 15A is a block diagram of bits S in forward previous decisions _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the dynamic module according to the second embodiment of the disclosed concept is in the evaluation period T _eva Schematic representation of the operation. On the other hand, FIG. 15B shows a bit S determined in the forward direction _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the dynamic module according to the second embodiment of the disclosed concept is during the evaluation period T _eva Schematic representation of the operation.

Referring to fig. 16, an upper bone plate circuit according to a second embodiment of the present disclosure operates during a review period T _eva Is a flow chart of (a). The operation of the upper bone plate circuit 71 shown in fig. 15A and 15B is described below. First, the dynamic latch 713 generates the selection signal sa_p (step S71) and the selection signal sa_n (step S73) at the same time.

Since the latch clock signal clk_l (clk_l=1) turns on the NMOS transistor upN, the NMOS transistor uinN in the decision selecting stage 713c is turned on to the selection signal sa_p (step S71 a), and the selection signal sa_p is determined by the on state of the NMOS transistor uinN. The NMOS transistor uinN is further formed by inverting the previous decision bit SB _po Control (step S71 b). As shown in FIG. 15A, when the previous decision bit SB is reversed _po Is at a high logic level (SB _po =1), the select signal sa_p is equal to the ground voltage Gnd (sa_p=0). As shown in FIG. 15B, when the previous decision bit SB is reversed _po Is of low logic level (SB _po =0), the selection signal sb_n is floating (sb_n=z).

Since the inverted latch clock signal clkb_l (clkb_l=1) turns on the PMOS transistor unP, the PMOS transistor uinP in the selection stage circuit 713c is determined to be turned on to the selection signal sa_n (step S73 a), and the selection signal sa_n is determined by the on state of the PMOS transistor uinP. The PMOS transistor uinP further determines the bit S from the forward previous _po Control (step S73 b). As shown in FIG. 15A, when the cell S is determined forward _po At a low logic level (S _po =0), the select signal sa_n is equal to the supply voltage Vcc (sa_n=1). As shown in FIG. 15B, when the cell S is determined forward _po At a high logic level (spo=1), the select signal sa_n is floating (sa_n=z).

Therefore, the selection signal sa_p determines the bit SB in response to the previous inversion _po Change and select signal sa_n determines bit S in forward direction _po And (3) changing. Responsive to forward previous determination of bits S _po Reverse previous decision bit SB _po Two different situations have to be considered.

When the select signals sa_p, sa_n are floating (sa_p= Z, sa _n=z), the multiplexer 711 is disabled and the above bone plate circuit 71 does not affect the forward multiplexed output MXOP, the inverse multiplexed output MXON (step S77). FIG. 15B shows the components of the upper bone plate circuit 71 with a dot-shaped bottom, representing the period T during the evaluation _eva If the previous decision bit S is forward _po Is at a high logic level (spo=1) and when the inverse previous decision bit is at a low logic level (SB _po When=0), the upper bone plate circuit 73 does not affect the forward multiplexed output MXOP and the inverse multiplexed output MXON.

When the selection signal sa_p is the ground voltage Gnd (sa_p=0) and the selection signal sa_n is the supply voltage (sa_n=1), the multiplexer 711 generates the forward multiplexing output MXOP, the reverse multiplexing output MXON (mxop=ap and mxon=an) based on the first positive monorail output AP and the first negative monorail output AN (step S75).

As shown in fig. 15A, the selection signal sa_n (sa_n=0) of the low logic level turns on the PMOS transistor upoP2 in the positive output circuit 711a and the PMOS transistor unoP2 in the negative output circuit 711 b; the selection signal sa_n (sa_n=1) of the high logic level turns on the NMOS transistor upoN1 of the positive output circuit 711a and the NMOS transistor unoN2 of the negative output circuit 711 b.

Then, the forward multiplexing output MXOP is determined by the on states of the PMOS transistor upoP1 and the NMOS transistor unoN1 in the positive output circuit 711 a. Wherein, the PMOS transistor upoP1 and the NMOS transistor unoN1 are controlled by the first negative monorail output AN (step S75 a). On the other hand, the inverse multiplexing output MXON is determined by the on states of the PMOS transistor unoP1 and the NMOS transistor unoN1 in the negative output circuit 711 b. Wherein, the PMOS transistor unoP1 and the NMOS transistor unoN1 are controlled by the first positive monorail output AP (step S75 b).

Step S75 considers two cases of the first rail-to-rail output pair: (ap=0 and an=1) and (ap=1 and an=0).

First, the case where ap=0 and an=1 is explained. Since the first negative single-rail output AN is at a high logic level (an=1), in the positive output circuit 711a, the PMOS transistor upoP1 is turned off, and the NMOS transistor upoN1 is turned on. In conjunction, the forward multiplexed output MXOP is equal to ground voltage Gnd (mxop=0). Meanwhile, in the negative output circuit 711b, the PMOS transistor unoP1 is turned on and the NMOS transistor unoN1 is turned off because the first positive single-rail output AP is at a low logic level (ap=0). In conjunction, the inverse multiplexing output MXON is equal to the supply voltage Vcc (mxon=1). Therefore, when the first rail-to-rail output pair (AP, AN) satisfies that the first positive monorail output AP is at a low logic level (ap=0) and the first negative monorail output AN is at a high logic level (an=1), the relationship between the forward multiplexing output MXOP and the first positive monorail output AP is mxop=ap=0 and the relationship between the reverse multiplexing output MXON and the first negative monorail output AN is mxon=an=1.

Next, the case of ap=1 and an=0 is described. Because the first negative monorail output AN is at a low logic level (an=0), in the positive output circuit 711a, the PMOS transistor upoP1 is on and the NMOS transistor upoN1 is off. Accordingly, the forward multiplexing output MXOP is equal to the supply voltage Vcc (mxop=1). At this time, since the first positive single-rail output AP is at a high logic level (ap=1), in the negative output circuit 711b, the PMOS transistor unoP1 is turned off and the NMOS transistor unoN1 is turned on. In conjunction, the inverse multiplexing output MXON is equal to the ground voltage Gnd (mxon=0). Therefore, when the first rail-to-rail output pair (AP, AN) meets the condition that the first positive monorail AP output is at a high logic level (ap=1) and the first negative monorail output AN is at a low logic level (an=0), the relationship between the forward multiplexing output MXOP and the first positive monorail output AP is mxop=ap=1 and the relationship between the reverse multiplexing output MXON and the first negative monorail output AN is mxon=an=0.

When the dynamic module 7 is in the evaluation period T _eva In this case, the phase setting circuits 713a and 713b, the decision selecting stage circuit 713c and the multiplexer 711 in the upper bone plate circuit 71 are sequentially operated. The phase setting circuits 713a and 713b determine whether the selection stage circuit 713c is related to the selection signals sa_p and sa_n in the upper bone plate circuit 81. If not (as shown in fig. 15B), the selection signal sa/u in the upper bone plate circuit 71 p, sa_n are floating (sa_p= Z, sa _n=z). If so (as shown in fig. 15A), the selection signals sa_p and sa_n in the upper tile circuit 71 enable the positive output circuit 711a and the negative output circuit 711b, and the first rail-to-rail output pair AP and AN are used to update the forward multiplexed output MXOP and the inverse multiplexed output MXONN. I.e. mxop=ap, mxon=an.

In fig. 15A and 15B, the lower bone plate circuit 73 operates similarly to the upper bone plate circuit 71, and thus details thereof will not be described in detail. When the dynamic module 7 is running in the evaluation period T _eva In this case, the phase setting circuits 733a and 733b determine whether or not the selection stage circuit 733c is related to the selection signals sb_p and sb_n in the lower bone plate circuit 73. If not (as shown in fig. 15A), the selection signals sb_p and sb_n in the lower bone plate circuit 73 are floating (sb_p= Z, sb _n=z). If so (as shown in fig. 15B), the selection signals sb_p and sb_n in the lower tile circuit 73 enable the positive output circuit 731a and the negative output circuit 731B, and update the forward multiplexed output MXOP and the inverse multiplexed output MXON by using the second rail-to-rail output pair (BP, BN). Namely mxop=bp and mxon=bn.

Details of how the dynamic module 7 operates in response to different input signals are described above. For comparison, fig. 17 shows a combination of different input signals, and the corresponding forward multiplexed output MXOP and inverse multiplexed output MXON.

Please refer to fig. 17, which illustrates a dynamic module during a precharge period T according to a second embodiment of the present disclosure _pre And evaluation period T _eva A summary table of signal states of (a). Dynamic module 7 during precharge period T _pre The operation of (a) can be summarized from the descriptions of fig. 14, 15A, 15B, and 16.

During the precharge period T _pre The latch clock signal clk_l is at a low logic level (clkl=0), and the inverted latch clock signal clkb_l is at a high logic level (clkb_l=1). Accordingly, the select signal sa_p is at a high logic level (sa_p=1); the select signal sa_n is at a low logic level (sa_n=0); the select signal sb_p is a high logic level (sb_p=1); and, the selection signal sb_n is a low logic level (sb_n=0). Forward block based on the select signals sa_p, sa_n, sb_p, sb_nLocating element S _po Reverse previous decision bit SB _po The first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN) do not affect the forward multiplexed output MXOP, the reverse multiplexed output MXON, and the memory circuit 75 holds the forward multiplexed output MXOP, the reverse multiplexed output MXON.

During the evaluation period T _eva The selection signals sa_p, sa_n, sb_p, sb_n determine the bit S in the forward direction _po Reverse previous decision bit SB _po But vary. If forward previous decision bit S _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the selection signals sa_p, sa_n and the forward previous determination bits S in the upper bone plate circuit 71 _po Reverse previous decision bit SB _po In the relation of sa_p=0=s _po 、sa_n＝1＝SB _po . The selection signals sb_p and sb_n in the lower tile circuit 73 are floating (sb_p= Z, sb _n=z). Next, the forward multiplexed output MXOP and the reverse multiplexed output MXON are updated with the first track-to-track output pair (AP, AN) (mxop=ap, mxon=an). On the other hand, if the previous decision bit S is forward _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the selection signals sb_p, sb_n and the forward previous decision bits S in the lower bone plate circuit 73 _po Reverse previous decision bit SB _po In the relation of sb_p=0=s _po 、sb_n＝1＝SB _po . The selection signals sa_p and sa_n in the upper bone plate circuit 71 are floating (sa_p=z, sa_n=z). Then, the forward multiplexed output MXOP and the reverse multiplexed output MXON are updated with the second rail-to-rail output pair (BP, BN) (mxop=bp, mxon=bn).

As described above, the speculative DFE 3 operates in a recursive manner, and the even speculative path 31 and the odd speculative path 33 interact. To illustrate how dynamic module 7 is applied to speculative DFE 3, the signal relationships when speculative DFE 3 employs dynamic module 7 are then illustrated in a waveform diagram.

Please refer to fig. 18, which is a waveform diagram illustrating an example of a data stream processed by the speculative DFE according to the second embodiment of the present disclosure. The waveforms of fig. 12 and 18 are similar except for the selection signals sa_p, sa_n, sb_p, sb_n. Therefore, waveforms of the system clock signal clk_sys, the input data in (a) to in (F), the even-path forward latch clock signal clk_l (even), the odd-path forward latch clock signal clk_l (odd), the rail-to-rail output pair (APevn, ANevn), (BPevn, BNevn), (APodd, and), (BPodd, BPevn), and the forward/inverse multiplexing output (MXOPevn, MXONevn, MXOPodd, MXONodd) of the even/odd paths are not repeatedly described here.

In the even-numbered speculative path 31, the selection signals sa_p, sa_n are used to decide whether the pair of rail-to-rail outputs (APevn, ANevn) of the first even-numbered path should be selected as the forward multiplexed output mxopev of the even-numbered path, the inverse multiplexed output MXONevn of the even-numbered path; the selection signals sb_p, sb_n are used to decide whether the rail-to-rail output pair (BPevn, BNevn) of the second even path should be selected as the forward multiplexed output MXOPevn of the even path, the inverse multiplexed output MXONevn of the even path. Because of the transfer delay of the phase setting circuit, in the even-numbered estimation path 31, the period in which the selection signals sb_p, sb_n are generated is later than the period in which the rail-to-rail output pair (APevn, ANevn) of the first even-numbered path and the rail-to-rail output pair (BPevn, BNevn) of the second even-numbered path are generated, and the period in which the forward multiplexed output MXOPevn of the even-numbered path and the inverse multiplexed output MXONevn of the even-numbered path are generated is later than the period in which the selection signals sb_p, sb_n are generated in the even-numbered estimation path 31. The even-numbered speculation paths 31 are labeled ap (A), an (A), bp (A), bn (A), respectively, for select signals sa_p, sa_n, sb_p, sb_n generated with the sample data sa (A). The even-numbered speculation paths 31 are labeled in a similar manner to the select signals sa_p, sa_n, sb_p, sb_n generated by the sampled data sa (C), sa (E) and will not be repeated.

The selection signals sa_p and sa_n in the odd number speculation path 33 are used for determining whether to select the track-to-track output pair (APodd, andd) of the first odd number path as the forward multiplexing output MXOPodd of the odd number path and the inverse multiplexing output MXONodd of the odd number path; the selection signals sb_p and sb_n are used for determining whether to select the rail-to-rail output pair (BPodd, bnodd) of the second odd path as the forward multiplexing output MXOPOdd of the odd path and the inverse multiplexing output MXONOODd of the odd path. Because of the transfer delay of the phase setting circuit, in the odd-numbered estimation path 33, the generation period of the selection signals sb_p, sb_n is later than the generation period of the first odd-numbered path rail-to-rail output pair (APodd, andd), the second even-numbered path rail-to-rail output pair (bpod, bnod), and the generation period of the odd-numbered path forward multiplexed output MXOPodd, the odd-numbered path inverse multiplexed output MXONodd is later than the generation period of the selection signals sb_p, sb_n in the odd-numbered estimation path 33. The odd numbered speculation paths 33 are labeled ap (B), an (B), bp (B), bn (B), respectively, for select signals sa_p, sa_n, sb_p, sb_n generated with the sample data sa (B). The odd numbered speculation path 33 is labeled in a similar manner to the select signals sa_p, sa_n, sb_p, sb_n generated by the sampled data sa (D) and will not be repeated.

The lower part of fig. 18 shows the delay cause of the speculative first-order tap (tap 1) that generates the input data in (B). Please refer to fig. 5B, fig. 6 and fig. 18. Clock transfer delay T of sense amplifiers 333a, 333b _clk2sa Between time T1 and time T2, the setting time T of the sense amplifiers 333a, 333b _suSA Between time T2 and time T3, and the transfer delay T of the odd dynamic block 335 _dyn Between time t3 and time t 5. Therefore, the processing and transfer delays of the odd-numbered speculative path 33 are between time t1 and time t4, and the operation margin of the speculative first-order tap (tap 1) is between time t4 and time t 5.

Please refer to fig. 12 and fig. 18 simultaneously. In fig. 12, the forward multiplexing output MXOP and the reverse multiplexing output MXON of the first embodiment are directly determined by the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN). On the other hand, in fig. 18, the multiplexed output forward multiplexed output MXOP and the inverse multiplexed output MXON of the second embodiment are indirectly determined by the selection signals sa_p, sa_n, sb_p, sb_n determined by the first rail-to-rail output pair (AP, AN) and the second rail-to-rail output pair (BP, BN). Thus, the transfer delay T of the dynamic module 6 _dyn Transfer delay T of more dynamic module 7 _dyn Short.

In other words, the forward multiplexing output MXOP and the inverse multiplexing output MXON of the first embodiment and the second embodiment are generated in a single stage manner and a two-stage manner, respectively. That is, unlike the first embodiment that generates the forward multiplexed output MXOP and the reverse multiplexed output MXON directly based on the monorail outputs (AP, AN), (BP, BN), the second embodiment generates the forward multiplexed output MXOP and the reverse multiplexed output MXON using the selection signals (sa_p, sa_n, sb_p, sb_n) after generating the selection signals (sa_p, sa_n, sb_p, sb_n).

Third embodiment

Fig. 19A and 19B are a block diagram and a circuit design of a dynamic module 8 according to a third embodiment of the present disclosure, respectively. FIG. 20 illustrates dynamic module 8 during precharge period T _pre Is a function of the operation of (a). FIGS. 21A, 21B, and 22 illustrate the dynamic module 8 during the review period T _eva Is a function of the operation of (a). Fig. 23 lists a combination of different signal states of the dynamic module 8.

Referring to fig. 19A, a block diagram of a dynamic module according to a third embodiment of the present disclosure is shown. The dynamic module 8 includes an upper bone plate circuit 81, a lower bone plate circuit 83, and a memory circuit 85. The upper card circuit 81 further includes a dynamic latch 813 and a multiplexer 811, and the lower card circuit 63 further includes a dynamic latch 833 and a multiplexer 831.

Please refer to fig. 13A and fig. 19A. The dynamic module of fig. 13A has similar element and wiring relationships to the dynamic module of fig. 19A. The difference between the dynamic module 7 and the dynamic module 8 is the position and arrangement of the multiplexers 711, 811, 731, 831. In the dynamic module 7, the multiplexers 711 and the elements in the multiplexer 731 are arranged in the longitudinal direction. On the other hand, in the dynamic module 8, the multiplexer 811 and the elements in the multiplexer 831 are arranged in the lateral direction.

Please refer to fig. 19B, which is a schematic diagram of a circuit design of a dynamic module according to a third embodiment of the present disclosure. Since the dynamic latches 813 and 833 of the third embodiment are similar to those of the second embodiment, the elements and connections within the dynamic latches 813 and 833 will not be described again, and only the elements and connections of the multiplexers 811 and 831 will be described. Basically, the positive output circuits 811a, 831a and the negative output circuits 811b, 831b are implemented using transmission gates.

In the multiplexer 811, the positive output circuit 811a includes a PMOS transistor upoP and an NMOS transistor upoN, and the negative output circuit 811b includes a PMOS transistor unoP and an NMOS transistor unoN. The gates of the PMOS transistors upoP and unoN are electrically connected to the selection terminal N _ap . The gates of the NMOS transistors upoN and unoN are electrically connected to the selection terminal N _an . Next, the signal relationship between the elements of the multiplexer 811 will be described.

In the positive output circuit 811, the source of the PMOS transistor upoP and the drain of the NMOS transistor upoN are commonly connected to the positive multiplexing output node N _mxop . In the negative output circuit 811b, the source of the PMOS transistor unoP and the drain of the NMOS transistor unoN are commonly connected to the first negative monorail output AN, and the drain of the PMOS transistor unoP and the source of the NMOS transistor unoN are electrically connected to the inverse multiplexing output terminal N _mxon 。

In the multiplexer 831, the positive output circuit 831a includes a PMOS transistor lpoP and an NMOS transistor lpoN, and the negative output circuit 831b includes a PMOS transistor lnoP and an NMOS transistor lnoN. The gates of the PMOS transistors lpoP and lnoP are electrically connected to the selection terminal N _bp . The gates of the NMOS transistors lpoN and lnoN are electrically connected to the selection terminal N _bn . Next, the signal relationship of the multiplexer 811 is explained.

In the positive output circuit 831a, the source of the PMOS transistor lpoP and the drain of the NMOS transistor lpoN are commonly connected to the positive multiplex output node N _mxop . In the negative output circuit 831b, the source of the PMOS transistor lnoP and the drain of the NMOS transistor lnoN are commonly connected to the second negative monorail output BN, and the drain of the PMOS transistor lnoP and the source of the NMOS transistor lnoN are electrically connected to the inverse multiplexing output terminal N _mxon 。

The memory circuit 85 comprises cross-coupled inverters sinv1, sinv2. The input and output terminals of the inverter sin v1 are electrically connected to the forward multiplexing output terminal N _mxop And reverse directionMultiplex output terminal N _mxon . The input and output terminals of the inverter sin v2 are electrically connected to the inverse multiplexing output terminal N _mxon And forward multiplexing output terminal N _mxop 。

Please refer to fig. 20, which is a dynamic module according to a third embodiment of the present disclosure, during precharge period T _pre Schematic of how to operate. Since the phase setting circuits 813a, 813b and the decision selecting stage 813c of the third embodiment are similar to those of the second embodiment, the manner of generating the selection signals sa_p=1, sa_n=0, sb_p=1 and sb_n=0 is also similar to that of fig. 14, and will not be described here.

Next, the operation of the multiplexer 811 is described. Since the selection signal sa_p is equal to the supply voltage Vcc (sa_p=1), the PMOS transistor upoP in the positive output circuit 811a is turned off, and the PMOS transistor unoP in the negative output circuit 811b is turned off. Since the selection signal sa_n is equal to the ground voltage Gnd (sa_n=0), the NMOS transistor upoN in the positive output circuit 811a is turned off, and the NMOS transistor unoN in the negative output circuit 811b is turned off. During the precharge period T _pre The upper bone plate circuit 81 does not affect the forward multiplexed output MXOP and the inverse multiplexed output MXON because the multiplexer 811 is disabled due to the PMOS transistors upoP and unoP and the NMOS transistors upoN and unoN in the multiplexer 811 being all turned off.

Similarly, since the select signal sb_p is equal to the supply voltage Vcc (sb_p=1) and the select signal sb_n is equal to the ground voltage Gnd (sb_n=0), the PMOS transistors lpoP, lnoP and the NMOS transistors lpoN, lnoN in the multiplexer 831 are all turned off. Thus, according to the third embodiment of the present disclosure, during precharge period T _pre The multiplexer 831 is disabled so that the lower tile circuit 83 does not affect the forward multiplexed output MXOP, the reverse multiplexed output MXON.

During the precharge period T _pre The memory circuit 65 holds the forward multiplexed output MXOP and the inverse multiplexed output MXON for, for example, the evaluation period T _eva The stored state. In fig. 20, multiplexers 811 and 831 are shown with dot-shaped bottoms, and the multiplexers 811 and 831 are represented during the precharge period T _pre Is disabled.

Fig. 21A and 21B illustrateDynamic module 8 during the evaluation period T _eva In operation, the signals and element states of the dynamic module 8. Please refer to fig. 21A, which illustrates determining the bit S in the forward direction _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the dynamic module according to the third embodiment of the present disclosure is in the evaluation period T _eva Schematic representation of the operation. Please refer to fig. 21B, which illustrates determining the bit S in the forward direction _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the dynamic module according to the third embodiment of the present disclosure is in the evaluation period T _eva Schematic representation of the operation.

Referring to fig. 22, an upper bone plate circuit according to a third embodiment of the present disclosure operates during the review period T _eva Is a flow chart of (a). Please refer to fig. 21A, 21B, and 22.

As described above, the elements of the dynamic latch 813 are similar to the dynamic latch 713 of the second embodiment in connection therewith. Accordingly, steps S81a, S81b, S83a, S83b of fig. 22 are similar to steps S71a, S71b, S73a, S73b of fig. 16 and are not repeated here. Only steps S85 and S87 will be described here.

When the select signals sa_p, sa_n are floating (sa_p= Z, sa _n=z), the multiplexer 811 is disabled and the above bone plate circuit 71 does not affect the forward multiplexed output MXOP, the inverse multiplexed output MXON (step S87). In FIG. 21B, the upper bone plate circuit 83 is shown with a dot-like bottom to indicate when the bit S was previously determined in the forward direction _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po When=0), the upper bone plate circuit 83 does not affect the forward multiplexed output MXOP and the inverse multiplexed output MXON.

When the selection signal sa_p is the ground voltage Gnd (sa_p=0) and the selection signal sa_n is the supply voltage Vcc (sa_n=1), the multiplexer 811 generates the forward multiplexing output MXOP and the inverse multiplexing output MXON according to the first positive monorail output AP and the first negative monorail output AN. That is, mxop=ap and mxon=an (step S85).

As shown in fig. 21A, the selection signal sa_n (sa_n=0) of the low logic level turns on the PMOS transistor upoP in the positive output circuit 811A and the PMOS transistor unoP in the negative output circuit 811 b; and, the selection signal sa_n (sa_n=1) of the high logic level turns on the NMOS transistor upoN in the positive output circuit 811a and the NMOS transistor unoN in the negative output circuit 811 b.

Next, the positive output circuit 811a turns on the first positive monorail output AP to the forward multiplexing output node N _mxop The MXOP is outputted as a forward multiplex (step S85 a). On the other hand, the negative output circuit 811b turns on the first negative monorail output AP to the inverse multiplexing output terminal N _mxon The output MXON is used as the inverse multiplex output (step S85 b).

According to fig. 22, when the dynamic module 8 is operating during the review period T _eva In this case, the phase setting circuits 813a and 813b, the decision selecting circuit 813c, and the multiplexer 811 in the upper bone plate circuit 81 operate sequentially. The phase setting circuits 813a and 813b determine whether the selection stage circuit 813c is related to the selection signals sa_p and sa_n in the upper bone plate circuit 81. If not (see fig. 21B), the selection signals sa_p, sa_n are floating (sa_p= Z, sa _n=z), and the multiplexer 811 is disabled. If so (see fig. 21A), the selection signals sa_p and sa_n enable the positive output circuit 811A and the negative output circuit 811b, and the first rail-to-rail output pair AP and AN are used to update the forward multiplexed output MXOP and the inverse multiplexed output MXON. That is, mxop=ap and mxon=an.

In fig. 21A and 21B, the operation of the upper card circuit 81 above the lower card circuit 83 is symmetrical, and thus the details thereof will not be described in detail. When the dynamic module 8 is in the evaluation period T _eva In operation, the phase setting circuits 833a, 833b, the decision selection stage 833c and the multiplexer 711 in the lower tile circuit 83 are sequentially operated. The phase setting circuits 833a and 833b determine whether the selection stage 833c is related to the selection signals sb_p and sb_n in the lower bone plate circuit 83. If not (as shown in fig. 21A), the selection signals sb_p, sb_n are floating (sb_p= Z, sb _n=z), and the multiplexer 831 is disabled. If so (as shown in fig. 21B), the selection signals sb_p, sb_n enable the positive output circuit 831a and the negative output The circuit 831b updates the multiplexed output forward multiplexed output MXOP and the inverse multiplexed output MXON using the second rail-to-rail output pair (BP, BN). Namely mxop=bp and mxon=bn.

Please refer to fig. 23, which illustrates the precharge period T _pre And evaluation period T _eva Summary table of signal states of dynamic modules according to a third embodiment contemplated by the present disclosure. Dynamic module 8 during precharge period T _pre The operation of (2) can be deduced from figure 20. Dynamic module 8 during the evaluation period T _eva The operation of (a) can be deduced from fig. 21A, 21B, and 22.

During the precharge period T _pre Because the forward latch clock signal clk_l is at a low logic level (clk_l=0) and the reverse latch clock signal clkb_l is at a high logic level (clkb_l=1), the select signal sa_p is equal to the supply voltage Vcc (sa_p=1); the select signal sa_n is equal to the ground voltage Gnd (sa_n=0); the selection signal sb_p is equal to the supply voltage Vcc (sb_p=1); and, the selection signal sb_n is equal to the ground voltage Gnd (sb_n=0). According to the selection signals sa_p, sa_n, sb_p, sb_n, the multiplexers 811, 831 are disabled and the forward multiplexed output MXOP, the inverse multiplexed output MXON is not subject to the forward preceding determination bit S _po Reverse previous decision bit SB _po Influence. In conjunction, the memory circuit 85 maintains a forward multiplexed output MXOP and an inverse multiplexed output MXON.

During the evaluation period T _eva The selection signals sa_p, sa_n, sb_p, sb_n determine the bit S in the forward direction _po Reverse previous decision bit SB _po And changes. During the evaluation period T _eva If the previous decision bit S is forward _po At a low logic level (S _po =0), and inverts the previous decision bit SB _po Is at a high logic level (SB _po When=1), the selection signals sa_p, sa_n and the forward previous determination bits S in the upper bone plate circuit 81 _po Reverse previous decision bit SB _po In the relation of sa_p=0=s _po 、sa_n＝1＝SB _po . The selection signals sb_p and sb_n in the lower tile circuit 83 are floating (sb_p=z, sb_n=z). Then, the forward multiplexing output MXOP and the reverse multiplexing output MXOP are updated by the first rail-to-rail output pair (AP, AN)And multiplexing the output MXON. On the other hand, during the review period T _eva If the previous decision bit S is forward _po At a high logic level (S _po =1), and inverts the previous decision bit SB _po Is of low logic level (SB _po =0), the selection signals sb_p, sb_n and the forward previous decision bits S in the lower bone plate circuit _po Reverse previous decision bit SB _po The relationship is that sb_p=0=s _po 、sb_n＝1＝SB _po . The selection signals sa_p and sa_n in the upper bone plate circuit 81 are floating (sa_p= Z, sa _n=z). Then, the forward multiplexed output MXOP and the reverse multiplexed output MXON are updated with the second rail-to-rail output pair (BP, BN).

The above embodiment of the speculative DFE can relieve the time requirement of the speculative first-order tap (tap 1), and further save more time margin by combining the latch in the dynamic module with the dynamic module. The present disclosure may also be implemented at a quarter rate.

Please refer to fig. 24, which is a schematic diagram of a speculative DFE with a quarter-rate structure. The speculative DFE 90 includes four equal-split paths, i.e., speculative paths 91, 92, 93, 94. The estimation paths 91, 92, 93, 94 receive the input data D _in And the estimated paths 91, 92, 93, 94 generate path decisions D, respectively _{out_p1} 、D _{out_p2} 、D _{out_p3} 、D _{out_p4} . Path determination D _{out_p1} 、D _{out_p2} 、D _{out_p3} 、D _{out_p4} Together form DFE output D _out . Since the operation of speculative DFE 90 may be derived based on the aforementioned half-rate speculative architecture embodiments, speculative DFE 90 will not be described in detail herein.

In summary, although the present invention has been described in terms of the above embodiments, it is not limited thereto. Those skilled in the art will appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the present invention. Accordingly, the scope of the invention is defined by the appended claims.

Claims

1. A dynamic module, comprising:

A first domino circuit which generates a first multiplexed output, comprising:

a first multiplexer receiving two of a first monorail output, a second monorail output, a third monorail output, and a fourth monorail output;

at least one first phase setting circuit for receiving a first clock signal; and

a first decision selector circuit electrically connected to the first multiplexer and the at least one first phase setting circuit for receiving a first previous decision bit and a second previous decision bit, wherein the first previous decision bit and the second previous decision bit are complementary to each other; and

a second domino circuit electrically connected to the first domino circuit, which generates a second multiplexed output, the second domino circuit comprising:

a second multiplexer receiving the other two of the first monorail output, the second monorail output, the third monorail output, and the fourth monorail output;

at least one second phase setting circuit for receiving a second clock signal, wherein the first clock signal and the second clock signal are complementary; and

a second decision selector circuit electrically connected to the second multiplexer and the at least one second phase setting circuit for receiving the first and second previous decision bits, wherein,

During an evaluation period, the first multiplexed output and the second multiplexed output are selectively updated with the first single-track output, the second single-track output, the third single-track output and the fourth single-track output, and

the first multiplexed output and the second multiplexed output remain unchanged during a precharge period.

2. The dynamic module of claim 1, wherein,

during the evaluation, the dynamic module receives the first and second previous decision bits from another dynamic module, and

during the precharge, the dynamic module provides a third previous determination bit and a fourth previous determination bit to the other dynamic module, wherein,

the third previous decision bit is generated based on the first multiplexed output and the fourth previous decision bit is generated based on the second multiplexed output.

3. The dynamic module of claim 1, wherein,

the first and second monorail outputs are provided by a first sense amplifier, and the third and fourth monorail outputs are provided by a second sense amplifier, wherein,

during the evaluation, the first single track output and the second single track output form a first rail-to-rail output pair, and the third single track output and the fourth single track output form a second rail-to-rail output pair, and

During the precharge, the first monorail output is equal to the second monorail output and the third monorail output is equal to the fourth monorail output.

4. The dynamic module of claim 3, wherein,

the first multiplexer receiving the first monorail output from the first sense amplifier and the third monorail output from the second sense amplifier; and is also provided with

The second multiplexer receives the second monorail output from the first sense amplifier and the fourth monorail output from the second sense amplifier.

5. The dynamic module of claim 3, wherein,

the first multiplexer receives the first single-rail output and the second single-rail output from the first sense amplifier, and

the second multiplexer receives the third monorail output and the fourth monorail output from the second sense amplifier.

6. The dynamic module of claim 1, further comprising:

a memory circuit electrically connected to the first domino circuit through a first multiplexed output terminal and electrically connected to the second domino circuit through a second multiplexed output terminal, wherein,

the first multiplexed output is generated at the first multiplexed output node;

the second multiplexed output is generated at the second multiplexed output node; and is also provided with

The memory circuit maintains the first multiplexed output and the second multiplexed output during the precharge period.

7. The dynamic module of claim 6, wherein,

the at least one first phase setting circuit is electrically connected to the first multiplexing output terminal, and is controlled by the first clock signal; and

the at least one second phase setting circuit is electrically connected to the second multiplexing output terminal, and the at least one second phase setting circuit is controlled by the second clock signal.

8. The dynamic module of claim 7, wherein during the precharge,

the first decision selection stage is disconnected from the first multiplexing output node, and

the second decision selecting stage circuit is disconnected from the second multiplexing output terminal.

9. The dynamic module of claim 3, wherein,

during the evaluation period, the first decision selecting stage circuit is selectively and electrically connected to the first multiplexing output terminal, and the second decision selecting stage circuit is selectively and electrically connected to the second multiplexing output terminal.

10. The dynamic module of claim 6, wherein,

the first multiplexer comprises a first positive output circuit and a first negative output circuit, and the second multiplexer comprises a second positive output circuit and a second negative output circuit, wherein during the evaluation period,

One of the first positive electrode output circuit and the second positive electrode output circuit generates the first multiplexed output, and

one of the first negative output circuit and the second negative output circuit generates the second multiplexed output.

11. The dynamic module of claim 10, wherein,

when the first predetermined bit is at a first logic level and the second predetermined bit is at a second logic level, the first positive output circuit generates the first multiplexed output and the first negative output circuit generates the second multiplexed output, and

when the first previous decision bit is the second logic level and the second previous decision bit is the first logic level, the second positive output circuit generates the first multiplexed output and the second negative output circuit generates the second multiplexed output.

12. The dynamic module of claim 10, wherein the at least one first phase setting circuit comprises:

a first phase setting circuit electrically connected to the first decision selecting stage circuit, the first positive output circuit and the first negative output circuit, for receiving the first clock signal and generating a first selection signal; and

And a second first phase setting circuit electrically connected to the first decision selecting stage circuit, the first positive output circuit and the first negative output circuit for receiving the second clock signal and generating a second first selection signal.

13. The dynamic module of claim 12, wherein the at least one second phase setting circuit comprises:

a first phase setting circuit electrically connected to the second decision selecting stage circuit, the second positive output circuit and the second negative output circuit, for receiving the first clock signal and generating a first second selection signal; and

and a second phase setting circuit electrically connected to the second decision selecting stage circuit, the second positive output circuit and the second negative output circuit for receiving the second clock signal and generating a second selection signal.

14. The dynamic module of claim 13, wherein during the precharge,

the first and second positive electrode output circuits stop generating the first multiplexed output, and

the first negative output circuit and the second negative output circuit stop generating the second multiplexed output.

15. The dynamic module of claim 13, wherein, during the review period,

If the first previous decision bit is a first logic level and the second previous decision bit is a second logic level, the first selection signal is equal to the first previous decision bit and the second selection signal is equal to the second previous decision bit; and

if the first predetermined bit is the second logic level and the second predetermined bit is the first logic level, the first second selection signal is equal to the second predetermined bit and the second selection signal is equal to the first predetermined bit.

16. The dynamic module of claim 1, wherein, during the review,

if the first previous decision bit is at a first logic level and the second previous decision bit is at a second logic level,

the first domino circuit updates the first multiplexed output with the first single-rail output, updates the second multiplexed output with the second single-rail output, and

the second domino circuit stops generating the first multiplexed output and the second multiplexed output.

17. The dynamic module of claim 1, wherein, during the review,

when the first previous decision bit is at a second logic level and the second previous decision bit is at a first logic level,

The first domino circuit stops generating the first multiplexed output and the second multiplexed output, and

the second domino circuit updates the first multiplexed output with the third single-rail output and updates the second multiplexed output with the fourth single-rail output.

18. The dynamic module of claim 1, wherein the evaluation period and the precharge period are determined by the first clock signal and the second clock signal.

19. A decision feedback equalizer comprising:

a first speculative path providing a first previous decision bit and a second previous decision bit during an evaluation period, wherein the first previous decision bit and the second previous decision bit are complementary to each other; and

a second speculative path electrically connected to the first speculative path, comprising:

a first sense amplifier whose output comprises a first rail-to-rail output pair of a first monorail output and a second monorail output;

a second sense amplifier whose output comprises a second rail-to-rail output pair of a third monorail output and a fourth monorail output; and

a dynamic module electrically connected to the first sense amplifier and the second sense amplifier, comprising:

a first domino circuit producing a first multiplexed output, the first domino circuit comprising:

a first decision selector circuit electrically connected to the first multiplexer and the at least one first phase setting circuit for receiving the first previous decision bit and the second previous decision bit; and

a second domino circuit producing a second multiplexed output, the second domino circuit comprising:

at least one second phase setting circuit receiving a second clock signal, wherein the first clock signal and the second clock signal are complementary to each other; and

during the evaluation, the first multiplexed output and the second multiplexed output are selectively updated with one of the first rail-to-rail output pair and the second rail-to-rail output pair, and

20. The decision feedback equalizer of claim 19 wherein the dynamic block further comprises:

and a memory circuit electrically connected to the first domino circuit and the second domino circuit, which maintains the first multiplexed output and the second multiplexed output during the precharge period.

21. The decision feedback equalizer of claim 20 wherein the second speculative path further comprises:

a first inverter electrically connected to the dynamic module, the memory circuit and the first speculative path; and

a second inverter electrically connected to the dynamic module, the memory circuit and the first speculative path, wherein during the precharge,

the first inverter converts the first multiplexed output into a third previous decision bit, and

the second inverter converts the second multiplexed output into a fourth prior decision bit,

wherein the first speculative path receives the third previous decision bit and the fourth previous decision bit.

22. The decision feedback equalizer of claim 19 wherein the evaluation period and the precharge period are determined by the first clock signal and the second clock signal.