WO2021102927A1

WO2021102927A1 - Clock generation circuit

Info

Publication number: WO2021102927A1
Application number: PCT/CN2019/122029
Authority: WO
Inventors: 刘铛; 闵卿
Original assignee: 华为技术有限公司
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2021-06-03
Also published as: CN114731155A

Abstract

Disclosed is a clock generation circuit, comprising a multi-phase clock generation circuit, an FM, a PD and a control circuit, wherein the multi-phase clock generation circuit is used for generating a multi-phase clock signal according to a first control signal and a reference clock signal; the FM is used for performing frequency multiplication on the multi-phase clock signal to generate an output clock signal; the PD is used for generating a phase error signal according to the phase of the output clock signal; and the control circuit is used for generating the first control signal according to the phase error signal. The phase error signal is associated with the output clock signal, and therefore, the phase error signal contains the influence of the FM on the output clock signal during the process of synthesizing the output clock signal; the first control signal generated by the control circuit on the basis of the phase error signal can adjust the process of the multi-phase clock generation circuit generating the multi-phase clock signal, thereby changing an input of the FM in order to correct the influence of the FM on the output clock signal and reduce spur components in the frequency spectrum of the output clock signal, such that the output clock signal satisfies requirements.

Description

A clock generating circuit

Technical field

The embodiments of the present application relate to the field of electronic circuits, and in particular to a clock generation circuit.

Background technique

The clock generation circuit is an important part of a wired or wireless system. This circuit can be used to obtain a clock signal of a desired frequency. Figure 1 is a schematic diagram of a traditional clock generation circuit. The clock generation circuit includes: a multi-phase clock generation circuit, a phase detector (PD), a control circuit and a frequency multiplier (FM), when the reference clock signal After the multi-phase clock generation circuit, a multi-phase clock signal can be generated. FM can synthesize an output clock signal with a certain frequency based on the multi-phase clock signal. Because the multi-phase clock generation circuit is susceptible to various factors (such as manufacturing process, temperature, etc.) ) Will cause the generated multi-phase clock signal to have a phase error. In order to eliminate the phase error, the phase of the reference clock signal and the multi-phase clock signal can be compared through the PD and the phase error signal is generated, and then sent to the control circuit, and then The control circuit outputs a control signal to the multi-phase clock generating circuit based on the phase error signal, so that the multi-phase clock generating circuit generates a qualified multi-phase clock signal.

However, even if the multi-phase clock generating circuit can generate qualified multi-phase clock signals, due to the non-ideal effect of FM itself, it will affect the process of FM synthesizing the output clock signal with the multi-phase clock signal, resulting in a large frequency spectrum of the output clock signal. The burr composition cannot meet the demand.

Summary of the invention

The embodiment of the present application provides a clock generation circuit, which can reduce glitch components in the frequency spectrum of the output clock signal, so that the output clock signal can meet requirements.

The embodiment of the present application provides a clock generation circuit, which includes: a multi-phase clock generation circuit, FM, PD, and a control circuit. Among them, the output terminal of the multi-phase clock generating circuit is coupled with the input terminal of the FM, the output terminal of the FM is coupled with the input terminal of the PD, the output terminal of the PD is coupled with the input terminal of the control circuit, and the output terminal of the control circuit is coupled with the multi-phase clock. The input of the circuit is coupled, the multi-phase clock generation circuit is used to generate a multi-phase clock signal according to the first control signal and the reference clock signal, FM is used to multiply the multi-phase clock signal to generate an output clock signal, and the PD is used to generate an output clock signal according to the output clock signal. The phase of generates a phase error signal, and the control circuit is used to generate a first control signal according to the phase error signal.

In the above clock generation circuit, the correction loop of the circuit is composed of PD and a control circuit, and the input signal of the correction loop is the output clock signal output by the FM, and the PD can generate a phase error signal based on the phase of the output clock signal. The phase error signal is related to the output clock signal. Therefore, the phase error signal includes the influence of the FM on the output clock signal during the process of synthesizing the output clock signal. Therefore, the control circuit generates the first output clock signal based on the phase error signal. The control signal can gradually adjust the process of multi-phase clock generation circuit generating multi-phase clock signals, and then change the input of FM to gradually correct the influence of FM on the output clock signal, reduce the glitch component in the frequency of the output clock signal, and make the output clock The signal can meet the demand.

Optionally, the PD may include BBPD and DL. The first input terminal of BBPD is coupled with the output terminal of FM, the second input terminal of BBPD is coupled with the output terminal of the second DL, and the input terminal of the second DL is coupled with the output terminal of FM. Coupling, where the second DL is used to delay the output clock signal to obtain the delayed output clock signal, and BBPD is used to compare the phase of the output clock signal and the phase of the delayed output clock signal and generate a phase error signal.

In the above implementation, the two input signals of BBPD are respectively the output clock signal output by FM and the delayed output clock signal output by the second DL. BBPD can generate a phase error signal by comparing the phase difference between the two clock signals , Used to indicate the influence of the first DL and FM on the frequency of the output clock signal.

Optionally, the multi-phase clock generating circuit may be a first DL, and the first DL is used to adjust the first delay value according to the first control signal, and delay the reference clock signal according to the adjusted first delay value to obtain the multi-phase clock signal .

In the foregoing implementation manner, a multi-phase clock signal can be generated through the first DL to increase the flexibility and selectivity of the solution.

Optionally, the phase error signal includes a first phase error signal, and BBPD is also used to compare the phase of the output clock signal and the phase of the delayed output clock signal to obtain the first delay error, and generate the first delay error according to the first delay error. A phase error signal. The first delay error is related to the delay error caused by the first DL and FM to the output clock signal. The control circuit is also used for generating a first control signal according to the first phase error signal.

In the foregoing implementation manner, after the BBPD obtains the first delay error, the first phase error signal may be generated based on the first delay error, and the first phase error signal is used to indicate the magnitude of the first delay error. After receiving the first phase error signal, the control circuit can determine the magnitude of the first delay error, and calculate the magnitude of the delay error caused by the first DL and FM to the output clock signal according to the magnitude of the first delay error, and then generate The first control signal is used to adjust the process of generating the multi-phase clock signal by the first DL.

Optionally, the phase error signal further includes a second phase error signal, and BBPD is also used to compare the phase of the output clock signal and the phase of the delayed output clock signal to obtain the second delay error, and generate it according to the second delay error The second phase error signal, and the second delay error is the delay error caused by the second DL on the delayed output clock signal. The control circuit is also used for generating a second control signal according to the second phase error signal. The second DL is also used to adjust the second delay value according to the second control signal, and delay the output clock signal according to the adjusted second delay value to obtain the delayed output clock signal, so that the output clock signal is the same as the delayed output clock Signal alignment.

In the foregoing implementation manner, after the BBPD obtains the second delay error, the second phase error signal may be generated based on the second delay error, and the second phase error signal is used to indicate the magnitude of the second delay error. After the control circuit receives the second phase error signal, it can analyze it to determine the size of the second delay error, and generate a second control signal to adjust the second DL delay output clock process, so that the output clock signal and the delay After the output clock signal is aligned.

Optionally, if the first DL is the first VCDL, the clock generation circuit further includes: a first digital-to-analog converter DAC. The first DAC is used to perform digital-to-analog conversion on the first control signal to obtain the converted first control signal. The first DL is also used to adjust the first delay value according to the converted first control signal, and delay the reference clock signal according to the adjusted first delay value to obtain a multi-phase clock signal.

In the foregoing implementation manner, if the first DL is the first VCDL, the first DAC can be set to perform digital-to-analog conversion on the first control signal to realize the adjustment of the first DL, which increases the flexibility and selectivity of the solution.

Optionally, if the second DL is the second VCDL, the clock generation circuit further includes: a second DAC. The second DAC is used to perform digital-to-analog conversion on the second control signal to obtain the converted second control signal. The second DL is also used to adjust the second delay value according to the converted second control signal, and delay the output clock signal according to the adjusted second delay value to obtain the delayed output clock signal.

In the foregoing implementation manner, if the second DL is the second VCDL, the second DAC can be set to perform digital-to-analog conversion on the second control signal to realize the adjustment of the second DL, which increases the flexibility and selectivity of the solution.

Optionally, the frequency of the output clock signal may be an integer multiple of the frequency of the reference clock signal.

Optionally, the frequency of the output clock signal may be a non-integer multiple of the frequency of the reference clock signal.

The embodiment of the present application provides a clock generating circuit, which includes a multi-phase clock generating circuit, FM, PD, and a control circuit; the output terminal of the multi-phase clock generating circuit is coupled with the input terminal of the FM, and the output terminal of the FM is coupled with the input terminal of the FM. The input end of the PD is coupled, the output end of the PD is coupled to the input end of the control circuit, and the output end of the control circuit is coupled to the input end of the multi-phase clock generating circuit; wherein, the multi-phase clock generating circuit is used for according to the first control signal and the reference The clock signal generates a multi-phase clock signal, FM is used to multiply the frequency of the multi-phase clock signal to generate an output clock signal, PD is used to generate a phase error signal according to the phase of the output clock signal, and the control circuit is used to generate a first control signal according to the phase error signal . In the above clock generation circuit, the correction loop of the circuit is composed of PD and a control circuit, and the input signal of the correction loop is the output clock signal output by the FM, and the PD can generate a phase error signal based on the phase of the output clock signal. The phase error signal is related to the output clock signal. Therefore, the phase error signal includes the influence of the FM on the output clock signal during the process of synthesizing the output clock signal. Therefore, the control circuit generates the first output clock signal based on the phase error signal. The control signal can gradually adjust the process of generating the multi-phase clock signal by the multi-phase clock generating circuit, and then change the FM input to gradually correct the influence of FM on the output clock signal, reduce the burr component in the frequency spectrum of the output clock signal, and make the output clock The signal can meet the demand.

Description of the drawings

Figure 1 is a schematic diagram of a conventional clock generating circuit;

FIG. 2 is a schematic structural diagram of a clock generation circuit provided by an embodiment of the application;

3 is a schematic diagram of another structure of a clock generating circuit provided by an embodiment of the application;

FIG. 4 is a schematic structural diagram of a first DL provided by an embodiment of this application;

FIG. 5 is a schematic diagram of synthesizing and outputting a clock signal based on a multi-phase clock signal according to an embodiment of the application;

6 is another schematic diagram of synthesizing and outputting a clock signal based on a multi-phase clock signal according to an embodiment of the application;

FIG. 7 is a schematic diagram of an output clock signal and a delayed output clock signal provided by an embodiment of the application.

Detailed ways

The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the drawings in the embodiments of the present application.

FIG. 2 is a schematic structural diagram of the clock generation circuit provided by the embodiment of the application. Please refer to FIG. 2. An embodiment of the clock generation circuit provided by the embodiment of the application includes: a multi-phase clock generation circuit, FM, PD, and control circuit , Where the output terminal of the multiphase clock generating circuit is coupled with the input terminal of the FM, the output terminal of the FM is coupled with the input terminal of the PD, the output terminal of the PD is coupled with the input terminal of the control circuit, and the output terminal of the control circuit is coupled with the multiphase clock The input terminal of the generating circuit is coupled.

In the above-mentioned clock generation circuit, the multi-phase clock generation circuit can be used to receive an externally input reference clock signal, and process the reference clock signal according to the first control signal from the control circuit to generate a multi-phase clock signal, that is, a plurality of Different phase clocks, and then send the multi-phase clock signal to the FM. After FM receives a multi-phase clock signal, it can select the required clock from the multi-phase clock signal to generate an output clock signal with a certain frequency. The frequency of the output clock signal is an integer multiple or non-integer of the frequency of the reference clock signal For example, the frequency of the output clock signal is 1.5 times the frequency of the reference clock signal, another example is the frequency of the output clock signal is 3 times the frequency of the reference clock signal, and so on. The PD and the control circuit form a correction loop, which is used to correct the influence of the multi-phase clock generation circuit and FM on the frequency of the output clock signal. Specifically, the PD can receive the output clock signal from the FM, and according to the phase of the output clock signal Generate a phase error signal, and then send the phase error signal to the control circuit. After receiving the phase error signal from the PD, the control circuit can generate a first control signal based on the phase error signal, and send the first control signal to the multiphase clock generating circuit to adjust the process of generating the multiphase clock signal by the multiphase clock generating circuit.

Since the phase error signal is generated based on the output clock signal, the phase error signal includes the influence of the multiphase clock generation circuit and FM on the frequency of the output clock signal, and the control circuit generates the first control signal based on the phase error signal , Can gradually adjust the process of multi-phase clock generation circuit generating multi-phase clock signal, not only can correct the influence of multi-phase clock generation circuit on the frequency of the output clock signal, but also correct the influence of FM on the frequency of the output clock signal , Thereby reducing the glitch component in the frequency of the output clock signal, so that the output clock signal can meet the demand.

On the basis of the embodiment corresponding to FIG. 2, this application also provides another embodiment to further illustrate the clock generation circuit provided by this application. FIG. 3 is a schematic diagram of another structure of a clock generation circuit provided by an embodiment of this application. Please refer to FIG. 3. Another embodiment of a clock generation circuit provided by an embodiment of this application includes: a first delay line (DL) , FM, bang-bang Phase Detector (BBPD), second DL and control circuit, wherein the output terminal of the first DL is coupled with the input terminal of FM, and the first input terminal of BBPD is coupled with the input terminal of FM. The output terminal is coupled, the second input terminal of the BBPD is coupled with the output terminal of the second DL, the input terminal of the second DL is coupled with the output terminal of the FM, and the output terminal of the control circuit is coupled with the input terminal of the first DL.

In the above clock generation circuit, the first DL can be used to receive an externally input reference clock signal, adjust its own first delay value according to the first control signal from the control circuit, and then delay the reference clock according to the adjusted first delay value Signal to obtain a multi-phase clock signal, that is, multiple clocks with different phases, and then send the multi-phase clock signal to the FM. Specifically, the first DL has multiple stages of delay units (for example, inverters) connected in sequence, and each stage of the delay unit is set with a first delay value, so each stage of delay unit can respond to the input based on the first delay value. The clock is delayed, and the delayed clock is output to the FM and the next-stage delay unit. For ease of understanding, the first DL will be further introduced in conjunction with FIG. 4. FIG. 4 is a schematic structural diagram of the first DL provided by an embodiment of this application. As shown in FIG. 4, the period of the reference clock signal is 1 ns, and the first DL is The first delay value of each stage of delay unit in DL is 1/3ns (that is, 120°). When the first stage delay unit delays the reference clock signal by 1/3ns, the first phase clock signal can be obtained, and its phase is 120° °, the second-stage delay unit can delay the first phase clock signal by 1/3ns to obtain the second-phase clock signal, the phase of which is 240°, and so on, the third-stage delay unit can also output the third phase clock signal, Therefore, the first phase clock signal, the second phase clock signal, and the third phase clock signal constitute a multi-phase clock signal, and each stage of the delay unit can send the delayed clock to the FM, that is, the first DL can send the clock to the FM. FM outputs a multi-phase clock signal. It should be understood that the first DL in FIG. 3 only uses a three-stage delay unit as a schematic illustration, and does not limit the number of stages of the delay unit in the first DL in this application.

After receiving the multi-phase clock signal, FM can select the required clock from the multi-phase clock signal, and generate an output clock signal with a certain frequency based on the selected clock. The frequency of the output clock signal is the frequency of the reference clock signal Of rational multiples. For ease of understanding, the process of synthesizing an output clock signal will be introduced below in conjunction with FIG. 5. FIG. 5 is a schematic diagram of synthesizing an output clock signal based on a multi-phase clock signal according to an embodiment of the application. It should be noted that the process shown in FIG. 5 The example is related to the example shown in Figure 4. As shown in Figure 5, suppose the frequency of the required output clock signal is 3 times the frequency of the reference clock signal. Since the period of the reference clock signal is 1 ns, the ideal output clock signal can be known The period is 1/3ns, so FM can select the reference clock signal, the first phase clock signal and the second phase clock signal to synthesize the output clock signal.

However, in practical applications, because the first DL is susceptible to various factors, the delay units of each level of the first DL cannot accurately delay the reference clock signal, that is, the multi-phase clock generated by the first DL The signal has a delay error, which makes the output clock signal synthesized based on the multi-phase clock signal have a delay error. Further, the non-ideal effect of FM itself will also affect the process of synthesizing the output clock signal based on the multi-phase clock signal. Therefore, the first Both DL and FM will cause a delay error in the output clock signal. For ease of understanding, the process of synthesizing the output clock signal will be further introduced below in conjunction with FIG. 6. FIG. 6 is another schematic diagram of synthesizing the output clock signal based on the multi-phase clock signal according to an embodiment of the application. It should be noted that FIG. 6 The example shown is related to the example shown in FIG. 5, and for convenience of explanation, each clock signal only shows the rising edge of the clock (the upward arrow in FIG. 6). As shown in FIG. 6, because the first DL cannot Perform an accurate delay so that the first phase clock signal has a delay error Δt1, that is, the deviation between the ideal first phase clock signal (dashed arrow) and the actual first phase clock signal (solid arrow) in Fig. 6, Similarly, the second phase clock signal also has a delay error △t2. If the FM synthesizes the output clock signal based on the reference clock signal, the actual first phase clock signal and the actual second phase clock signal under ideal conditions, the output clock signal The delay error of △t1 and △t2 is △t1 and △t2. Due to the non-ideal effect of FM itself, it will affect the process of FM synthesizing the output clock signal, resulting in changes in △t1 and △t2. Therefore, in the actual output clock signal, the first The delay errors caused by DL and FM are △t1' and △t2'.

In order to correct the delay error in the output clock signal, the first DL can be adjusted accordingly through the correction loop formed by the second DL, BBPD and the control circuit. Specifically, after receiving the output clock signal generated by the FM, the second DL may delay the output clock signal by nearly one cycle to obtain the delayed output clock signal. After the BBPD receives the output clock signal generated by FM and the delayed output clock signal generated by the second DL, it can compare the phases between the two to obtain the first delay error and the second delay error, where the first delay error and the second delay error The first DL and FM are related to the delay error caused by the output clock signal, and the second delay error is the delay error caused by the second DL on the delayed output clock signal. For ease of understanding, the first delay error and the second delay error will be further introduced below in conjunction with FIG. 7. FIG. 7 is a schematic diagram of the output clock signal and the delayed output clock signal provided by an embodiment of the application. It should be noted that, The example shown in FIG. 7 is related to the example shown in FIG. 6. As shown in Figure 7, the second delay value of the second DL is 1/3ns+△t1'. In an ideal state, the second DL can accurately delay the output clock signal by 1/3ns+△t1', so that the output clock signal and delay The subsequent output clock signal is aligned, which is the ideal situation shown in Figure 7 (the two rising edges in the rectangular box in Figure 7 are aligned). However, because the second DL is susceptible to various factors, it cannot be The clock signal is accurately delayed, resulting in the output clock signal and the delayed output clock signal cannot be aligned, that is, the two rising edges in the rectangular box in Figure 7 cannot be aligned, and there is a delay error between the two rising edges. The error is the delay error caused by the second DL on the delayed output clock signal, that is, the second delay error.

In order to correct the second delay error, the second delay value of the second DL can be adjusted by the control circuit, so that the output clock signal and the delayed output clock signal can be aligned. Specifically, after BBPD compares the phase of the output clock signal with the phase of the delayed output clock signal, the second delay error can be obtained. BBPD can generate the second phase error signal based on the second delay error. It should be noted that the second The phase error signal is a digital signal used to indicate the magnitude of the second delay error. After the control circuit receives the second phase error signal, it can analyze it to determine the magnitude of the second delay error, and generate a second control signal, which is also a digital signal, used to adjust the second DL The second delay value. Still in the example shown in FIG. 7, if the control circuit determines that the second delay error is lagging 10° (that is, lagging 1/36ns) based on the second phase error signal, the second control signal can be generated for adjusting the second delay error. The second delay value of DL reduces the second delay value by 1/36ns.

It is usually a fast process for the control circuit to adjust the second delay value of the second DL through the second control signal. When the process is completed, the output clock signal and the delayed output clock signal can be aligned, as shown in Figure 7 The ideal situation. Based on this ideal situation, BBPD can compare the phase of the output clock signal with the phase of the delayed output clock signal to obtain the first delay error, which is related to the delay error caused by the first DL and FM on the output clock signal . Still in the example shown in Figure 7, after BBPD receives the aligned output clock signal and the delayed output clock signal, it can compare the phase of the rising edge A with the phase of the rising edge B, and the phase difference between the two is 2 △t1'-△t2', and compare the phase of the rising edge C and the phase of the rising edge D, the phase difference between the two is △t1'+△t2', so 2△t1'-△t2',△ t1'+△t2' is the first delay error. After the BBPD obtains the first delay error, it can generate a first phase error signal based on the first delay error. The first phase error signal is also a digital signal, which is used to indicate the magnitude of the first delay error. After receiving the first phase error signal, the control circuit can determine the magnitude of the first delay error, and calculate the magnitude of the delay error caused by the first DL and FM to the output clock signal according to the magnitude of the first delay error, and then generate The first control signal, where the first control signal is used to adjust the first delay value of the first DL. Still in the example shown in Figure 7, after receiving the first phase error signal, the control circuit can determine the magnitude of △t1'+△t2' and 2△t1'-△t2', and based on △t1'+△t2' and 2△t1'-△t2' calculates the magnitude of △t1' and △t2', and generates the first control signal according to the magnitude of △t1' and △t2' to adjust the first delay value of the first DL, for example, control The circuit calculates that △t1' is 5° ahead (ie lags 1/72ns), and △t2' is 10° lag (ie lags 1/36ns), the first-stage delay unit of the first DL can be adjusted by the first control signal The first delay value of is increased by 1/72ns, and the first delay value of the second-stage delay unit is decreased by 1/36ns. Therefore, after the first DL receives the first control signal sent by the control circuit, it can adjust the first delay value according to the first control signal, and delay the reference clock signal according to the adjusted first delay value to obtain a multi-phase clock signal, Because the first control signal can adjust the process of generating the multi-phase clock signal by the first DL, and then change the input of FM to gradually correct the influence of FM on the output clock signal, reduce the glitch component in the frequency spectrum of the output clock signal, and make the output clock signal Able to meet the demand.

In addition, in the clock generation circuit provided in the embodiment of the present application, the types of the first DL and the second DL can be set according to actual requirements. In a possible implementation manner, the first DL may be a first digital control delay line (DCDL) to increase the flexibility and selectivity of the solution. In a possible implementation manner, the second DL may be a second DCDL to increase the flexibility and selectivity of the solution. In a possible implementation manner, the first DL may also be a first voltage control delay line (VCDL). When the first DL is the first VCDL, a first digital-to-analog converter (DAC) is also provided between the control circuit and the first VCDL. Since the first control signal output by the control circuit is a digital signal, The first DAC may perform digital-to-analog conversion on the first control signal, and send the first control signal converted into an analog signal to the first VCDL, so as to realize the adjustment of the first VCDL. In a possible implementation manner, the second DL may also be a second VCDL. When the second DL is the second VCDL, a second DAC is also provided between the control circuit and the first VCDL. Since the second control signal output by the control circuit is a digital signal, the second DAC can count the second control signal. Analog conversion, sending the second control signal converted into an analog signal to the second VCDL, so as to realize the adjustment of the second VCDL.

The clock generation circuit provided by the embodiment of the present application can directly correct the output clock signal, and can reduce the glitch components in the frequency spectrum of the output clock signal, so that the quality of the output clock signal can meet actual requirements.

Claims

A clock generating circuit, characterized in that the clock generating circuit includes: a multi-phase clock generating circuit, a frequency multiplier FM, a phase detector PD, and a control circuit;

The output terminal of the multi-phase clock generating circuit is coupled with the input terminal of the FM, the output terminal of the FM is coupled with the input terminal of the PD, and the output terminal of the PD is coupled with the input terminal of the control circuit, The output terminal of the control circuit is coupled with the input terminal of the multi-phase clock generating circuit;

Wherein, the multi-phase clock generating circuit is used for generating a multi-phase clock signal according to the first control signal and a reference clock signal, the FM is used for multiplying the frequency of the multi-phase clock signal to generate an output clock signal, and the PD is used for A phase error signal is generated according to the phase of the output clock signal, and the control circuit is configured to generate the first control signal according to the phase error signal.
The clock generating circuit according to claim 1, wherein the PD includes a bang-bang phase detector BBPD and a second delay line DL, and the first input terminal of the BBPD is coupled with the output terminal of the FM, The second input terminal of the BBPD is coupled with the output terminal of the second DL, and the input terminal of the second DL is coupled with the output terminal of the FM;

Wherein, the second DL is used to delay the output clock signal to obtain a delayed output clock signal, and the BBPD is used to compare the phase of the output clock signal and the phase of the delayed output clock signal and generate The phase error signal.
The clock generation circuit according to claim 2, wherein the multi-phase clock generation circuit is a first DL, and the first DL is used to adjust a first delay value according to the first control signal, and according to the adjustment The subsequent first delay value delays the reference clock signal to obtain the multi-phase clock signal.
4. The clock generation circuit of claim 3, wherein the phase error signal comprises a first phase error signal, and the BBPD is also used to compare the phase of the output clock signal with the delayed output clock signal The first delay error is obtained, and the first phase error signal is generated according to the first delay error. The first delay error is related to the first DL and the FM to the output clock The delay error caused by the signal is correlated;

The control circuit is also used to generate the first control signal according to the first phase error signal.
The clock generation circuit according to claims 2 to 4, wherein the phase error signal further comprises a second phase error signal, and the BBPD is also used to compare the phase of the output clock signal and the delayed Output the phase of the clock signal to obtain a second delay error, and generate the second phase error signal according to the second delay error, and the second delay error is the effect of the second DL on the delayed Delay error caused by output clock signal;

The control circuit is further configured to generate a second control signal according to the second phase error signal;

The second DL is also used to adjust a second delay value according to the second control signal, and delay the output clock signal according to the adjusted second delay value to obtain a delayed output clock signal, so that the output The clock signal is aligned with the delayed output clock signal.
The clock generation circuit according to any one of claims 3 to 5, wherein if the first DL is a first voltage-controlled delay line VCDL, the clock generation circuit further comprises: a first digital-to-analog converter DAC;

The first DAC is used to perform digital-to-analog conversion on the first control signal to obtain the converted first control signal;

The first DL is further configured to adjust a first delay value according to the converted first control signal, and delay the reference clock signal according to the adjusted first delay value to obtain the multi-phase clock signal.
5. The clock generation circuit of claim 5, wherein if the second DL is a second VCDL, the clock generation circuit further comprises: a second DAC;

The second DAC is used to perform digital-to-analog conversion on the second control signal to obtain a converted second control signal;

The second DL is further configured to adjust a second delay value according to the converted second control signal, and delay the output clock signal according to the adjusted second delay value to obtain a delayed output clock signal.
7. The clock generating circuit according to any one of claims 1 to 7, wherein the frequency of the output clock signal is an integer multiple of the frequency of the reference clock signal.
7. The clock generating circuit according to any one of claims 1 to 7, wherein the frequency of the output clock signal is a non-integer multiple of the frequency of the reference clock signal.