CN114731155A - Clock generating circuit - Google Patents

Clock generating circuit Download PDF

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Publication number
CN114731155A
CN114731155A CN201980102513.4A CN201980102513A CN114731155A CN 114731155 A CN114731155 A CN 114731155A CN 201980102513 A CN201980102513 A CN 201980102513A CN 114731155 A CN114731155 A CN 114731155A
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phase
clock signal
signal
delay
output
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刘铛
闵卿
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

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Abstract

A clock generation circuit comprising a multi-phase clock generation circuit, an FM, a PD, and a control circuit, wherein: the multi-phase clock generating circuit is used for generating multi-phase clock signals according to the first control signals and the reference clock signals, the FM is used for multiplying the frequency of the multi-phase clock signals to generate output clock signals, the PD is used for generating phase error signals according to the phases of the output clock signals, and the control circuit is used for generating first control signals according to the phase error signals. The control circuit can adjust the process of generating the multi-phase clock signal by the multi-phase clock generating circuit based on the first control signal generated by the phase error signal, so as to change the input of the FM, correct the influence of the FM on the output clock signal, reduce the burr component in the frequency spectrum of the output clock signal and enable the output clock signal to meet the requirement.

Description

Clock generating circuit Technical Field
The embodiment of the application relates to the field of electronic circuits, in particular to a clock generation circuit.
Background
Clock generation circuits are an important component of wired or wireless systems, which can be used to obtain a clock signal of a desired frequency. Fig. 1 is a schematic diagram of a conventional clock generation circuit, which includes: a multi-phase clock generating circuit, a Phase Detector (PD), a control circuit and a frequency multiplier (freq multiplier, FM), when a reference clock signal passes through the multi-phase clock generating circuit, a multi-phase clock signal may be generated, FM may synthesize an output clock signal having a frequency based on the multi-phase clock signal, since the multi-phase clock generating circuit is susceptible to various factors (such as manufacturing process, temperature, etc.), the multi-phase clock signal generated by the multi-phase clock generating circuit has a phase error, and in order to eliminate the phase error, the phases of the reference clock signal and the multi-phase clock signal may be compared by the PD and a phase error signal generated, sent to the control circuit, and then outputting a control signal to the multi-phase clock generation circuit through the control circuit based on the phase error signal so that the multi-phase clock generation circuit generates qualified multi-phase clock signals.
However, even if the multiphase clock generation circuit can generate qualified multiphase clock signals, the FM itself has a non-ideal effect, which affects the process of synthesizing the output clock signal by the multiphase clock signals, and further causes a large glitch component in the frequency spectrum of the output clock signal, and thus cannot meet the requirement.
Disclosure of Invention
The embodiment of the application provides a clock generation circuit, which can reduce the burr component in the frequency spectrum of an output clock signal, so that the output clock signal can meet the requirement.
An embodiment of the present application provides a clock generation circuit, including: the device comprises a multi-phase clock generation circuit, an FM, a PD and a control circuit. The output end of the multi-phase clock generating circuit is coupled with the input end of an FM, the output end of the FM is coupled with the input end of a PD, the output end of the PD is coupled with the input end of a control circuit, the output end of the control circuit is coupled with the input end of the multi-phase clock generating circuit, the multi-phase clock generating circuit is used for generating multi-phase clock signals according to a first control signal and a reference clock signal, the FM is used for multiplying the frequency of the multi-phase clock signals to generate output clock signals, the PD is used for generating phase error signals according to the phases of the output clock signals, and the control circuit is used for generating the first control signal according to the phase error signals.
In the clock generating circuit, the correcting loop of the circuit is composed of the PD and the control circuit, and the input signal of the correcting loop is the output clock signal output by the FM, the PD can generate the phase error signal based on the phase of the output clock signal, and the phase error signal is associated with the output clock signal, so the phase error signal includes the influence of the FM on the output clock signal in the process of synthesizing the output clock signal, and the control circuit can gradually adjust the process of generating the multiphase clock signal by the multiphase clock generating circuit based on the first control signal generated by the phase error signal, and further change the input of the FM to gradually correct the influence of the FM on the output clock signal, reduce the glitch component in the frequency of the output clock signal, and enable the output clock signal to meet the requirement.
Alternatively, the PD may include BBPD and DLs, a first input of the BBPD being coupled to an output of the FM, a second input of the BBPD being coupled to an output of a second DL, an input of the second DL being coupled to an output of the FM, wherein the second DL is configured to delay the output clock signal to obtain a delayed output clock signal, and the BBPD is configured to compare a phase of the output clock signal with a phase of the delayed output clock signal and generate a phase error signal.
In the foregoing implementation manner, the two input signals of the BBPD are an output clock signal output by the FM and a delayed output clock signal output by the second DL, respectively, and the BBPD may generate a phase error signal by comparing a phase difference between the two clock signals, so as to indicate an influence of the first DL and the FM on the frequency of the output clock signal.
Optionally, the multi-phase clock generation circuit may be a first DL, and the first DL is configured to adjust a first delay value according to the first control signal, and delay the reference clock signal according to the adjusted first delay value to obtain the multi-phase clock signal.
In the above implementation, the multi-phase clock signal may be generated through the first DL to increase flexibility and selectivity of the scheme.
Optionally, the phase error signal includes a first phase error signal, and the BBPD is further configured to compare the phase of the output clock signal with the phase of the delayed output clock signal to obtain a first delay error, and generate the first phase error signal according to the first delay error, where the first delay error is associated with a delay error caused by the first DL and FM on the output clock signal. The control circuit is further configured to generate a first control signal based on the first phase error signal.
In the foregoing implementation, after obtaining the first delay error, the BBPD may generate a first phase error signal based on the first delay error, where the first phase error signal is used to indicate a magnitude of the first delay error. After receiving the first phase error signal, the control circuit can determine the magnitude of the first delay error, and calculate the magnitude of the delay error caused by the first DL and FM to the output clock signal according to the magnitude of the first delay error, so as to generate a first control signal, so as to adjust the process of generating the multi-phase clock signal by the first DL.
Optionally, the phase error signal further includes a second phase error signal, and the BBPD is further configured to compare the phase of the output clock signal with the phase of the delayed output clock signal to obtain a second delay error, and generate a second phase error signal according to the second delay error, where the second delay error is a delay error caused by the second DL to the delayed output clock signal. The control circuit is further configured to generate a second control signal based on the second phase error signal. The second DL is further configured to adjust a second delay value according to the second control signal, and delay the output clock signal according to the adjusted second delay value to obtain a delayed output clock signal, so that the output clock signal is aligned with the delayed output clock signal.
In the above implementation, after obtaining the second delay error, the BBPD may generate a second phase error signal based on the second delay error, where the second phase error signal is used to indicate a magnitude of the second delay error. The control circuit may analyze the second phase error signal after receiving it, to determine a magnitude of the second delay error, and generate a second control signal to adjust a process of delaying the output clock by the second DL, so that the output clock signal is aligned with the delayed output clock signal.
Optionally, if the first DL is the first VCDL, the clock generating circuit further includes: a first digital-to-analog converter DAC. The first DAC is used for carrying out digital-to-analog conversion on the first control signal to obtain a converted first control signal. The first DL is further configured to adjust a first delay value according to the converted first control signal, and delay the reference clock signal according to the adjusted first delay value to obtain the multi-phase clock signal.
In the foregoing implementation manner, if the first DL is the first VCDL, the first control signal may be subjected to digital-to-analog conversion by setting the first DAC, so as to implement adjustment of the first DL, thereby increasing flexibility and selectivity of the scheme.
Optionally, if the second DL is a second VCDL, the clock generating circuit further includes: a second DAC. The second DAC is used for carrying out digital-to-analog conversion on the second control signal to obtain a converted second control signal. The second DL is further configured to adjust a second delay value according to the converted second control signal, and delay the output clock signal according to the adjusted second delay value to obtain a delayed output clock signal.
In the foregoing implementation manner, if the second DL is the second VCDL, the second DAC may be configured to perform digital-to-analog conversion on the second control signal to adjust the second DL, so that flexibility and selectivity of the scheme are increased.
Alternatively, the frequency of the output clock signal may be an integer multiple of the frequency of the reference clock signal.
Alternatively, the frequency of the output clock signal may be a non-integer multiple of the frequency of the reference clock signal.
The embodiment of the application provides a clock generation circuit, which comprises a multi-phase clock generation circuit, an FM (frequency modulation), a PD (pulse width modulation) and a control circuit; the output end of the multi-phase clock generating circuit is coupled with the input end of the FM, the output end of the FM is coupled with the input end of the PD, the output end of the PD is coupled with the input end of the control circuit, and the output end of the control circuit is coupled with the input end of the multi-phase clock generating circuit; the multi-phase clock generating circuit is used for generating multi-phase clock signals according to a first control signal and a reference clock signal, the FM is used for multiplying the frequency of the multi-phase clock signals to generate output clock signals, the PD is used for generating phase error signals according to the phases of the output clock signals, and the control circuit is used for generating first control signals according to the phase error signals. In the clock generating circuit, the correcting loop of the circuit is composed of the PD and the control circuit, and the input signal of the correcting loop is the output clock signal output by the FM, the PD can generate the phase error signal based on the phase of the output clock signal, because the phase error signal is associated with the output clock signal, the phase error signal includes the influence of the FM on the output clock signal in the process of synthesizing the output clock signal, so the control circuit can gradually adjust the process of generating the multiphase clock signal by the multiphase clock generating circuit based on the first control signal generated by the phase error signal, and further change the input of the FM to gradually correct the influence of the FM on the output clock signal, reduce the glitch component in the frequency spectrum of the output clock signal, and enable the output clock signal to meet the requirement.
Drawings
FIG. 1 is a schematic diagram of a conventional clock generation circuit;
fig. 2 is a schematic structural diagram of a clock generation circuit according to an embodiment of the present disclosure;
fig. 3 is another schematic structural diagram of a clock generation circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a first DL provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of a multi-phase clock signal-based synthesis of an output clock signal according to an embodiment of the present application;
FIG. 6 is another schematic diagram of synthesizing an output clock signal based on multi-phase clock signals according to an embodiment of the present application;
fig. 7 is a schematic diagram of an output clock signal and a delayed output clock signal according to an embodiment of the present application.
Detailed Description
The following describes technical solutions in the embodiments of the present application in detail with reference to the drawings in the embodiments of the present application.
Fig. 2 is a schematic structural diagram of a clock generation circuit according to an embodiment of the present disclosure, and referring to fig. 2, an embodiment of the clock generation circuit according to the embodiment of the present disclosure includes: the device comprises a multi-phase clock generating circuit, an FM, a PD and a control circuit, wherein the output end of the multi-phase clock generating circuit is coupled with the input end of the FM, the output end of the FM is coupled with the input end of the PD, the output end of the PD is coupled with the input end of the control circuit, and the output end of the control circuit is coupled with the input end of the multi-phase clock generating circuit.
In the clock generating circuit, the multiphase clock generating circuit may be configured to receive an externally input reference clock signal, process the reference clock signal according to a first control signal from the control circuit to generate a multiphase clock signal, i.e., a plurality of clocks having different phases, and then transmit the multiphase clock signal to the FM. After receiving the multi-phase clock signals, the FM can select a desired clock from the multi-phase clock signals to generate an output clock signal having a frequency that is an integer or non-integer multiple of the frequency of the reference clock signal, for example, the frequency of the output clock signal is 1.5 times the frequency of the reference clock signal, and the frequency of the output clock signal is 3 times the frequency of the reference clock signal. The PD and the control circuit form a correction loop for correcting the influence of the multi-phase clock generation circuit and the FM on the frequency of the output clock signal, and specifically, the PD may receive the output clock signal from the FM, generate a phase error signal according to the phase of the output clock signal, and send the phase error signal to the control circuit. After receiving the phase error signal from the PD, the control circuit may generate a first control signal based on the phase error signal, and send the first control signal to the multi-phase clock generation circuit to adjust a process of the multi-phase clock generation circuit generating the multi-phase clock signal.
The control circuit can gradually adjust the process of generating the multi-phase clock signal by the multi-phase clock generating circuit based on the first control signal generated by the phase error signal, not only can correct the influence of the multi-phase clock generating circuit on the frequency of the output clock signal, but also can correct the influence of the FM on the frequency of the output clock signal, thereby reducing the burr component in the frequency of the output clock signal and enabling the output clock signal to meet the requirement.
On the basis of the embodiment corresponding to fig. 2, the present application further provides another embodiment to further describe the clock generation circuit provided in the present application. Fig. 3 is another schematic structural diagram of a clock generation circuit according to an embodiment of the present disclosure, and referring to fig. 3, another embodiment of the clock generation circuit according to the embodiment of the present disclosure includes: a first Delay Line (DL), an FM, a bang-bang Phase Detector (BBPD), a second DL, and a control circuit, wherein an output of the first DL is coupled to an input of the FM, a first input of the BBPD is coupled to an output of the FM, a second input of the BBPD is coupled to an output of the second DL, an input of the second DL is coupled to an output of the FM, and an output of the control circuit is coupled to an input of the first DL.
In the clock generating circuit, the first DL may be configured to receive a reference clock signal input from an external device, adjust a first delay value of the first DL according to a first control signal from the control circuit, delay the reference clock signal according to the adjusted first delay value to obtain a multi-phase clock signal, i.e., a plurality of clocks having different phases, and then send the multi-phase clock signal to the FM. Specifically, the first DL has a plurality of stages of delay units (e.g., inverters) connected in sequence, and each stage of delay unit is provided with a first delay value, so that each stage of delay unit can delay an input clock based on the first delay value and output the delayed clock to the FM and the next stage of delay unit. For convenience of understanding, the first DL is further described below with reference to fig. 4, fig. 4 is a schematic structural diagram of the first DL provided in this embodiment, and as shown in fig. 4, it is assumed that a period of a reference clock signal is 1ns, a first delay value of each stage of delay unit in the first DL is 1/3ns (i.e., 120 °), when the first stage of delay unit delays the reference clock signal for 1/3ns, a first phase clock signal with a phase of 120 ° is obtained, a second stage of delay unit delays the first phase clock signal for 1/3ns, a second phase clock signal with a phase of 240 ° is obtained, and so on, a third stage of delay unit may also output a third phase clock signal, so that the first phase clock signal, the second phase clock signal, and the third phase clock signal constitute a multi-phase clock signal, and each stage of delay unit may transmit a clock obtained after the delay thereof to FM, i.e. the first DL may output a multi-phase clock signal to the FM. It should be understood that the first DL in fig. 3 is only schematically illustrated by three stages of delay units, and does not limit the number of stages of the delay units of the first DL in the present application.
FM can select a desired clock from the multiphase clock signals after receiving the multiphase clock signals, and generate an output clock signal having a frequency that is a rational multiple of the frequency of the reference clock signal based on the selected clock. For convenience of understanding, the process of synthesizing the output clock signal is described below with reference to fig. 5, where fig. 5 is a schematic diagram of synthesizing the output clock signal based on the multi-phase clock signal according to the embodiment of the present application, it should be noted that the example shown in fig. 5 is associated with the example shown in fig. 4, as shown in fig. 5, the frequency of the required output clock signal is 3 times the frequency of the reference clock signal, and since the period of the reference clock signal is 1ns, it is known that the ideal period of the output clock signal is 1/3ns, the FM can select the reference clock signal, the first phase clock signal, and the second phase clock signal to synthesize the output clock signal.
However, in practical applications, the first DL is susceptible to various factors, and each stage of the delay unit of the first DL cannot accurately delay the reference clock signal, that is, the multi-phase clock signal generated by the first DL has a delay error, so that the output clock signal synthesized based on the multi-phase clock signal has a delay error, and further, the FM itself has a non-ideal effect and also affects the process of synthesizing the output clock signal based on the multi-phase clock signal, so both the first DL and the FM may cause the output clock signal to have a delay error. For the convenience of understanding, the process of synthesizing the output clock signal will be further described with reference to fig. 6, where fig. 6 is another schematic diagram of synthesizing the output clock signal based on the multi-phase clock signals provided in the embodiment of the present application, and it should be noted that the example shown in fig. 6 is associated with the example shown in fig. 5, and each clock signal only shows a rising edge of the clock (an upward arrow in fig. 6) for convenience of description, as shown in fig. 6, since the first DL cannot perform accurate delay, the delay error Δ t1 exists in the first phase clock signal, that is, the deviation between the ideal first phase clock signal (a dotted arrow) and the actual first phase clock signal (a solid arrow) in fig. 6, and similarly, the delay error Δ t2 exists in the second phase clock signal, if the output clock signal is synthesized based on the reference clock signal, the actual first phase clock signal and the actual second phase clock signal under the ideal condition of FM, the delay errors of the output clock signals are Δ t1 and Δ t2, and due to the non-ideal effect of FM itself, the process of FM synthesizing the output clock signals is affected, and Δ t1 and Δ t2 change, so the delay errors caused by the first DL and FM in the actually obtained output clock signals are Δ t1 'and Δ t 2'.
In order to correct the delay error in the output clock signal, the first DL can be adjusted accordingly by a correction loop formed by the second DL, BBPD and the control circuit. Specifically, after receiving the output clock signal generated by the FM, the second DL may delay the output clock signal by approximately one cycle to obtain a delayed output clock signal. After receiving the FM generated output clock signal and the second DL generated delayed output clock signal, the BBPD compares the phases of the FM generated output clock signal and the DL generated delayed output clock signal to obtain a first delay error and a second delay error, where the first delay error is associated with a delay error caused by the first DL and the FM to the output clock signal, and the second delay error is a delay error caused by the second DL to the delayed output clock signal. For convenience of understanding, the first delay error and the second delay error are further described below with reference to fig. 7, where fig. 7 is a schematic diagram of an output clock signal and a delayed output clock signal provided in an embodiment of the present application, and it should be noted that the example shown in fig. 7 is associated with the example shown in fig. 6. As shown in fig. 7, the second delay value of the second DL is 1/3ns +. DELTA.t 1 ', and in an ideal state, the second DL can accurately delay the output clock signal by 1/3ns +. DELTA.t 1', so that the output clock signal and the delayed output clock signal are aligned, i.e., in an ideal state shown in fig. 7 (two rising edges in the rectangular box in fig. 7 are aligned), however, since the second DL is susceptible to various factors, the output clock signal cannot be accurately delayed, and the output clock signal and the delayed output clock signal cannot be aligned, i.e., two rising edges in the rectangular box in fig. 7 cannot be aligned, and there is a delay error between the two rising edges, i.e., a delay error caused by the second DL to the delayed output clock signal, i.e., the second delay error.
To correct the second delay error, the second delay value of the second DL may be adjusted by the control circuit to enable alignment of the output clock signal and the delayed output clock signal. Specifically, after comparing the phase of the output clock signal with the phase of the delayed output clock signal, the BBPD may obtain a second delay error, and based on the second delay error, the BBPD may generate a second phase error signal, where the second phase error signal is a digital signal for indicating the magnitude of the second delay error. The control circuit may analyze the second phase error signal after receiving the second phase error signal, determine a magnitude of the second delay error, and generate a second control signal, which is also a digital signal and used to adjust a second delay value of the second DL. Still referring to the example shown in fig. 7, if the control circuit determines that the second delay error is delayed by 10 ° (i.e., by 1/36ns) based on the second phase error signal, the control circuit may generate the second control signal for adjusting the second delay value of the second DL such that the second delay value is reduced by 1/36 ns.
The control circuit adjusting the second delay value of the second DL by the second control signal is usually a fast process, and when the process is completed, the output clock signal and the delayed output clock signal can be aligned, for example, the ideal situation shown in fig. 7. Based on this ideal situation, the BBPD may compare the phase of the output clock signal to the phase of the delayed output clock signal to obtain a first delay error associated with the delay error caused by the first DL, FM on the output clock signal. In the example shown in fig. 7, after receiving the aligned output clock signal and the delayed output clock signal, the BBPD compares the phase of the rising edge a with the phase of the rising edge B to obtain a phase difference between the two signals as 2 Δ t1 '- Δ t 2', and compares the phase of the rising edge C with the phase of the rising edge D to obtain a phase difference between the two signals as Δ t1 '- Δ t 2', so 2 Δ t1 '- Δ t 2' - Δ t1 '- Δ t 2' is the first delay error. After the BBPD obtains the first delay error, a first phase error signal may be generated based on the first delay error, and the first phase error signal is also a digital signal for indicating a magnitude of the first delay error. The control circuit can determine the magnitude of the first delay error after receiving the first phase error signal, and calculate the magnitude of the delay error caused by the first DL and the FM to the output clock signal according to the magnitude of the first delay error, so as to generate a first control signal, wherein the first control signal is used for adjusting the first delay value of the first DL. In the example shown in fig. 7, the control circuit may determine the magnitudes of Δ t1 '+. DELTA.t 2' and 2. DELTA.t 1 '-. DELTA.t 2' after receiving the first phase error signal, calculate the magnitudes of Δ t1 'and Δ t 2' based on Δ t1 '+. DELTA.t 2' and 2. DELTA.t 1 '-. DELTA.t 2', generate the first control signal according to the magnitudes of Δ t1 'and Δ t 2' to adjust the first delay value of the first DL, for example, when the control circuit calculates that Δ t1 'is 5 ° advanced (i.e., 1/72ns delayed) and Δ t 2' is 10 ° delayed (i.e., 1/36ns delayed), increase 1/72ns by the first control signal and decrease 1/36ns by the first delay value of the first stage delay unit of the first DL. Therefore, after receiving the first control signal sent by the control circuit, the first DL can adjust the first delay value according to the first control signal, and delay the reference clock signal according to the adjusted first delay value to obtain the multiphase clock signal.
In addition, in the clock generation circuit provided in the embodiment of the present application, the types of the first DL and the second DL may be set according to actual requirements. In one possible implementation, the first DL may be a first Digitally Controlled Delay Line (DCDL) to increase flexibility and selectivity of the scheme. In one possible implementation, the second DL may be a second DCDL to increase flexibility and selectivity of the scheme. In one possible implementation, the first DL may also be a first Voltage Controlled Delay Line (VCDL). When the first DL is the first VCDL, a first Digital-to-Analog Converter (DAC) is further disposed between the control circuit and the first VCDL, and since the first control signal output by the control circuit is a Digital signal, the first DAC can perform Digital-to-Analog conversion on the first control signal, and send the first control signal converted into an Analog signal to the first VCDL, so as to implement adjustment of the first VCDL. In one possible implementation, the second DL may also be a second VCDL. When the second DL is the second VCDL, a second DAC is further disposed between the control circuit and the first VCDL, and since the second control signal output by the control circuit is a digital signal, the second DAC can perform digital-to-analog conversion on the second control signal, and send the second control signal converted into an analog signal to the second VCDL, so as to adjust the second VCDL.
The clock generation circuit provided by the embodiment of the application can directly correct the output clock signal, and can reduce the burr component in the frequency spectrum of the output clock signal, so that the quality of the output clock signal can meet the actual requirement.

Claims (9)

  1. A clock generation circuit, the clock generation circuit comprising: the device comprises a multi-phase clock generating circuit, a frequency multiplier FM, a phase discriminator PD and a control circuit;
    the output end of the multi-phase clock generation circuit is coupled with the input end of the FM, the output end of the FM is coupled with the input end of the PD, the output end of the PD is coupled with the input end of the control circuit, and the output end of the control circuit is coupled with the input end of the multi-phase clock generation circuit;
    the multi-phase clock generation circuit is used for generating multi-phase clock signals according to a first control signal and a reference clock signal, the FM is used for multiplying the frequency of the multi-phase clock signals to generate output clock signals, the PD is used for generating phase error signals according to the phase of the output clock signals, and the control circuit is used for generating the first control signal according to the phase error signals.
  2. The clock generation circuit of claim 1, wherein the PD comprises a bang-bang phase detector BBPD and a second delay line DL, wherein a first input of the BBPD is coupled to an output of the FM, wherein a second input of the BBPD is coupled to an output of the second DL, and wherein an input of the second DL is coupled to an output of the FM;
    wherein the second DL is configured to delay the output clock signal to obtain a delayed output clock signal, and the BBPD is configured to compare a phase of the output clock signal with a phase of the delayed output clock signal and generate the phase error signal.
  3. The clock generation circuit of claim 2, wherein the multi-phase clock generation circuit is a first DL, and the first DL is configured to adjust a first delay value according to the first control signal and delay the reference clock signal according to the adjusted first delay value to obtain the multi-phase clock signal.
  4. The clock generation circuit of claim 3, wherein the phase error signal comprises a first phase error signal, and wherein the BBPD is further configured to compare the phase of the output clock signal with the phase of the delayed output clock signal to obtain a first delay error, and to generate the first phase error signal according to the first delay error, the first delay error being associated with a delay error caused by the first DL, the FM on the output clock signal;
    the control circuit is further configured to generate the first control signal based on the first phase error signal.
  5. The clock generation circuit of claims 2 to 4, wherein the phase error signal further comprises a second phase error signal, the BBPD is further configured to compare the phase of the output clock signal with the phase of the delayed output clock signal to obtain a second delay error, and generate the second phase error signal according to the second delay error, the second delay error being a delay error caused by the second DL to the delayed output clock signal;
    the control circuit is further configured to generate a second control signal based on the second phase error signal;
    the second DL is further configured to adjust a second delay value according to the second control signal, and delay the output clock signal according to the adjusted second delay value to obtain a delayed output clock signal, so that the output clock signal is aligned with the delayed output clock signal.
  6. The clock generation circuit of any of claims 3 to 5, wherein if the first DL is a first Voltage Controlled Delay Line (VCDL), the clock generation circuit further comprises: a first digital-to-analog converter (DAC);
    the first DAC is used for carrying out digital-to-analog conversion on the first control signal to obtain a converted first control signal;
    the first DL is further configured to adjust a first delay value according to the converted first control signal, and delay the reference clock signal according to the adjusted first delay value to obtain the multi-phase clock signal.
  7. The clock generation circuit of claim 5, wherein if the second DL is a second VCDL, the clock generation circuit further comprises: a second DAC;
    the second DAC is used for carrying out digital-to-analog conversion on the second control signal to obtain a converted second control signal;
    the second DL is further configured to adjust a second delay value according to the converted second control signal, and delay the output clock signal according to the adjusted second delay value to obtain a delayed output clock signal.
  8. The clock generation circuit of any of claims 1 to 7, wherein the frequency of the output clock signal is an integer multiple of the frequency of the reference clock signal.
  9. The clock generation circuit of any of claims 1 to 7, wherein the frequency of the output clock signal is a non-integer multiple of the frequency of the reference clock signal.
CN201980102513.4A 2019-11-29 2019-11-29 Clock generating circuit Pending CN114731155A (en)

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