JP2000174744A - Frame synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently establish frame synchronization with a simple configuration. SOLUTION: A demodulation circuit output signal 14 reproduced in a demodulation circuit 12 together with a clock signal 13 is successively compared with a UW 19 from a frame synchronizing signal generation circuit 18 and a judgement circuit 40 judges them. The judgment circuit 40 executes judgement with a judgement condition that the matching number of codes and the non- matching number of codes with UW 19 are varied in accordance with a permission bit number setting signal 42 supplied from a permission number setting circuit 41. A synchronous state display signal 26 showing the establishment or the step-out of frame synchronism is generated by a synchronism protection circuit 23 and a synchronism establishment circuit 25 from a judgement circuit output signal 43 and it is supplied to a count circuit 49. The count circuit 49 generates a permission bit number setting signal 42 supplied from the permission number setting circuit 41 in accordance with the frame synchronous state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly, to a frame synchronization circuit for receiving and demodulating a framed digital modulation signal.

[0002]

2. Description of the Related Art In the field of broadcasting and communication, various types of communication data such as video data and audio data are digitally modulated and transmitted in units of a data structure called a frame.
In digital modulation, video data, audio data, and other data as digitized communication data are superimposed on a high-frequency electric signal that is a carrier wave. The digital modulation method includes a phase modulation method that modulates in the phase direction of a carrier wave and a quadrature amplitude modulation (Quad amplitude modulation) that modulates in both the phase and amplitude directions.
rature Amplitude Modulation: hereinafter abbreviated as QAM. ) There is a method. Further, in the phase modulation method, binary phase shift keying (Binary Phase Shi
ft Keying: Abbreviated as BPSK. ) Quadrature Phase Shift Keying:
Abbreviated as QPSK. ), 8 phase shift keying (8 Phas
e Shift Keying: hereinafter abbreviated as 8PSK. ) Has been put to practical use.

A frame as a transmission unit of communication data subjected to such digital modulation is obtained by dividing digitized communication data by a predetermined fixed communication amount.
When transmitting frames as communication data, a frame synchronization signal pattern is added to the beginning of each frame. As the frame communication data, communication data divided into the frame synchronization signal pattern and the fixed number is cyclically transmitted.

[0004] The frame synchronization signal pattern is used to identify the head of a frame, which is a data delimiter, from a received data sequence after performing quadrature demodulation, frequency phase reproduction, clock reproduction, and the like on the receiving side. And
It becomes a time series reference for performing subsequent data processing. Therefore, the receiving side cannot demodulate the received data unless the frame synchronization signal pattern can be accurately identified from the received digital data. Normally, as a frame synchronization signal pattern, a unique word (Unique Word) which is a fixed bit pattern of about 16 to 20 bits having the lowest appearance probability with respect to framed communication data.
d: Hereinafter, abbreviated as UW. ) Is selected. This UW is
The bit pattern and bit length are determined in advance on both the transmitting and receiving sides.

FIG. 7 shows an outline of the configuration of such framed communication data. That is, one frame data 5 having a fixed number of predetermined "n + k" (n and k are natural numbers) bits is composed of an n-bit UW 6 and k-bit various data 7 to be communicated. Such one frame data is transmitted continuously in time. Therefore, the position of the communication data can be recognized by detecting the UW which is the head of one frame data,
Transmission and reception of communication data can be performed.

The detection of the frame synchronization signal pattern as described above is performed by a frame synchronization circuit in a receiving device or a receiver.

FIG. 8 shows an outline of the configuration of a conventionally proposed frame synchronization circuit. In this frame synchronization circuit, a reception signal 11 is input from an input terminal 10 to a demodulation circuit 1
2 has been entered. The demodulation circuit 12 performs frequency phase reproduction and clock reproduction from the input received signal 11, and the clock signal 13 and the demodulation circuit output signal 14 are reproduced. Although not shown, the clock signal 13 is supplied from the clock output terminal 15 to all the functional units shown in FIG. Therefore, all the functional units shown in FIG. 8 perform various operations in synchronization with the clock signal 13. On the other hand, the demodulation circuit output signal 14 is input to the comparison circuit 16 and the signal processing circuit 17. The comparison circuit 16 also receives a predetermined plurality of bits of UW 19 which is a frame synchronization signal pattern from the frame synchronization signal generation circuit 18. Then, each time the demodulation circuit output signal 14 is input from the demodulation circuit 12, the signals are sequentially compared in synchronization with the clock signal 13 reproduced by the demodulation circuit 12. Such a comparison circuit 16
Is an arithmetic circuit that performs an exclusive OR operation for each bit of the UW 19, which is a frame synchronization signal pattern, and the demodulation circuit output signal 14. A multi-bit comparison circuit output signal 20 indicating the comparison result is input to the determination circuit 21. The determination circuit 21 receives the comparison circuit output signal 20
Are all "0", it means that the UW 19 which is the frame synchronization signal pattern and the respective bits of the demodulation circuit output signal 14 completely match. The result is output to the synchronization protection circuit 23 as the determination circuit output signal 22.

In the asynchronous state, the synchronization protection circuit 23 cannot obtain a matching result of the determination circuit output signals 22 continuously for a predetermined number of frames with reference to the determination circuit output signal 22 input from the determination circuit 21. As long as frame synchronization is established, it is not determined. This avoids erroneous synchronization.

On the other hand, in the synchronous state, the synchronous protection circuit 23
Is a decision circuit output signal 22 inputted from the decision circuit 21
, It is not determined that frame synchronization has been lost unless a mismatch result of the determination circuit output signal 22 is obtained continuously for a predetermined number of frames. As a result, loss of synchronization does not frequently occur.

As described above, the synchronous protection circuit 23 outputs the judgment circuit output signal 22 in the synchronous state or the asynchronous state.
Are output to the synchronization establishing circuit 25 for detecting and judging that the same result is obtained continuously for a predetermined number of times. The synchronization establishing circuit 25 generates a synchronization state display signal 26 according to the synchronization protection signal 24. This synchronization state display signal 26 indicates that synchronization has been established or synchronization has been lost. The synchronization state display signal 26 is notified from the synchronization state output terminal 27 to each unit of the device, and also to the synchronization protection circuit 23. The synchronization protection circuit 23 outputs the synchronization state indication signal 2
6, one of a rearward protection operation and a frontward protection operation is performed. Further, the synchronization establishing circuit 25 outputs a synchronization frame pulse 28 to the signal processing circuit 17 according to the synchronization protection signal 24.

The signal processing circuit 17 performs signal processing such as error correction processing and deinterleaving for rearranging the signals in a fixed order on the demodulation circuit output signal 14 in synchronization with the frame synchronization pulse 28. The signal processing circuit 17 generates an output signal 29 as a result of the signal processing, and
Is output to each part of the apparatus.

FIG. 9 shows timing waveforms of received data, a clock signal, and a frame synchronization pulse in the frame synchronization circuit shown in FIG. 9 (a) shows the signal waveform of the demodulation circuit output signal 14, FIG. 9 (b) shows the signal waveform of the clock signal 13, and FIG. 9 (c) shows the signal waveform of the frame synchronization pulse 28. The axes are represented as signal levels. The demodulation circuit 12 performs frequency phase reproduction and clock reproduction from the received signal 11 as described above, and outputs the clock signal 13 and the demodulation circuit output signal 14.
Is played. The reproduced clock signal 13 and demodulated circuit output signal 14 are shown in FIG.
They are output in synchronization as shown in FIG. However, when the received signal 11 is initially input to the demodulation circuit 12, the comparison circuit 16 does not detect a match with the UW 19, which is the frame synchronization signal pattern from the frame synchronization signal generation circuit 18. Therefore, the frame synchronization pulse 28 is not output, and the signal processing circuit 17 cannot identify the head of the frame, which is the data delimiter.

When the synchronization protection circuit 23 detects the coincidence with the UW 19 by a predetermined number of frames by the backward protection operation, the synchronization protection circuit 23 enters a synchronization state, and a frame synchronization pulse 28 from the synchronization establishment circuit 25 is shown in FIG. Output at the timing. That is, the frame synchronization pulse 28
If the demodulation data A portion of the demodulation circuit output signal 14 is, for example, the top bit portion of the frame synchronization signal pattern, the demodulation data A is supplied to the signal processing circuit 17 in synchronization with the timing of the demodulation data A. The signal processing circuit 17 can recognize a predetermined position in a frame, such as a frame data delimiter, and can perform the frame data processing as described above. In each unit, various operations are performed in a state where synchronization is achieved for each clock of the reproduced clock signal 13.

As described above, in the frame synchronization circuit shown in FIG. 8, the comparison circuit 16 and the determination circuit 21 detect the coincidence between the UW 19 which is the frame synchronization signal pattern generated by the frame synchronization signal generation circuit 18 and the demodulated signal. I have. Then, based on the detection result of the UW which is the frame synchronization signal pattern, the synchronization protection circuit 23 performs a backward protection operation or a forward protection operation so as to avoid erroneous synchronization or unnecessary loss of synchronization.

In the above-described frame synchronization circuit, since the frame synchronization is detected by a perfect match with the UW which is the frame synchronization signal pattern, when the reception level of the reception signal 11 is low depending on the state of the reception line which is the transmission line, etc. Often, frame synchronization is not detected.
In order to avoid such a situation, it is common practice to allow a detection error in a range of the number of error-permitted bits of about several bits when detecting coincidence with UW.

For example, Japanese Unexamined Patent Publication (Kokai) No. 3-184439 discloses a "unique word detection system", which discloses an allowable error bit number for detecting a UW calculated from a measured line error rate of a received signal, a predetermined UW and a reception UW. There is disclosed a technology relating to a frame synchronization circuit that detects UW from the number of error bits counted by comparison with a signal.

Also, for example, in Japanese Unexamined Patent Publication No. Hei 7-336345, "Portable Radio Communication Terminal Device", an arbitrary number of allowable bits is set for a UW detection circuit, and the number of bits is estimated from UW detection positions in all frames. There is disclosed a technology related to a frame synchronization circuit in which a UW detection window is provided at a position to avoid erroneous detection of UW even when the number of error bits of UW detection exceeds 1 bit.

Further, when the UW has not been detected yet, such as when the power of the system is turned on, the number of allowable error bits is reduced in order to detect the UW as accurately as possible. By doing so, frame synchronization is appropriately established according to the state of the system. Further, a line quality monitoring circuit for monitoring a line state of a reception line, which is a transmission path of a reception signal, is provided, and frame synchronization is established in real time by the allowable error bit number determined with reference to the monitoring result. Efficient frame synchronization can be established. The technology relating to such a frame synchronization circuit is disclosed in, for example,
This is disclosed in Japanese Patent Publication No. 2 “Synchronous word detection method”.

Further, for example, Japanese Patent Application Laid-Open No. 7-2548
Japanese Patent Publication No. 88, “Frame Synchronization Determination Method and Frame Synchronization Determination Apparatus” compares a predetermined number of bits of received data with UW, sets a coincidence occurrence point as a reference time position, and sets the same time corresponding to this reference time position. A technique relating to a frame synchronization circuit that establishes frame synchronization when a condition that pattern matching continuously occurs over a predetermined number of backward protection stages at a position is first disclosed. This frame synchronization circuit establishes frame synchronization even at a position different from the time position where the UW should exist in the burst data, and can quickly and effectively receive data.

Further, for example, see Japanese Patent Application Laid-Open No. Hei 9-116483.
In the publication "wireless communication system", when the number of allowed bits is set in accordance with the data error rate or the received electric field strength in the time zone at the time of UW detection, even if the received electric field strength and interference change. A technology related to a frame synchronization circuit that appropriately detects UW and establishes optimal frame synchronization is disclosed.

Further, for example, Japanese Patent Application Laid-Open No. 10-15043
No. 9, “frame synchronization circuit and communication system” is provided with a likelihood calculation circuit, calculates a Hamming distance between UW and a received data sequence, and determines a likelihood data addition value by a threshold value determination circuit. A technique related to a frame synchronization circuit that suppresses an increase in redundancy required for frame synchronization and avoids loss of synchronization or erroneous synchronization is disclosed.

[0022]

First, in the conventional frame synchronization circuit shown in FIG. 8, the bit error rate in a low C / N (carrier power-to-noise power ratio) environment is low in a reception line which is a transmission path of a reception signal. Due to the increase, there is a problem that it is difficult to capture the frame synchronization in the complete match detection with the UW. On the other hand, in the technique disclosed in Japanese Patent Application Laid-Open No. Hei 3-184439, a match with UW is detected using the allowable error bit number calculated from the measured line error rate of the received signal. Similarly to the technique disclosed in Japanese Patent Application Laid-Open No. 7-336345 having a UW detection window, even if a predetermined error rate allowable bit number is carelessly set depending on the line state, the error synchronization There is a problem that becomes high.

Japanese Patent Laid-Open Publication No. 1-256232 discloses a system in which a search mode and a narrow mode are provided, and when a match with UW is detected, only the number of allowable bits corresponding to the line state of the receiving line is permitted. In the technology, as the number of allowable error bits is variable depending on the state of the line that is the transmission path of the received signal, depending on the setting of the number of bits, false synchronization detection or loss of synchronization may occur unnecessarily, resulting in an optimal synchronization detection state. It is very difficult to keep. Further, since the hardware configuration is made variable by the hardware information stored in the memory according to the line quality, there is a problem that the circuit becomes large in size. Furthermore, the technique disclosed in Japanese Patent Application Laid-Open No. 10-150439 also has a problem in that the processing load and the size of the circuit are reduced.

According to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-254888, it is determined whether or not a condition for continuously generating pattern matching over a predetermined number of rear protection stages at the same time position corresponding to the reference time position is satisfied. Must be determined one by one, and the processing load increases. Therefore, as the reception signal is received at a higher speed, the processing load becomes a burden and the speed cannot be increased,
There is a problem that a buffer memory or the like is required to cope with the processing load, and the circuit becomes large.

Further, according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 9-116483, even if an attempt is made to set the number of allowable bits in accordance with the data error rate in the time zone or the received field strength, the frame synchronization is not performed in the error correction processing. There is a problem that it cannot be applied to a system performed after the establishment. Also, even when the allowable number of error bits is set according to the received electric field strength, there is a case where the received electric field strength changes little like a satellite channel transmission line, and only the C / N mainly changes. Have difficulty.

Further, a digital phase modulation system and QA
In the M system, in each case, the smaller the signal point distance, that is, the more polyphase modulation that increases the transmission capacity, the higher the bit error rate due to the influence of noise.
The required C / N increases. However, in the various frame synchronization circuits proposed in the related art described above, the number of allowable mismatch bits for detecting frame synchronization is not fixed, and the number of allowable errors is set according to a change in the environment of the transmission path. Is required C / N depending on the type of digital modulation.
Can't respond to changes. In particular, there is a problem that it is not possible to cope with hierarchical modulation transmission employing a plurality of modulation schemes.

It is an object of the present invention to provide a frame synchronization circuit which has a simple configuration and can efficiently establish frame synchronization.

Another object of the present invention is to provide a simple configuration,
It is another object of the present invention to provide a frame synchronization circuit that efficiently establishes frame synchronization and supports hierarchical modulation transmission employing a plurality of modulation schemes.

[0029]

According to the first aspect of the present invention, there are provided: (a) demodulation means for demodulating received data and a clock signal from a modulated received signal; and (b) predetermined in synchronization with a clock signal. Comparing means for comparing the received data with the frame synchronization pattern on a bit-by-bit basis; and (c) determining whether or not frame synchronization has been detected from the comparison result of the comparing means with reference to a predetermined number of allowable bits. Means; (d) synchronization protection means for determining frame synchronization or asynchronous when the determination result of the determination means is the same for a predetermined number of consecutive frames; and (e) synchronization status determined by the synchronization protection means. The frame synchronization circuit is provided with error allowable number setting means for setting the error allowable bit number according to the asynchronous state.

That is, according to the first aspect of the present invention, the received data and the clock signal are demodulated from the received signal modulated by the demodulation means. Then, the comparing means compares the predetermined frame synchronization pattern with the demodulated received data in synchronization with the demodulated clock signal. The determining means determines whether or not frame comparison has been detected by referring to the comparison result with a predetermined error allowable bit number. In the synchronization protection means, when the same result is obtained continuously for a predetermined number of frames by the determination means, frame synchronization or frame asynchronousness is determined. Then, the allowable error number setting means sets the allowable number of error bits used in the determination by the determining means according to the result of the determination.

According to the second aspect of the present invention, (a) demodulating means for demodulating received data and a clock signal from the modulated received signal, and (b) receiving a predetermined frame synchronization pattern in synchronization with the clock signal and receiving the data. (C) whether frame synchronization is detected based on whether or not the comparison result of the comparison means indicates that the number of bits excluding the number of error-permissible bits is equal to each other. (E) synchronization protection means for determining that the frame is not synchronized when the determination means determines that frame synchronization is not to be detected continuously for a predetermined number of frames; The frame synchronization circuit is provided with error allowable number setting means for increasing the number of error allowable bits each time the synchronous protection means determines that the state is asynchronous.

That is, according to the second aspect of the present invention, the received data and the clock signal are demodulated from the received signal modulated by the demodulation means. The comparison means compares a predetermined frame synchronization pattern and the demodulated received data bit by bit in synchronization with the demodulated clock signal. The determination means determines whether or not frame synchronization has been detected based on whether or not the comparison result indicates that the number of bits excluding the number of error-permitted bits indicates a match. In the synchronization protection unit, when the determination unit determines that the frame synchronization is not detected continuously for a predetermined number of frames, it is determined that the frame is out of synchronization. Then, each time it is determined that the frame is in the asynchronous state, the number of error allowable bits of the determination means is increased.

According to the third aspect of the present invention, (a) demodulating means for demodulating received data and a clock signal from a hierarchically modulated received signal and detecting synchronization for each modulation method in the hierarchical modulation; Comparison means for comparing the received data with a predetermined frame synchronization pattern in synchronization with a signal for each bit; (c) error tolerance according to the synchronization state for each modulation scheme in the hierarchical modulation detected by the demodulation means Determining means for changing the number of bits and determining whether or not frame synchronization has been detected based on whether or not the comparison result of the comparing means indicates that the number of bits is the same as the number of bits excluding the number of error-permitted bits; (D) Synchronization for determining that a frame is not synchronized when it is determined that frame synchronization is not detected by the determination means for a predetermined number of consecutive frames. Means Mamoru, (e) is provided and an error allowable number setting means for increasing the number of allowable error bits each time it is determined that the asynchronous state by the synchronization protection means to the frame synchronization circuit.

That is, according to the third aspect of the present invention, the received data and the clock signal are demodulated from the received signal hierarchically modulated by the demodulation means, and the synchronization state is detected for each modulation method in the hierarchical modulation. . Then, the comparing means compares the predetermined frame synchronization pattern with the demodulated received data bit by bit in synchronization with the demodulated clock signal. Further, in the determination means,
The number of allowed bits is changed according to the synchronization state of each modulation scheme in the hierarchical modulation detected by the demodulation means. Further, whether or not frame synchronization has been detected is determined based on whether or not the comparison result of the comparing means indicates that the number of bits excluding the number of error-permitted bits matches. In the synchronization protection unit, when the determination unit determines that the frame synchronization is not detected continuously for a predetermined number of frames, it is determined that the frame is out of synchronization. Then, each time it is determined that the frame is in the asynchronous state, the number of error allowable bits of the determination means is increased.

According to a fourth aspect of the present invention, in the frame synchronization circuit of the first to third aspects, the determination means determines that the comparison result of the comparison means at the time of a predetermined reset input indicates that all bits match. It is determined that the frame synchronization is detected only when the frame synchronization is detected.

In other words, according to the fourth aspect of the present invention, when a predetermined reset is input to the determination means, frame synchronization is detected only when it is determined that all bits of the comparison result of the comparison means match. The decision is made. Therefore, by inputting a predetermined reset, only a perfect match between the demodulated received data and the frame synchronization pattern can be determined as the frame synchronization pattern. That is, it is possible to easily avoid the occurrence of false synchronization by inputting a reset to a state where the possibility of false synchronization is high, such as when the power of the receiving device or the receiver is turned on or when the receiving channel is switched. Will be able to

According to a fifth aspect of the present invention, in the frame synchronization circuit according to the first to third aspects, when the frame synchronization is determined by the synchronization protection means, the number of error tolerable bits is set to a predetermined maximum value. It is characterized by doing.

That is, according to the fifth aspect of the present invention, when frame synchronization is determined by the synchronization protection means, the number of allowable error bits is set to a predetermined maximum value. As a result, some acceptable reception errors can be compensated for by error correction processing.
Once the frame synchronization has been detected, it is possible to prevent the occurrence of frame synchronization loss frequently and to provide an efficient frame synchronization circuit.

According to a sixth aspect of the present invention, in the frame synchronization circuit according to the second or third aspect, the error allowable number setting means determines that the number of error allowable bits to be increased does not exceed a predetermined upper limit value. Features.

In other words, in the invention according to claim 6, the error allowable number setting means prevents the number of error allowable bits to be increased from exceeding a predetermined upper limit value. This makes it possible to provide an efficient frame synchronization circuit by preventing erroneous synchronization from occurring frequently.

According to a seventh aspect of the present invention, in the frame synchronization circuit according to the third aspect, the demodulation means detects whether or not synchronization is performed in the order of a modulation scheme having a higher required carrier power ratio to noise power ratio. Features.

That is, according to the seventh aspect of the invention, the demodulation means detects the synchronization state in the order of the modulation scheme having the higher required carrier power ratio to noise power ratio.
Hierarchical modulation such as SK, QPSK, 8PSK, etc., in which the transmission capacity is large but the error rate is large due to the small inter-signal distance, and the modulation scheme where the transmission capacity is small but the inter-signal distance is large, so the error rate is small. Modulation system and mixed
Even if the required carrier power ratio to noise power ratio differs depending on the modulation scheme, the allowable number of error bits can be set appropriately, so that a very efficient frame synchronization circuit in hierarchical modulation transmission can be provided. Become.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

First Embodiment

FIG. 1 shows the outline of the configuration of the frame synchronization circuit according to the first embodiment of the present invention. However, the same parts as those of the conventional frame synchronization circuit shown in FIG. In the frame synchronization circuit according to the first embodiment, a reception signal 11 is input from an input terminal 10 to a demodulation circuit 12. The demodulation circuit 12 performs frequency phase reproduction and clock reproduction from the input received signal 11, and reproduces the clock signal 13 and the demodulation circuit output signal 14. Although not shown, the clock signal 13 is supplied from the clock output terminal 15 to all the functional units shown in FIG. Therefore, all the functions shown in FIG. 1 perform various operations in synchronization with the clock signal 13.
On the other hand, the demodulation circuit output signal 14 is input to the comparison circuit 16 and the signal processing circuit 17. The comparison circuit 16 includes:
A predetermined plurality of bits of UW 19 which is a frame synchronization signal pattern is also input from the frame synchronization signal generation circuit 18. The comparison circuit 16 receives the clock signal 1
For each one of the three clocks, the signal is sequentially compared with the demodulation circuit output signal 14 from the demodulation circuit 12. Such a comparison circuit 16
Is an arithmetic circuit that performs an exclusive OR operation for each bit of the UW 19, which is a frame synchronization signal pattern, and the demodulation circuit output signal 14. The comparison circuit output signal 20 of a plurality of bits indicating the comparison result is input to the determination circuit 40. The comparison circuit output signal 20 input to the determination circuit 40 indicates that the bit whose bit data is “0”
And the bit whose bit data is “1” is UW1
9 and 9 are not matched.

The decision circuit 40 sets an error allowable bit number according to an allowable bit number setting signal 42 from an allowable number setting circuit 41. This determination circuit 40
Referring to the number of error tolerable bits set by error tolerable bit setting signal 42, input comparator circuit output signal 20
And UW19 are determined to be coincident. Specifically, the judgment circuit 4
A value of 0 determines that the UW 19 matches the demodulation circuit output signal 14 as long as the number of bits whose bit data is "1" out of all bits of the comparison circuit output signal 20 does not exceed the number of error-permitted bits. . Determination circuit 4 for performing such determination
From 0, a determination circuit output signal 43 indicating the determination result is supplied to the synchronization protection circuit 23.

FIG. 2 shows an outline of a main part of the configuration of the synchronization protection circuit 23. The synchronization protection circuit 23 includes a front protection synchronization circuit 44, a rear protection synchronization circuit 45, and a selection circuit 46. The forward protection synchronizing circuit 44 and the rear protection synchronizing circuit 45 respectively include a determination circuit output signal 43 output from the determination circuit 40 and a clock signal 13.
Is entered. The forward protection synchronization circuit 44 performs a forward protection operation on the input determination circuit output signal 43 in synchronization with the clock signal 13 reproduced by the demodulation circuit 12. That is, when the determination circuit output signal 43 determines that the UW 19 and the demodulation circuit output signal 14 do not match each other for a predetermined number of frames, the forward protection synchronization circuit 44 indicates that forward synchronization has been lost. A synchronization signal 47 is generated. As a result, loss of synchronization does not frequently occur. The predetermined number of consecutive frames in this case is referred to as “forward protection count”.

On the other hand, the rear protection synchronizing circuit 45 performs a rear protection operation on the input judgment circuit output signal 43 in synchronization with the clock signal 13 reproduced by the demodulation circuit 12. That is, when the determination circuit output signal 43 determines that the UW 19 matches the demodulation circuit output signal 14 for a predetermined number of frames, the backward protection synchronization circuit 45 indicates that frame synchronization has been established. A protection synchronization signal 48 is generated. Thereby, erroneous synchronization is avoided. The predetermined number of consecutive frames in this case is referred to as “backward protection number”.

The front protection synchronization signal 47 and the rear protection synchronization signal 48 thus generated are input to the selection circuit 46. The selection circuit 40 outputs the synchronization state display signal 2 generated by the synchronization establishment circuit 25 among the output signals of the front protection synchronization circuit 44 and the rear protection synchronization circuit 45.
6, one of them is selected. Specifically, when the synchronization state indication signal 26 indicates the detection of the frame synchronization signal pattern, that is, when the synchronization state is established, the forward protection synchronization signal 47 is selected. On the other hand, when the synchronization state indication signal 26 indicates a state in which the frame synchronization signal pattern is not detected, that is, when the state is asynchronous, the backward protection synchronization signal 48 is selected. The protection synchronization signal that is selectively selected as the synchronization signal for the front protection or the rear protection is supplied to the synchronization establishing circuit 25 as the synchronization protection signal 24.

Returning to FIG. 1, the description will be continued.

The synchronization establishing circuit 25 supplies the synchronization protection signal 24 as it is to the synchronization protection circuit 23 as a synchronization status indication signal 26 from the synchronization status output terminal 27 to each unit of the device. This synchronization state display signal 26
Indicates that synchronization has been established or synchronization has been lost. As described above, with reference to the synchronization state display signal 26, the synchronization protection circuit 2
3 performs one of the rearward protection operation and the frontward protection operation. Further, the synchronization establishing circuit 25 outputs a synchronization frame pulse 28 to the signal processing circuit 17 according to the synchronization protection signal 24.

The signal processing circuit 17 performs error correction processing and signal processing such as deinterleaving for rearranging the signals in a fixed order on the demodulation circuit output signal 14 in synchronization with the frame synchronization pulse 28. An output signal 29 as a result of such signal processing is output from the signal processing circuit 17 and supplied from an output terminal 30 to each unit of the device.

Incidentally, the synchronization state display signal 26 generated by the synchronization establishment circuit 25 is also supplied to the count circuit 49. The counter circuit 49 includes a demodulation circuit 1
In synchronization with the clock signal 13 reproduced by 2, one or more than one value can be counted up according to the synchronization state display signal 26.
On the other hand, the count-up circuit 49 is configured such that when the synchronous state display signal 26 is equal to or more than a predetermined number of frames and the asynchronous state continues, the count value does not exceed a predetermined upper limit. For example, when the UW 19 as the frame synchronization signal pattern is 20 bits, the number of allowable mismatch bits is set to a maximum of 5 bits.

The count value is calculated by the count circuit 4
9 is supplied to the allowable number setting circuit 41 as a count circuit output signal 50. The allowable number setting circuit 41 outputs the allowable bit number setting signal 4
2 is output, and the number of allowable bits is set by the decision circuit 40. That is, when the synchronous state display signal 26 indicates that the state is asynchronous, the number of error-permitted bits counted up by one or more than one value in the count circuit 49 is set in the determination circuit 40. Thus, frame synchronization can be efficiently established. Further, the count circuit 49 and the permissible number setting circuit 41 are reset by a reset signal input (not shown) when the power supply of the receiving device is turned on or the receiving channel is switched.

Next, the operation in the case where the receiving apparatus or the receiver is provided with the frame synchronization circuit having such a configuration will be described.

First, when the power of the receiving device or the receiver is turned on or when the receiving channel is switched, the counting circuit 49 is used.
And the allowable number setting circuit 41 is reset by a reset input (not shown). Reset count circuit 4
In 9 and the allowable number setting circuit 41, the count value is “
0 ", and the error allowable bit number setting signal 42 becomes" 0 ".
As a result, in the determination circuit 40, the comparison circuit 16 uses the UW1
9 when performing frame synchronization detection by comparing with
The number of allowable bits is set to “0”. Therefore, the judgment circuit 40 determines whether the demodulation circuit output signal 14
It is determined whether or not it is a perfect match with W19.

When the determination circuit 40 determines that the patterns completely match, it is determined that a frame synchronization signal pattern has been detected.
Frame synchronization is established by the synchronization protection operation by the synchronization protection circuits 23 and 25. Therefore, the synchronization state display signal 26 indicates the synchronization state, and does not increment the count value of the count circuit 49. On the other hand, even if the determination circuit 40 determines that the two are completely matched, frame synchronization may not be established due to the synchronization protection operation by the synchronization protection circuits 23 and 25.
In such a case, the count value of the counting circuit 49 is incremented by one or a plurality of values when the state continues for a predetermined number of frames by referring to the synchronous state display signal 26 indicating the asynchronous state. Then, at the time of determination by the determination circuit 40, frame synchronization is detected by allowing errors by the set number of error allowable bits. Further, every time the asynchronous state is detected for a predetermined number of frames, the count value of the count circuit 49 is counted up by one or more than one. Thereby, the judgment circuit 40
Increases the allowable number of error bits, making it easier to detect frame synchronization.

However, since the asynchronous state is detected for the predetermined number of frames, the counting circuit 49
The count value counted up by is not to exceed a predetermined upper limit value as described above. Therefore, even if UW1 as a frame synchronization signal pattern
When 9 is 20 bits, it is possible to prevent counting up to a value equal to or greater than a predetermined maximum number of code mismatches, such as setting the maximum number of mismatch bits to 5 bits at maximum, so that erroneous synchronization can be avoided. .

As described above, the frame synchronization circuit in the first embodiment generates the demodulation circuit output signal 14 reproduced by the demodulation circuit 12 together with the clock signal 13 by the frame synchronization signal generation circuit 18. The signal pattern UW19 and the clock signal 13
And the comparison circuit 16 sequentially compares them in synchronization with each other. The comparison result of the comparison circuit 16 is determined by the determination circuit 40. The determination circuit 40 can determine the number of code matches and the number of code mismatches with the UW 19 under variable determination conditions according to the allowable bit number setting signal 42 supplied from the allowable number setting circuit 41. The determination circuit output signal 43 determined and output as described above is generated by the synchronization protection circuit and the synchronization establishment circuit 25 based on whether or not the determination result is continuously the same for a predetermined number of frames continuously. A synchronization state indication signal 26 indicating the establishment or loss of synchronization of the frame synchronization is output. This synchronization state display signal 26 is supplied to the count circuit 49. The count circuit 49 generates an allowable bit number setting signal 42 supplied from the allowable number setting circuit 41 by counting up in the count circuit 49 in accordance with the frame synchronization state. Thereby, the UW 19 when detecting the frame synchronization is detected according to the frequency of the frame synchronization detection.
, The number of code matches and the number of code mismatches can be adaptively changed to provide a frame synchronization circuit that enables an efficient frame synchronization operation.

Second Embodiment

In the frame synchronization circuit according to the first embodiment, the count circuit 49 and the allowable number setting circuit 41 are made into functional blocks to perform a reset operation or the like so as to efficiently detect the frame synchronization. It is also possible to provide these and process these operations by software.

FIG. 3 shows an outline of the configuration of the frame synchronization circuit in the second embodiment. However, FIG.
The same parts as those of the frame synchronization circuit in the first embodiment shown in FIG. A first point different from the frame synchronization circuit in the first embodiment is that
The point is that the control circuit 51 is provided. This control circuit 51
Is a central processing unit (Central Processing Uni
t: Hereinafter, abbreviated as CPU. ) And memory,
CPU according to the program stored in this memory
Performs the processing, and the processing in-process result and the processing result are appropriately stored in the memory. Further, a second point different from the frame synchronization circuit in the first embodiment is that the judgment circuit output signal 43 output from the judgment circuit 40 is input to the synchronization protection circuit 52. The control circuit 51 includes a clock signal 13 and a synchronization state display signal 26, and a synchronization protection circuit 52.
, A synchronization determination signal 53 is input. The synchronization determination signal 53 can notify various determination results.
The control circuit 51 generates an allowable bit number setting signal 42 from the synchronization state display signal 26 and the synchronization determination signal 53 in synchronization with the clock signal 13 and supplies the signal 42 to the determination circuit 40.

FIG. 4 shows a control circuit 51 according to the second embodiment.
3 shows an outline of the processing contents. This process
This is performed every time the power of the apparatus is turned on or the reception channel is switched. First, when the power-on of the apparatus or the switching of the reception channel is notified by a signal notification line (not shown), the control circuit 51 sets the number of allowable bits to “0” to the determination circuit 40 and sets the UW 19 Is determined (step S60). And
The judgment circuit 40 outputs the demodulation circuit output signal 14 and the UW 19
Is output, the synchronization protection circuit 52 outputs a clock signal 1 (not shown).
In step S60, it is determined whether or not a complete match is made continuously for a predetermined number of frames (step S60: Y, step S61). If it is not determined that a complete match has been made for a predetermined number of frames (step S61: N), the process returns to step S60. On the other hand, when it is determined that there is a complete match for a predetermined number of frames (step S61: Y),
The synchronization establishment circuit 25 outputs the synchronization state display signal 26 indicating that the frame synchronization has been established via the synchronization protection signal 54 (step S62). Next, the control circuit 51 that has been notified of this from the synchronization protection circuit 52 via the synchronization determination signal 53 sets the allowable number of bits to the predetermined maximum value for the determination circuit 40 (step S63). . That is, once the synchronization is established with perfect match, the synchronization state is maintained as much as possible.

Thereafter, the decision circuit 40 is sequentially compared with the UW 19 for each clock of the clock signal 13 with reference to the number of allowable bits set in step S63 (step S64). This state is repeated as long as the comparison with the UW 19 matches with reference to the set error allowable bit number in the judgment circuit 40 (step S64:
Y). On the other hand, in step S64, the determination circuit 40 determines that the comparison with the UW 19 does not match by referring to the set number of allowed bits (step S64: N). It is determined whether or not the number of times is continuous (step S65). Then, in step S65, when the mismatch is not determined continuously for the predetermined number of times (step S65: N), the process returns to step S64.
On the other hand, when it is determined in step S65 that there is no match a predetermined number of times (step S65: Y), it is detected that frame synchronization has been lost, and the synchronization state display signal 26 is output (step S66). Then, the process returns to step S60 again (return).

Incidentally, step S60 immediately after the start
If it is not determined that the data matches the UW 19 completely (step S60: N), the synchronization protection circuit 52 is caused to determine whether or not this is repeated a predetermined number of times (step S67). When the predetermined number of times is not consecutive (step S67: N),
It returns to step S60 again. On the other hand, when the predetermined number of consecutive times (step S67: Y), the control circuit 5
1 is notified through the synchronization determination signal 53, and the number of error-permitted bits to be set in the determination circuit 40 is set by counting up by one or more than one value (step S68). Then, the determination circuit 40 again determines the match with the UW 19 (step S69). Step S69
Is determined to match the UW19 (step S69:
Y), when this is repeated a predetermined number of times (step S70:
In Y), the process returns to step S62 to generate the synchronization state display signal 26 assuming that frame synchronization has been established. When it does not match with UW19 in step S69 (step S69:
In N), it is determined whether or not this is repeated a predetermined number of times (step S71). When it is determined in step S71 that they do not match a predetermined number of times in a row (step S71:
Y), returning to step S68 to further increase the allowable bit number by 1
Alternatively, only one or more values are counted up (step S68). On the other hand, when it is determined in step S71 that there is no mismatch for a predetermined number of times (step S71:
In N), the flow returns to step S69 to again determine the coincidence with UW.

If it is determined in step S69 that the pattern matches the UW 19 (step S69: Y), and if this does not continue a predetermined number of times (step S70: N), the control circuit 5
It is determined whether or not 1 is the maximum number of error allowable bits set for the determination circuit 402 (step S72). If it is not the maximum value (step S72: N), step S6
Returning to 8, the allowable bit number is further counted up by one or more than one value (step S68). However, if the maximum value is obtained in step S72 (step S72:
Y), the process returns to step S69, and it is determined again whether or not it matches the UW19 (step S69).

As described above, the frame synchronization circuit according to the second embodiment can be implemented by software, in accordance with the frequency of frame synchronization detection, in accordance with the frequency of frame synchronization detection. And a frame synchronization circuit that enables an efficient frame synchronization operation.

Third Embodiment

In the frame synchronization circuits of the first and second embodiments, frame synchronization is efficiently established with respect to a predetermined modulation signal. However, in the frame synchronization circuit of the third embodiment, a received signal is BPSK, QPS
It is possible to efficiently establish frame synchronization even for a hierarchical modulation signal whose required C / N changes such as K and 8PSK.

FIG. 5 shows the outline of the configuration of the frame synchronization circuit in the third embodiment. However, FIG.
The same parts as those of the frame synchronization circuit in the first embodiment shown in FIG. The difference from the frame synchronization circuit in the first embodiment is a demodulation circuit 80 and a decision circuit 81, each of which is adapted to handle a hierarchical modulation signal. The demodulation circuit 80
A PSK synchronization signal 8 demodulated from a received signal modulated by SK, QPSK, and 8PSK and output according to the demodulation state.
2, the number of allowable bits in the determination circuit 81 can be changed.

FIG. 6 shows an outline of an example of the configuration of the demodulation circuit 80. In the demodulation circuit 80, the hierarchically modulated reception signal 11 is input to the quadrature demodulator 83. The quadrature demodulator 83 separates an in-phase component I-channel signal 84 and a quadrature component Q-channel signal 85 of a quadrature function suitable for information transmission efficiency. Then, each component of the separated orthogonal function is converted into a digital signal by the analog / digital converter 86 and input to the carrier phase correction circuit 87. Carrier phase correction circuit 87
Is a Numerically Controlled Oscillato
r: hereinafter abbreviated as NCO. ) The phase of each component is corrected based on the numerical value set from 88. Each component signal corrected by the carrier phase correction circuit 87 is input to a clock phase detector 89 and a carrier phase detector 90.

First, the clock phase detector 89 detects the phase of the clock signal to be reproduced from each of the input component signals and removes the higher harmonic component by the loop filter 91. Then, the voltage phase controlled oscillator (Voltage Controlled Oscillator: hereinafter) V
Abbreviated as CO. At 92, the clock signal 13 is reproduced according to the phase difference detected by the clock phase detector 89. V
The clock signal 13 reproduced by the CO 92 is also supplied to the A / D converter 86, and the A / D converter 86 digitizes each component signal of the orthogonal function at a timing synchronized with the clock signal 13. .

The carrier phase detector 90 detects the phase of the carrier wave from each of the input component signals, removes the higher harmonic components by the loop filter 93, and responds to the phase difference detected by the carrier phase detector 90 by the NCO 88. The corrected value is supplied to the carrier phase correction circuit 87.

Each component signal of the orthogonal function corrected by the carrier phase correction circuit 87 is serially converted by the bit string converter 94 and output as the demodulation circuit output signal 14. In the bit string serial converter 94, 1 is used as a modulation signal.
One symbol as a data unit that can be transmitted each time is converted into, for example, 2 bits for QPSK and 3 bits for 8PSK.

The carrier phase detector 90 has PSK
The synchronization signal generation circuit 95 is connected. The PSK synchronization signal generation circuit 95 can detect the lock state at each point of the I channel and the Q channel from the carrier phase difference detected by the carrier phase detector 90. That is, when two predetermined phase locked states are detected, BPSK synchronization is performed. When four predetermined phase locked states are detected, QPSK synchronization is performed.
8PSK when the phase lock state of predetermined 8 points is detected
Of the PSK synchronization signal 8
2 can be generated.

Returning to FIG. 5, the description will be continued.

The determination circuit 81 detects a phase lock state indicating that demodulation is possible in each modulation scheme of the received signal hierarchically modulated in this manner, and thereby determines a required C of each of these modulation schemes.
Even when / N is changed, an optimum error-permissible bit can be set according to the required C / N. That is, the highest required C / N in the demodulation circuit 80
When 8PSK, which is the modulation method of the above, is demodulatable and synchronized, the determination circuit 81 first determines that only a perfect match between the demodulation circuit output signal 14 and the UW 19 is frame synchronization by a PSK synchronization signal 82 indicating that. To However, the highest required C / N modulation scheme, 8PS
When K cannot be demodulated and is not synchronized, and QPSK, which is the next higher required C / N modulation scheme, can be demodulated and is synchronized, the determination circuit 81 uses a PSK synchronization signal 82 indicating that, and the predetermined circuit The frame synchronization is determined by allowing a number of error-permitted bits. Further, when QPSK, which is the second highest required C / N modulation scheme, cannot be demodulated and is not synchronized, and BPSK, which is the next highest required C / N modulation scheme, is demodulatable and is synchronized, The determination circuit 81 further increases the number of allowable bits in accordance with the PSK synchronization signal 82 indicating that, and determines the frame synchronization by allowing the number of allowable bits.

As described above, the frame synchronization circuit according to the third embodiment adaptively determines the allowable number of code mismatches in frame synchronization depending on whether the detection of the frame synchronization signal pattern is not detected for a predetermined number of frames or more. To increase the reliability of frame synchronization. If the digitally modulated received signal is a hierarchically modulated signal, the number of code mismatches is set when frame synchronization is determined according to the required C / N of each modulation scheme.

In the frame synchronization circuits according to the first to third embodiments, when frame synchronization is not established, the number of allowable bits for frame synchronization detection determination is increased.
In the frame synchronization circuit according to the second embodiment, when the frame synchronization is established, the number of allowable error bits is set to a predetermined maximum value. However, the present invention is not limited to this. For example, an efficient frame synchronization circuit can be provided even if the number of error allowable bits is adaptively increased or decreased according to whether frame synchronization detection determination is possible.

[0081]

As described above, according to the first aspect of the present invention, the number of error-permissible bits at the time of frame synchronization detection is determined adaptively depending on whether or not frame synchronization has been detected for a predetermined number of frames. By changing the allowable number of code mismatches, it is possible to avoid the difficulty of acquiring frame synchronization due to an increase in bit errors in a low C / N environment of the receiving line.

According to the second aspect of the present invention, each time it is detected that the frame synchronization has been lost, the number of code matches with the UW and the number of code mismatches when detecting frame synchronization are adaptively changed. Therefore, it is possible to provide a frame synchronization circuit that enables an efficient frame synchronization operation.

According to the third aspect of the present invention, the allowable number of code mismatches, which is the number of error-permissible bits in frame synchronization, is set according to the difference between the required carrier power ratio and the noise power ratio of each modulation scheme in hierarchical modulation. I decided to
It can also be applied to hierarchical modulation transmission employing a plurality of modulation schemes.

Further, according to the fourth aspect of the present invention, by inputting a predetermined reset, only a complete match between the demodulated received data and the frame synchronization pattern can be determined as a frame synchronization pattern. Therefore, it is possible to easily avoid the occurrence of false synchronization by inputting a reset to a state where the possibility of false synchronization is high, such as when the power of the receiving device or the receiver is turned on or when the receiving channel is switched. Will be able to

Further, according to the fifth aspect of the present invention,
When it is determined that the frame is synchronized by the synchronization protection means, the allowable number of error bits is set to a predetermined maximum value, so that some allowable reception errors can be compensated by error correction processing. After the frame synchronization is detected, the frame synchronization is not frequently lost, so that an efficient frame synchronization circuit can be provided.

Further, according to the present invention, the error allowable number setting means does not cause frequent erroneous synchronization by preventing the number of error allowable bits to be increased from exceeding a predetermined upper limit value. Therefore, an efficient frame synchronization circuit can be provided.

Further, according to the seventh aspect of the present invention, the synchronization state is detected in the order of the modulation scheme having the higher required carrier power ratio to noise power ratio.
Hierarchical modulation such as PSK, 8PSK, etc., in which the transmission rate is large but the error rate is large due to the small inter-signal distance, and the modulation scheme in which the transmission capacity is small but the error rate is small due to the large inter-signal distance Even if the required carrier power ratio to noise power ratio differs depending on the modulation method, the allowable number of error bits can be set appropriately, providing a highly efficient frame synchronization circuit in hierarchical modulation transmission. Will be able to

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a configuration of a frame synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an outline of a configuration of a synchronization protection circuit according to the first embodiment.

FIG. 3 is a block diagram illustrating an outline of a configuration of a frame synchronization circuit according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing processing contents of a control circuit of a frame synchronization circuit in the second embodiment.

FIG. 5 is a block diagram illustrating an outline of a configuration of a frame synchronization circuit according to a third embodiment of the present invention.

FIG. 6 is a block diagram illustrating an outline of a configuration of a demodulation circuit according to a third embodiment.

FIG. 7 is an explanatory diagram illustrating an outline of a configuration of framed communication data.

FIG. 8 is a block diagram showing an outline of the configuration of a conventionally proposed frame synchronization circuit.

FIG. 9 is a waveform diagram showing an outline of an operation waveform of a conventional frame synchronization circuit.

[Explanation of symbols]

 Reference Signs List 10 input terminal 11 reception signal 12, 80 demodulation circuit 13 clock signal 14 demodulation circuit output signal 15 clock output terminal 16 comparison circuit 18 frame synchronization signal generation circuit 19 UW 20 comparison circuit output signal 21, 40, 81 judgment circuit 22, 43 judgment Circuit output signal 23, 52 Synchronization protection circuit 24, 54 Synchronization protection signal 25 Synchronization establishing circuit 26 Synchronization state display signal 27 Synchronization state output terminal 28 Synchronous frame pulse 29 Output signal 30 Output terminal 41 Permissible number setting circuit 42 Permissible bit number setting signal 44 Forward protection synchronization circuit 45 Back protection synchronization circuit 46 Selection circuit 47 Forward protection synchronization signal 48 Back protection synchronization signal 49 Count circuit 50 Count circuit output signal 51 Control circuit 53 Synchronization determination signal

Claims (7)

[Claims] 1. A demodulating means for demodulating received data and a clock signal from a modulated received signal, and a comparing means for comparing a predetermined frame synchronization pattern and the received data bit by bit in synchronization with the clock signal Determining means for determining whether or not frame synchronization has been detected from the comparison result of the comparing means by referring to a predetermined number of allowable error bits; and determining that the determination result of the determining means is the same for a predetermined number of consecutive frames. Synchronous protection means for determining frame synchronization or non-synchronization, and error allowable number setting means for setting the number of error allowable bits according to the synchronous state or the asynchronous state determined by the synchronous protection means. Frame synchronization circuit. 2. A demodulator for demodulating received data and a clock signal from a modulated received signal, and comparing means for comparing a predetermined frame synchronization pattern in synchronization with the clock signal with the received data for each bit. Determining means for determining whether or not frame synchronization has been detected based on whether or not the comparison result of the comparing means indicates that there is a match by the number of bits excluding the number of error-permitted bits; and a predetermined number of frames. A synchronization protection means for determining that the frame is not synchronized when the frame synchronization is not detected by the determination means continuously; and A frame synchronization circuit, comprising: 3. A demodulator for demodulating received data and a clock signal from a hierarchically modulated received signal and detecting synchronization for each modulation scheme in the hierarchical modulation, and a frame synchronization predetermined in synchronization with the clock signal. Comparing means for comparing the pattern and the received data bit by bit, and changing the number of error tolerable bits according to the synchronization state for each modulation scheme in the hierarchical modulation detected by the demodulation means, and comparing the comparison result of the comparison means. Means for judging whether or not frame synchronization has been detected based on whether or not indicates that the number of bits is equal to the number of bits excluding the number of error-allowed bits. Synchronous protection means for determining that the frame is out of synchronization when it is determined that frame synchronization is not detected; Thus the frame synchronization circuit characterized by comprising a allowable error number setting means for the increasing the number of allowable error bits each time it is determined that the asynchronous state. 4. The apparatus according to claim 1, wherein said determination means determines that frame synchronization has been detected only when the comparison result of said comparison means determines that all bits match at a predetermined reset input. The frame synchronization circuit according to claim 1. 5. The apparatus according to claim 1, wherein the number of allowable bits is set to a predetermined maximum value when frame synchronization is determined by the synchronization protection means.
The frame synchronization circuit according to claim 3. 6. The frame synchronization circuit according to claim 2, wherein said error allowable number setting means does not increase the number of error allowable bits exceeding a predetermined upper limit. 7. The frame synchronization circuit according to claim 3, wherein said demodulation means detects whether or not synchronization is performed in the order of a modulation scheme having a higher required carrier power ratio to noise power ratio.