JP4653053B2 - Frame synchronization method and apparatus - Google Patents

Description

  The present invention relates to the reception of digital data organized in frames. In particular, it relates to frame synchronization of received data.

  In a digital transmission system, when a frame is configured and transmitted, it is necessary to establish frame synchronization on the receiving side. As this method, generally, a frame synchronization pattern is added to a transmission signal, and the frame synchronization device on the receiving side detects the pattern to generate a frame synchronization signal.

  FIG. 2 is a block diagram showing a conventional frame synchronization apparatus. In this conventional example, a synchronization pattern detection circuit 21 is provided, and when a frame synchronization pattern is detected from received data, the synchronization pattern detection timing is output as a frame synchronization signal.

Data processing including error correction and the like is executed based on this frame synchronization signal. Various modulation schemes are used to improve transmission efficiency as well as increase transmission speed and distance (see Patent Document 2).
JP 2001-177491 A JP 2000-174744 A JP 2000-324116 A JP-A-6-169297 JP-A-5-110555 Real Kaihei 5-85140

  In the optical transmission system, the sign of the detected optical signal may be inverted or other bits may be detected depending on the configuration of the optical transmission device or the optical reception device.

  As a specific example, when the optical signal format is a DPSK (Differential Phase Shift Keying) signal, the Mach-Zehnder interferor converts the DPSK signal into an intensity-modulated signal. Depending on the setting, the sign of all bits of the detected optical signal may be inverted. When the optical signal format is a DQPSK (Differential Quadrature PSK) signal, the receiver separates the optical signal into two signals, and detects the I component and Q component of the phase using a Mach-Zehnder interferometer. When detecting a component, depending on the setting of the Mach-Zehnder interferometer, the other component may be detected by mistake, or may be detected by inverting all bits.

  As described above, in a situation where data is inverted and detected or other bits are detected, even if the received data includes a frame synchronization pattern, frame synchronization cannot be performed and communication is started. I can't.

  The present invention solves such a problem and provides a frame synchronization method capable of detecting a frame synchronization pattern in a state in which bit inversion is detected by mistake or other bits are detected. With the goal.

  According to the first aspect of the present invention, even if there is a reception error assumed in the received frame synchronization pattern, the data conversion means for subjecting the received data to constant data conversion in which the frame synchronization pattern is converted into the same fixed pattern And a fixed pattern detecting means for detecting the fixed pattern from the output of the data converting means.

  The data conversion means divides the frame synchronization pattern into a plurality of groups each consisting of N bits, where N ≧ 1, and excludes M bits from two groups, where 1 ≦ M ≦ N. Means for determining a logical OR (XOR) can be included. Thereby, it is possible to cope with a reception error in which the logic of the Mth bit of the group is inverted.

  The data conversion means divides the frame synchronization pattern into a plurality of groups composed of N bits, where N ≧ 2, and two groups in which all the bits are the same or all the bits are inverted From the above, it is possible to include means for obtaining an exclusive OR of the values of the Mth bit, where 1 ≦ M ≦ N. Thereby, it is possible to cope with an error in which the logic of the Mth bit of the group is the same as the logic of other bits or the logic of other bits is inverted.

  When the assumed reception error is all-bit inversion, the data conversion means can include means for obtaining an exclusive OR between adjacent bits with respect to data of the number of bits of the frame synchronization pattern. .

When the received data is a signal obtained by demodulating a DQPSK modulated signal, the transmission data is An, Bn, An + 1, Bn + 1, An + 2, Bn + 2,... , A ⁻ , B, B ⁻ (A ⁻ and B ⁻ are logical inversions of A and B, respectively) are assumed to be received in 16 combinations. In this case, the data conversion means includes means for obtaining an exclusive OR between two adjacent bits of the frame synchronization pattern, each of which has the same logic and different logic. Good.

  If the received pattern at that time and the frame synchronization pattern do not match despite the detection of the fixed pattern by the fixed pattern detection means, the corresponding bits of the received data are inverted so that they match. Alternatively, it is desirable to provide bit inversion / replacement means for replacing the corresponding bits. The bit inversion / replacement means is configured to invert or replace corresponding bits of the received data in accordance with a reception error detected by frame processing of the received data in synchronization with the detection output of the fixed pattern detecting means. Is desirable.

According to a second aspect of the present invention, in a frame synchronization method for establishing a frame synchronization by detecting a predetermined frame synchronization pattern from received data,
Even if there is a reception error that is assumed in the received frame synchronization pattern, the received data is subjected to a constant data conversion in which the frame synchronization pattern is converted into the same fixed pattern. A frame synchronization method is provided that detects the fixed pattern.

  According to the present invention, frame synchronization can be reliably established even when a reception error occurs in the frame synchronization pattern.

  FIG. 1 is a block diagram showing a frame synchronization apparatus according to an embodiment of the present invention. This device is a data which performs a certain data conversion on received data in which the frame synchronization pattern is converted into the same fixed pattern (hereinafter referred to as “abbreviated pattern”) even if there is a reception error assumed in the received frame synchronization pattern. A conversion circuit 11 and a shortening pattern detection circuit 12 for detecting a shortening pattern from the output of the data conversion circuit 11, and the received data at that time, although the shortening pattern detection circuit 12 detects the shortening pattern, A bit inversion circuit 13 is provided for inverting the corresponding bit of the received data so that the frame synchronization pattern does not match when the frame synchronization pattern does not match.

  The bit inversion circuit 13 may perform bit inversion so that the received data when the shortening pattern detection circuit 12 detects the shortening pattern matches the frame synchronization pattern. However, it is necessary to store the corresponding received data until the shortened pattern is detected by the shortened pattern detection circuit 12, and it is necessary to compare it with the frame synchronization pattern, which complicates the circuit configuration. Therefore, it is desirable that the corresponding bit of the received data is inverted according to a reception error detected by frame processing of the received data in synchronization with the detection output of the shortened pattern detection circuit 12.

  Instead of the bit inverting circuit 13, a bit replacement circuit that replaces the corresponding bit instead of inverting the corresponding bit of the received data can be used. This bit replacement circuit can be configured to replace corresponding bits of received data in accordance with reception errors.

  FIG. 3 shows an example of the relationship between the frame synchronization pattern and the shortening pattern and the data conversion circuit. Here, it is assumed that there are two reception states due to reception errors, normal and all bit inversion, and the frame synchronization pattern is F628 (hexadecimal number, the same applies hereinafter).

  In this case, the data conversion circuit 11 is configured to obtain an exclusive OR between bits adjacent to each other with respect to the data of the number of bits of the frame synchronization pattern. With this configuration, the output of the data conversion circuit 11 becomes 15 bits and a value of 0D3C with respect to a value of 16 bits of F628. Also, 0D3C is obtained for 09D7 (hexadecimal number) in which the frame synchronization pattern is all bits inverted. The value 0D3C is detected by the shortening pattern detection circuit 12.

  FIG. 4 shows a configuration example of a data conversion circuit that can cope with a situation where there is a possibility of abnormal reception of logic inversion and other bit detection. Here, it is assumed that the received data is a signal obtained by demodulating the DQPSK modulated signal, and the frame synchronization pattern is F628.

In the case of the DQPSK signal, the bit string of the transmission data is An, Bn, An + 1, Bn + 1, An + 2, Bn + 2,..., And depending on the demodulation, both A and B are A, ^{a -, B, B - (} a -, B - is a, the logic inversion of B respectively) when there is a reception state of four different, as for the AB 2 bits together a receive state of a combination of sixteen is assumed. Here, normal demodulation is AB, and other abnormal demodulation is AA, AA ⁻ , AB ⁻ ,. Table 1 shows the relationship between these reception states and synchronization patterns.

このような論理反転および他ビット検出の異常受信状態の可能性がある状況に対応するため、図４に示すデータ変換回路１１は、表１に示したようにＦ６２８のフレーム同期パターンが１６通りの異なったパターンで受信された場合でも、排他的論理和の値が全て「００１１１１００００００」となるように構成される。したがって、排他的論理和の値がこの値であるか否かを短縮パターン検出回路１２で判定することにより、１６通りの異なったパターンで受信したとしても、フレーム同期パターンの受信の有無を判定することができる。

In order to cope with such a situation where there is a possibility of an abnormal reception state of logic inversion and other bit detection, the data conversion circuit 11 shown in FIG. 4 has 16 frame synchronization patterns of F628 as shown in Table 1. Even when received in different patterns, the values of the exclusive OR are all “001111000000”. Therefore, by determining whether or not the value of the exclusive OR is this value, the shortened pattern detection circuit 12 determines whether or not the frame synchronization pattern is received even if 16 different patterns are received. be able to.

  5 and 6 are diagrams for explaining a frame synchronization pattern conversion method based on exclusive OR.

  When there is an abnormal reception state with 2 bits as in DQPSK, the frame synchronization patterns are b15 and b14, b13 and b12, b11 and b10,..., B1 and b0, as shown in FIG. And divided into groups of 2 bits. When the frame synchronization pattern is 16 bits, it is divided into 8 groups. Then, from the two groups (b15b14 and b13b12, b7b6 and b1b0, and b5b4 and b3b2 respectively) in which all the bits are the same, exclusive OR of the first bits and the second bits is performed. Take. Similarly, from the two groups (b11b10 and b9b8) in which all the bits are inverted, the first bit and the second bit are exclusive-ORed.

  If the exclusive OR of the first or second bits from two groups in which all the bits are the same is taken, even if the bits are inverted, both logics are inverted together, so the exclusive OR value is It becomes the same value. Even if there is an abnormality in which another bit or its inverted value is detected, the detected bit itself has the same value in the two groups, so that the exclusive OR value is the same value. .

  In addition, if the exclusive OR of the first or second bits from two groups in which all the bits are inverted from each other, both logics are inverted even if the bits are inverted. The sum value is the same value. In addition, even if there is an abnormality in which another bit or its inverted value is detected, the detected bits are mutually inverted in the two groups, so that the exclusive OR value becomes the same value. .

  In this way, even if the frame synchronization pattern is received in the abnormal reception state, the exclusive OR value selected according to the above rule becomes the same value as in the normal reception state, and the frame synchronization pattern can be detected.

The above method assumes both bit inversion and detection of other bits as abnormal reception states. If only the bit inversion is assumed, namely AB to normal reception of ^AB, AB ^-, AB ^- if there is an abnormal receiving condition, select any two groups, the group What is necessary is just to take the exclusive OR of the 1st bits and 2nd bits. In this case, even if the bit is inverted, both logics are inverted, so that the exclusive OR value is the same value.

  The method described above is not limited to the case where there is an abnormal reception state with a set of 2 bits, but can also be applied when there is an abnormal reception state with a set of N bits. FIG. 6 shows an example when N = 4.

  In this case, the frame synchronization pattern is first divided into a plurality of groups by collecting N bits. Then, the exclusive OR of the values of the Mth bit (M = 1 to N) is taken from two groups (group 1 and group 2 in the example of FIG. 6) in which all the bits are the same. At this time, even if bit inversion is performed, since both values are inverted, the exclusive OR value becomes the same value. Even if there is an abnormality in which another bit or its inverted value is detected, the detected bit itself has the same value in the two groups, so that the exclusive OR value is the same value. .

  Also, an exclusive OR of the values of the Mth bit (M = 1 to N) is taken from two groups (group 3 and group 4 in the example of FIG. 6) in which all bits are inverted. At this time, even if bit inversion is performed, the two values are inverted together, so that the exclusive OR value is the same value. Even if there is an abnormality in which another bit or its inverted value is detected, the detected bits are always inverted values in the two groups, so the exclusive OR values are the same. Value.

  According to the present invention, frame synchronization can be performed even in a reception state where a regular demodulation error has occurred, and the demodulation error can be corrected by performing bit inversion according to the reception state after synchronization is established. It becomes possible. Further, parallel processing of frame synchronization (see Patent Documents 3 and 4) is required as the transmission speed increases, but according to the present invention, not only can the number of bits of the search pattern be reduced, but also at adjacent bit positions. Since the exclusive OR circuit can be shared (reduction of the same exclusive OR) in parallel search, the circuit scale can be reduced.

1 is a block diagram showing a frame synchronization apparatus according to an embodiment of the present invention. The block block diagram which shows the frame synchronization apparatus of a prior art example. The figure which shows an example of the relationship between a frame synchronization pattern and a shortening pattern, and a data conversion circuit. The figure which shows another example of the relationship between a frame synchronization pattern and a shortening pattern, and a data conversion circuit. The figure explaining the conversion method of the frame synchronization pattern by exclusive OR. The figure explaining the conversion method of the frame synchronization pattern by exclusive OR.

Explanation of symbols

11 Data Conversion Circuit 12 Abbreviated Pattern Detection Circuit 13 Bit Inversion Circuit 21 Synchronization Pattern Detection Circuit

Claims (10)

In a frame synchronization apparatus that detects a predetermined frame synchronization pattern from received data and establishes frame synchronization,
The received data is a signal obtained by demodulating a differential phase modulation signal,
Data conversion means for subjecting the received data to constant data conversion in which the frame synchronization pattern is converted into the same fixed pattern even if there is a reception error assumed in the received frame synchronization pattern;
And a fixed pattern detecting means for detecting the fixed pattern from the output of the data converting means.   The data conversion means divides the frame synchronization pattern into a plurality of groups each consisting of N bits, where N ≧ 1, and excludes M bits from two groups, where 1 ≦ M ≦ N. 2. The frame synchronization apparatus according to claim 1, further comprising means for obtaining a logical OR.   The data conversion means divides the frame synchronization pattern into a plurality of groups composed of N bits, where N ≧ 2, and two groups in which all the bits are the same or all the bits are inverted 3. The frame synchronization apparatus according to claim 1, further comprising means for obtaining an exclusive OR of the values of the Mth bit, wherein 1 ≦ M ≦ N.   3. The frame synchronization apparatus according to claim 2, wherein the assumed reception error is an error in which the logic of the Mth bit of the group is inverted.   4. The frame synchronization apparatus according to claim 3, wherein the assumed reception error is an error in which the logic of the M-th bit of the group is the same as the logic of other bits or the logic of other bits is inverted.   5. The assumed reception error is all-bit inversion, and the data conversion means includes means for obtaining an exclusive OR between adjacent bits with respect to data of the number of bits of the frame synchronization pattern. Frame synchronizer. The differential phase modulated signal is a DQPSK modulation (Differential Quadrature Phase Shift Keying) No. signal, transmission data An, Bn, An + 1, Bn + 1, An + 2, Bn + 2, ... is a by When there are 16 combinations of reception states of A, A ⁻ , B, and B ⁻ (A ⁻ and B ⁻ are logical inversions of A and B, respectively) depending on demodulation, the data conversion means performs the frame synchronization. 6. The means according to claim 5, further comprising means for obtaining an exclusive OR of the odd-numbered bits and the even-numbered bits, respectively, between sets of the same logic and different sets of logic of the odd-numbered bits and even-numbered bits of the pattern. Frame synchronizer.   If the received pattern at that time and the frame synchronization pattern do not match despite the detection of the fixed pattern by the fixed pattern detection means, the corresponding bits of the received data are inverted so that they match. 2. The frame synchronization apparatus according to claim 1, further comprising bit inversion / replacement means for replacing the corresponding bit.   9. The bit inversion / replacement means inverts or replaces a corresponding bit of reception data in accordance with a reception error detected by frame processing of the reception data in synchronization with a detection output of the fixed pattern detection means. Frame synchronizer. In a frame synchronization method for establishing a frame synchronization by detecting a predetermined frame synchronization pattern from received data,
The received data is a signal obtained by demodulating a differential phase modulation signal,
Even if there is a reception error assumed in the received frame synchronization pattern, the received data is subjected to constant data conversion in which the frame synchronization pattern is converted into the same fixed pattern,
A frame synchronization method, wherein the fixed pattern is detected from received data that has undergone constant data conversion.

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