JP4347170B2 - Error detection apparatus, error correction apparatus using the same, and method - Google Patents

Description

  The present invention relates to an error detection device, an error correction device using the error detection device, and a method thereof, and more particularly to a bit error detection and correction method for transferring parallel data in a differential interface format.

  An error control code (abbreviated as ECC) is used to detect and correct a data transfer error on a bus for transmitting data. That is, for 1-bit error detection, 1-bit parity is added. For 1-bit error correction and 2-bit error detection, for example, 8-bit ECC is used for 64-bit data. In addition, error detection and correction are performed.

  However, with 1-bit parity, it is only possible to detect a 1-bit data error, and it is not possible to specify which bit of the data has an error. It is necessary to resend the same data, and the data transfer performance deteriorates. In order to correct a 1-bit error, it is necessary to add a multi-bit ECC as described above. In particular, in the case of parallel data transfer, the number of wires constituting the bus increases accordingly. become.

Here, as the bus transfer speed increases, each data bit constituting parallel data is transferred by a differential interface method using a difference between two signal lines instead of being transmitted by one signal line. Technology is used (see, for example, Patent Document 1). Since this differential interface method uses two signal lines for a 1-bit signal and uses the difference between the two signal lines, even if noise is superimposed on a data bit, 2 Since the noise is simultaneously superimposed on the signal lines of the book, by taking the difference, noise cancellation is performed and the circuit is resistant to noise.
JP-A-8-43472

  As described above, it is possible to detect only one bit error by adding a parity bit, but it is impossible to correct the error. Therefore, when an error is detected, a data retransmission process is required and the data transfer performance deteriorates. There is a problem of doing. The cause of this problem is that the bit position where the error occurred cannot be specified only by the parity bit.

  Therefore, if a method of adding a plurality of bits of ECC is employed to enable error correction, there is a problem that the number of bus lines increases. In particular, when this multi-bit ECC method is used for the above-described differential interface parallel data transfer, two signal lines are required for each bit of the multi-bit ECC, and the wiring of the bus The increase in the number is remarkable.

  An object of the present invention is to provide an error detection apparatus that can easily identify an error-occurring bit, an error correction apparatus using the same, and a method thereof.

  Another object of the present invention is to provide an error detection apparatus capable of detecting an error of a plurality of bits for parallel data, an error correction apparatus using the same, and a method thereof.

  Still another object of the present invention is to provide an error detection and correction apparatus capable of correcting a 1-bit error only by adding 1 parity bit to parallel data, and an error correction apparatus and method using the same. It is to be.

Error detection and correction device according to the invention, the parallel data bits and the parity bits, respectively a error detection and correction device of the data to be transmitted as a pair of differential signals, the parallel data bits and each of the parity bits A differential amplifier provided correspondingly and using the corresponding pair of differential signals as a differential input, and outputs of the differential amplifier are different from each other between a high level and a low level of the output. An error detecting device for detecting the presence or absence of an error of a corresponding bit according to the comparison result, and when the detection result by the error detecting device is a 1-bit error, this by using the other bits except for the bits detected error by the detection unit and the parity bit and an error correcting means for forming an error correction The features.

Rue error detecting device by the present invention, there is provided a first and a second error detection apparatus of the data bits in parallel to each other, the first data bit, the first in response to "0" and "1" Level and second level, first level converting means for converting to a first fixed level intermediate between the first and second levels, and the second data bit according to “0” and “1” Third level and fourth level, second level converting means for converting to a second fixed level that is intermediate between the third and fourth levels and different from the first fixed level, and the first level converting means The level output corresponding to the “0” and “1” is compared with the first and second fixed levels, and the “0” and “1” of the second level conversion unit. The level output according to "" is compared with the first and second fixed levels. Second comparison means, detecting the presence or absence of an error in the first data bit according to the comparison result of the first comparison means, and according to the comparison result of the second comparison means. It is characterized in that the presence or absence of an error in the second data bit is detected.

An error detection and correction apparatus according to the present invention is a data error detection and correction apparatus configured to transmit a parallel data bit and a parity bit thereof as a pair of differential signals, respectively, and each of the parallel data bit and the parity bit. The above-described error detection device provided correspondingly, and when the detection result by the error detection device is a 1-bit error, using the other bits except the bit error-detected by the error detection device and the parity bit And error correction means for performing error correction.

Error detection and correction method according to the invention, the parallel data bits and the parity bits, respectively a error detection and correction method of the data to be transmitted as a pair of differential signals, each of said parallel data bits and the parity bits In contrast, the step of differentially amplifying the pair of differential signals, and the output of the step of differentially amplifying are different first and second threshold values between a high level and a low level of the output A step of making an error detection method including a comparison step to compare and an error detection step of detecting the presence or absence of an error of a corresponding bit according to the comparison result ; Error correction is performed by using the other bits except the bit detected by the error detection method and the parity bit. Characterized in that it comprises a color correction step.

Rue error detection method by the present invention is a parallel first and second error detection method of the data bits from each other, the first data bit, the first in response to "0" and "1" A level and a second level, a first level conversion step of converting to a first fixed level intermediate between the first and second levels, and the second data bit in accordance with "0" and "1" A third level and a fourth level; a second level conversion step for converting to a second fixed level that is intermediate between the third and fourth levels and different from the first fixed level; and the first level conversion step The level output corresponding to the “0” and “1” is compared with the first and second fixed levels, and the “0” and “1” of the second level conversion step are compared. Level output according to the first and second The second comparison step for comparing with the fixed level of the first and the first comparison step detects the presence or absence of an error in the first data bit according to the comparison result of the first comparison step, and according to the comparison result of the second comparison step And an error detection step of detecting the presence or absence of an error in the second data bit.

An error detection and correction method according to the present invention is a data error detection and correction method in which a parallel data bit and its parity bit are transmitted as a pair of differential signals, respectively, each of the parallel data bit and the parity bit. On the other hand, using the above-described error detection method, and when the detection result by the error detection method is a 1-bit error, the other bits except the bit detected by the error detection method and the parity bit are used. And an error correction step for error correction.

  According to the present invention, there is a remarkable effect that it is possible to easily detect an error for one bit of data with only its own bit with a simple circuit configuration. Therefore, if this error detection method is used, it is possible to detect and correct a 1-bit error only by adding a 1-bit parity bit with respect to parallel data bits, thereby improving data transfer efficiency by retransmission control. Is possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 101 to 10N (N is an integer of 2 or more) are each data bit of the differential interface constituting the N-bit bus of the N-bit parallel signal. Reference numeral 110 denotes a parity bit of a differential interface that constitutes parity for the N-bit data. The differential interfaces 101 to 10N and 110 are input to the corresponding differential amplifiers 201 to 20N and 210, respectively, and “0” or “1” of the bits of the corresponding differential interfaces 101 to 10N and 110 are received by the respective differential amplifiers. "Is identified.

  The outputs of the differential amplifiers 201 to 20N and 210 are input to the corresponding error detection units 301 to 30N and 310, and error detection of the corresponding bits is performed. Since the configurations of these error detection units are all the same, the error detection unit 301 will be described with reference to FIG. In FIG. 2, the output 30 from the differential amplifier 201 in the previous stage is directly derived to the output 401 as the identification result of “0” or “1” of the data bit, and to the positive phase input of the differential amplifiers 31 and 32. Is also applied. Reference voltages V1 and V2 are input to the negative phase inputs of the differential amplifiers 31 and 32, respectively. The outputs of these differential amplifiers 31 and 32 are input to an EXOR (exclusive OR) circuit 35 and output as an error detection presence / absence signal 421.

  The other error detection units 302 to 30N and 310 also output “0” or “1” identification bit outputs 402 to 40N and 410 and error detection presence / absence signals 422 to 42N and 411, respectively.

  The outputs of the error detection units 301 to 30N and 310 are input to the error correction unit 400. In the error correction unit 400, if no error has occurred, the identification result of the data bits of the differential interfaces 101 to 10N by the differential amplifiers 201 to 20N is corrected. The result is output to 501 to 50N. When two or more multi-bit errors occur, a signal 601 is output for retransmission control. Further, when a 1-bit error occurs, a signal 602 used for log collection or the like is output.

  FIG. 3 is a block diagram showing a specific example of the error correction unit 400. The data bit identification result signals 401 to 40N and the parity bit identification result signal 410 from the error detection unit in the previous stage are input to the selectors 441 to 44N and the error correction value calculation circuit 450.

  Error correction value calculation circuit 450 outputs correction values 431 to 43N calculated from other data bits and parity bits for each data bit, and is connected to selector circuits 441 to 44N, respectively. The error detection presence / absence signals 421 to 42N for the respective data bits output from the error detection unit are connected as select signals of the selector circuits 441 to 44N, respectively. When no error is detected, the data bit identification result signals 401 to 40N are displayed. If selected and there is an error detection, correction values 431 to 43N are selected.

  The error detection presence / absence signals 421 to 42N are also input to the error detection bit count circuit 460, and the number of data bits in which an error has been detected is counted. When the number of detected errors is 2 or more, it is output as a signal 601, and when the number of detected errors is 1, it is output as a signal 602. Since the error detection bit count circuit 460 is well known to those skilled in the art and is not directly related to the present invention, its detailed configuration is omitted.

  Details of the error correction value calculation circuit 450 will be described with reference to FIG. The correction value 431 for the data bit 401 is an EXOR of the data bits 402 to 40N and the parity bit 410. Correction value 432 for data bit 402 is an EXOR of data bit 401 and data bit 403 to data bit 40N and parity bit 410. The same applies hereinafter, and the correction value 43N for the data bit 40N is an EXOR of the data bit 401 to the data bit 40 (N-1) and the parity bit 410.

  Since the output 411 of the parity bit error detection unit 310 is not used in the error correction unit 400 in the next stage, the error detection unit 310 may pass the output of the differential amplifier 210 as it is. .

  The operation of error detection and correction processing will be described below using the timing chart of FIG. 5 and the flowchart of FIG. FIG. 5A is a timing diagram of the clock signal, and FIG. 5B shows an example of a waveform change of the difference of the differential interface signal 101 that operates in synchronization with the clock signal. As shown in FIG. 5C, the output 30 of the differential amplifier 201 amplifies the differential interface signal 101 and supplies the output to the positive phase inputs of the differential amplifiers 31 and 32 of the error detection unit 301.

  The reference voltages V1 and V2 are respectively input to the negative phase inputs of the differential amplifiers 31 and 32, and the difference between the signal 30 and the reference voltages V1 and V2 is amplified and output. In this example, the reference voltages V1 and V2 are voltages between the high level V and the low level 0 of the signal 30, and are set to V1 = (3/4) V and V2 = (1/4) V, respectively. It is assumed that

  Here, on the transmission side (not shown) of the differential interface signal 101, the bit data changes from + VD to −VD depending on whether the bit data is “1” or “0”, and the output 30 of the differential amplifier 201 on the reception side. Then, it is larger than V1 or smaller than V2, and does not become a voltage level between V1 and V2, and when it reaches a voltage level between V1 and V2, it has a property of being a bit error. is there.

  Therefore, in the present invention, this characteristic is utilized, and the signal 30 is compared with the reference levels V1 and V2 by the differential amplifiers 31 and 32 having different reference levels (thresholds), and FIG. As shown in (E), the amplified difference (comparison result) is input to the EXOR circuit 35, and the presence or absence of error detection is output as a signal 421 as shown in FIG. 5 (F). . In this example, at the timing of the clock T3, the output of the differential amplifier 31 is digitally “0”, the output of the differential amplifier 32 is digitally “1”, and an error occurs in the output 421 of the EXOR circuit 33. A signal indicating the presence of detection is derived as “1”.

  In this way, if an error occurs in the differential interface signal 101 and the other differential interface signals 102 to 10N and 110 are normal, an error detected signal indicating that the error has occurred in the differential interface signal 101. One-bit error correction is performed by the error correction unit 400 using 421, other normal data bit identification signals 402 to 40N, and the parity bit 410. That is, as shown in FIGS. 3 and 4, the error-free data identification signals 402 to 40N and the EXOR output 431 of the parity bit 410 are selected by the selector 441 and derived as a corrected bit output 501. The correct data bit identification signals 402 to 40N are derived as they are from the other bit outputs 502 to 50N. When an error occurs in the other 1 bit, it is corrected in the same manner.

  The flowchart of FIG. 6 explains the operation of the error detection and correction processing apparatus of the present invention in a process flow. In the flowchart shown in FIG. 6, in step A, differential amplifier output for identifying 0 or 1 of the differential interface is performed, and in step B, error detection processing is performed by the error detection unit. In step C, it is determined whether or not an error is detected. If no error is detected, the data is output as it is in step D. If there is an error in step C, it is determined whether there is a 1-bit error in step E. If it is a 1-bit error, error correction processing is performed in step F, and the corrected data is output in step G In addition, a signal 602 is output for log collection and the like. When an error of 2 bits or more is detected instead of a 1-bit error in step E, a signal 601 is output for retransmission control or the like in step H.

  Next, another embodiment of the present invention will be described. FIG. 7 is a block diagram showing the present embodiment, and the same parts as those in FIG. In this example, the differential interfaces 101 to 10N and 110 are handled in two pairs, the differential amplifiers 201 to 20N and 210 in FIG. 1 are eliminated, and output level conversion units 701, 702,. (N + 1) / 2) is provided, and error detection is performed on the output side of the output level conversion unit using the error detection units 801, 802, ..., 80 ((N + 1) / 2). This is different from the example of FIG. 1, which is the previous embodiment, in that the error detection is devised.

  The output level conversion unit 701 handles two sets of differential interfaces 101 and 102 as a pair, and performs level conversion processing on the two sets of bit inputs 1 and 2 and outputs them as differential interfaces 101 and 102, respectively. The error detection unit 801 at the next stage receives two sets of differential interfaces 101 and 102 as inputs. The output level conversion unit 702 performs level conversion processing on the two sets of bit inputs 3 and 4 and outputs them as differential interfaces 103 and 104, respectively. The error detection unit 802 at the next stage receives two sets of differential interfaces 103 and 104 as inputs. Similarly, the output level conversion unit 70 ((N + 1) / 2) performs level conversion processing on the last bit input N and the parity bit 10 and outputs them as differential interfaces 10N and 110, respectively. The error detection unit 80 ((N + 1) / 2) at the next stage receives two sets of differential interfaces 10N and 110 as inputs.

  Hereinafter, as in the previous embodiment, the data bit identification result and the error detection presence / absence signal are output from each error detection unit and input to the error correction unit 400.

  FIG. 8 is a circuit diagram showing an example of the output level conversion unit 701 in FIG. Since the other output level conversion units have the same configuration, the description thereof is omitted. In FIG. 8, a differential interface driver 711 is connected to reference voltages 721 and 722 and outputs differential interfaces 741 and 742. Here, the differential interface 742 is fixed to an intermediate voltage between the reference voltages 721 and 722 by a resistor 731. In the figure, reference voltage 721 is + 4V volts, reference voltage 722 is -2V volts, and differential interface 742 is + V volts. The differential interface 741 varies from + 4V to -2V.

  On the other hand, the differential interface driver 712 is connected to the reference voltages 723 and 724 and outputs the differential interfaces 743 and 744. Here, the differential interface 744 is fixed to an intermediate voltage between the reference voltages 723 and 724 by a resistor 732. In the figure, the reference voltage 723 is + 2V volts, the reference voltage 724 is -4V volts, and the differential interface 744 is -V volts. The differential interface 743 varies from + 2V to −4V. That is, the differential interface 741 is larger than the differential interface 742 or smaller than the differential interface 744, and the differential interface 741 does not reach the voltage level between the differential interfaces 742 and 744 on the receiving side.

  Similarly, the differential interface 743 is larger than the differential interface 742 or smaller than the differential interface 744, and the differential interface 743 is at the voltage level between the differential interfaces 742 and 744 on the receiving side. Absent. The error detection is performed on the receiving side using the above-described properties.

  FIG. 9 is a circuit diagram showing an example of the error detection unit 801, and the other error detection units have the same configuration, and thus description thereof is omitted. In FIG. 9, the differential interface 101 (741, 742) is input to the differential amplifier 821, and the data bit identification result 401 is output. The differential interface 102 (743, 744) is input to the differential amplifier 823, and the data bit identification result 402 is output.

  741 of the differential interface 101 becomes a positive phase input of the differential amplifier 822, and 743 of the differential interface 102 becomes a positive phase input of the differential amplifier 824. Then, 742 of the differential interface 101 becomes a negative phase input of the differential amplifier 824 as a reference voltage (+ V), and 744 of the differential interface 102 becomes a negative phase input of the differential amplifier 822 as a reference voltage (−V). Yes. The output 401 of the differential amplifier 821 and the output of the differential amplifier 822 are input to the EXOR circuit 831, and the output 421 becomes an error detection presence / absence signal of the differential interface 101. The output 402 of the differential amplifier 823 and the output of the differential amplifier 824 are input to the EXOR circuit 832, and the output 422 becomes an error detection presence / absence signal of the differential interface 102.

It is a block diagram of one embodiment of the present invention. It is a figure which shows the specific example of the error detection part of FIG. It is a figure which shows the specific example of the error correction part of FIG. It is a figure which shows the specific example of the error correction value calculation circuit of FIG. It is an example of the timing chart which shows operation | movement of one embodiment of this invention. It is a flowchart which shows operation | movement of one embodiment of this invention. It is a block diagram of other embodiments of the present invention. It is a figure which shows the specific example of the output level adjustment part of FIG. It is a figure which shows the specific example of the error detection part of FIG.

Explanation of symbols

1 to N Parallel digital signal (bit data)
10 Variety bit
101-10N, 110 differential interface
201-20N, 210 Differential amplifiers 301-30N, 310,
801 to 80 ((N + 1) / 2) error detection unit
400 Error correction section
450 Error correction value calculation circuit
460 Error detection bit count circuit 701 to 70 ((N + 1) / 2) output level conversion circuit

Claims (14)

A data error detection and correction apparatus configured to transmit parallel data bits and parity bits thereof as a pair of differential signals , respectively .
A differential amplifier provided corresponding to each of the parallel data bit and the parity bit and using the corresponding pair of differential signals as a differential input, and the output of the differential amplifier is connected to a high level and a low level of the output. and a comparing means for comparing the different first and second thresholds between levels, and Rue error detection device to detect the presence or absence of a corresponding bit error in accordance with the comparison result,
Error detection means for performing error correction using the other bits excluding the bits detected by the error detection device and the parity bit when the detection result by the error detection device is a 1-bit error. An error detection and correction device. The comparison means includes first and second differential circuits that compare the output of the differential amplifier with the first and second threshold values, respectively.
2. The error detection and correction apparatus according to claim 1 , wherein the error detection apparatus further includes an exclusive OR circuit having outputs of the first and second differential circuits as inputs. An error detection device for first and second data bits in parallel with each other,
First level conversion means for converting the first data bit to a first level and a second level according to “0” and “1” and a first fixed level intermediate between the first and second levels. When,
The second data bit includes a third level and a fourth level corresponding to “0” and “1”, and a second fixed level that is intermediate between the third and fourth levels and different from the first fixed level. Second level conversion means for converting to
First comparison means for comparing level outputs corresponding to the "0" and "1" of the first level conversion means with the first and second fixed levels;
Second comparison means for comparing the level output corresponding to the "0" and "1" of the second level conversion means with the first and second fixed levels;
The presence or absence of an error in the first data bit is detected according to the comparison result of the first comparison means, and the presence or absence of an error in the second data bit is detected according to the comparison result of the second comparison means. An error detection device characterized by that. The first comparison means includes first and second differential circuits for comparing the level output of the first level conversion means with the first and second fixed levels, respectively.
The second comparing means has third and fourth differential circuits for comparing the level output of the second level converting means with the first and second fixed levels, respectively.
A first exclusive OR circuit that receives the outputs of the first and second differential circuits and a second exclusive OR circuit that receives the outputs of the third and fourth differential circuits. The error detection device according to claim 3, further comprising: A data error detection and correction apparatus configured to transmit parallel data bits and parity bits thereof as a pair of differential signals, respectively.
The error detection device according to claim 3 or 4 provided corresponding to each of the parallel data bits and the parity bits,
Error detection means for performing error correction using the other bits excluding the bits detected by the error detection device and the parity bit when the detection result by the error detection device is a 1-bit error. An error detection and correction device. 6. The error detection and correction apparatus according to claim 1, further comprising an error detection bit count circuit that counts the number of data bits in which an error has been detected by the error detection apparatus. A means for outputting a signal instructing retransmission of the parallel data bit and its parity bit when the detection result by the error detection device indicates an error of 2 bits or more, further comprising : The error detection and correction apparatus according to any one of 5 and 6 . A data error detection and correction method for transmitting parallel data bits and their parity bits as a pair of differential signals , respectively ,
For each of said parallel data bits and the parity bits, the steps of differentially amplifying said pair of differential signals, the output of the step of the differential amplifier, between the high and low levels of the output a comparison step of comparing the different first and second thresholds, the method comprising: an error detection step of detecting the presence or absence of a corresponding bit error in accordance with the comparison result form the free non-image error detection method,
An error correction step of performing error correction using the other bits excluding the bits detected by the error detection method and the parity bit when the detection result by the error detection method is a 1-bit error. Error detection and correction method. The comparing step comprises comparing the output of the differential amplifying step with the first and second threshold values, respectively;
9. The error detection and correction method according to claim 8, wherein the error detecting step includes a step of performing an exclusive OR process on the outputs of the comparing steps. An error detection method for first and second data bits in parallel with each other,
A first level converting step of converting the first data bits into first and second levels according to “0” and “1” and a first fixed level intermediate between the first and second levels; When,
The second data bit includes a third level and a fourth level corresponding to “0” and “1”, and a second fixed level that is intermediate between the third and fourth levels and different from the first fixed level. A second level conversion step to convert to,
A first comparison step of comparing level outputs corresponding to the “0” and “1” of the first level conversion step with the first and second fixed levels;
A second comparison step for comparing level outputs corresponding to the “0” and “1” of the second level conversion step with the first and second fixed levels;
The presence or absence of an error in the first data bit is detected according to the comparison result in the first comparison step, and the presence or absence of an error in the second data bit is detected according to the comparison result in the second comparison step. An error detection method comprising: an error detection step. The first comparison step includes a step of comparing the level output of the first level conversion step with the first and second fixed levels, respectively, and the second comparison step includes the second comparison step. Comparing the level output of the level converting step with the first and second fixed levels, respectively.
The error detection step includes a step of performing an exclusive OR process on each output of the first comparison step, and a step of performing an exclusive OR process on each output of the second comparison step. The error detection method according to claim 10. A data error detection and correction method for transmitting parallel data bits and their parity bits as a pair of differential signals, respectively,
The step of performing an error detection method according to claim 10 or 11 for each of the parallel data bits and the parity bits;
An error correction step of performing error correction using the other bits excluding the bits detected by the error detection method and the parity bit when the detection result by the error detection method is a 1-bit error. Error detection and correction method. 13. The error detection and correction method according to claim 8 , further comprising a step of counting the number of data bits in which an error is detected by the error detection method. 10. The method according to claim 8, further comprising a step of outputting a signal instructing retransmission of the parallel data bit and its parity bit when a detection result by the error detection method indicates an error of 2 bits or more . The error detection and correction method according to any one of 12 and 13 .

Images