JP4159580B2 - Symbol clock recovery circuit - Google Patents

Description

  The present invention relates to a clock recovery circuit of a demodulator provided in a digital mobile communication terminal or the like that receives a burst signal by adopting a TDMA (Time Division Multiple Access) system, and more particularly to phase modulation such as QPSK (quadrature phase shift keying). The present invention relates to a clock recovery circuit capable of performing high-speed phase acquisition for wave demodulation.

  In digital mobile communication, the π / 4QPSK phase modulation method and the TDMA method are employed. In such mobile communication, in order to transmit and receive data, it is necessary to synchronize with the timing of the symbol clock in the base station, so the phase of the symbol clock signal of the base station and the phase of the symbol clock signal of the mobile station Had to be synchronized. The digital mobile communication terminal, which is a mobile station, receives the signal transmitted from the base station, extracts the timing of the symbol clock signal of the base station from the received signal, and sets the phase of the symbol clock signal of the digital mobile communication terminal. Must be synchronized to the phase of the base station symbol clock signal. As described above, a circuit that regenerates the symbol clock signal in the mobile station so as to be synchronized with the phase of the symbol clock signal of the base station is a symbol clock recovery circuit.

FIG. 5 is a schematic block diagram showing a configuration example of a conventional symbol clock recovery circuit.
In FIG. 5, a symbol clock recovery circuit 100 includes a timing extraction circuit 101 and a PLL circuit 104 including a comparator 102 and a counter 103 having a free-running counter, and the phase of the recovered clock signal that is an output signal is A phase pull-in operation is performed to synchronize with the phase of the input modulated wave.

  The timing extraction circuit 101 detects a zero cross point of the inputted modulated wave signal and outputs a pulse signal indicating the zero cross point to the PLL circuit 104. In the PLL circuit 104, the output signal from the timing extraction circuit 101 is input as a symbol timing signal, and a free-running counter is synchronized with the symbol timing signal to generate and output a reproduced symbol clock signal.

  In such a configuration, if the phase pull-in range of the recovered symbol clock signal with respect to the symbol clock signal is widened, that is, the synchronization accuracy is lowered, the PLL circuit 104 increases the phase pull-in speed, which is the speed until the synchronization is achieved However, the stability of the reproduced symbol clock signal is lowered and the characteristics are deteriorated. Conversely, if the phase pull-in range of the regenerated symbol clock signal with respect to the symbol clock signal is narrowed, that is, the synchronization accuracy is improved, the phase pull-in speed is reduced, but the stability of the regenerated symbol clock signal is improved and the characteristics are also improved. .

FIG. 6 is a timing chart showing an operation example of the PLL circuit 104 shown in FIG. 5. The operation of the PLL circuit 104 in FIG. 5 will be described with reference to FIG.
The counter 103 is constituted by a free-running counter having a counter cycle of “00h” to “13h”, and the PLL circuit 104 indicates a zero cross point input from the timing extraction circuit 101 shown in FIG. The self-running counter value is adjusted so that the signal and the initial value “00h” of the free-running counter value shown in FIG. That is, the PLL circuit 104 performs an operation of synchronizing the free-running counter value “00h” with the rising edge of the symbol clock signal of the base station shown in FIG.

The PLL circuit 104 generates and outputs a reproduction symbol clock signal so that it rises at the free-running counter value “00h” and falls at the free-running counter value “09h”.
Here, for example, as shown in FIG. 6D, when the zero cross point in FIG. 6B is detected between “00h” to “09h” of the free-running counter value, the reproduced symbol clock to be output. In order to delay the phase of the signal, the self-running counter value that is normally initialized at “13h” is counted up to “14h” and then initialized. By doing so, the phase of the reproduced symbol clock signal can be delayed by 1/20 period.

  For example, as shown in FIG. 6 (e), when the zero cross point in FIG. 6 (b) is detected between “0Ah” to “13h” of the free-running counter value, the reproduced symbol clock signal to be output is output. In order to advance the phase of the self-running counter, the self-running counter value that is normally initialized with “13h” is initialized with “12h”. By doing so, the phase of the reproduced symbol clock signal can be advanced by 1/20 period.

  On the other hand, when the phase of the recovered symbol clock signal is 180 ° different from the symbol clock signal of the base station shown in FIG. 6A, as shown in FIG. In order to establish the synchronization of the phases of the reproduction symbol clock signal and the phase of the reproduction clock signal in the direction of delaying or advancing the phase of the reproduction clock signal as described above, for example, in the case of FIG. It was necessary to perform 10 times (10 × 1/20). Also, in mobile communications, phase pull-in from a completely opposite phase causes a carrier frequency error so that synchronization occurs in the opposite phase, or carrier frequency error correction and phase change results in synchronization in 10 phase change operations. It may not be completed and a lot of time is required.

  For this reason, in the digital mobile communication terminal, since it is necessary to perform phase acquisition at high speed in the initial state of burst reception, a method of increasing the phase acquisition speed by changing the amount of phase change is performed. For example, when the phase change amount is 1/20, this is a case where the phase acquisition range is narrow and the phase acquisition rate is low, and the stability of the recovered clock signal is improved. However, in the initial state of burst reception, since it takes too much time for phase acquisition, phase acquisition is not completed within the redundant bit (preamble) pattern, and communication cannot be established without establishing synchronization. Further, for example, when the phase change amount is 2/20, it is a case where the phase acquisition range is wide and the phase acquisition speed is high, and the phase acquisition is completed within the preamble pattern, but the stability of the reproduced symbol clock signal is poor, Although synchronization is established, a stable symbol clock signal cannot be reproduced, and it is difficult to obtain stable reception.

For this reason, when a TDMA system such as digital mobile communication is adopted, in the initial phase pull-in state, the phase pull-in range is widened and the phase pull-in speed is increased to supplement the synchronization, and the phase error is reduced. When it becomes smaller, the high-speed phase pull-in operation is completed. Next, in order to improve the stability of the operation, the phase acquisition range is narrowed and the phase acquisition speed is decreased to maintain synchronization, thereby generating a stable reproduction symbol clock signal.
In the conventional digital mobile communication terminal, the phase of the symbol clock of the base station is followed at a high speed so that the instantaneous interruption of the call can be completed in a short time at the time of handover, and it is highly stable even when the received electric field strength is weak. There was a symbol clock recovery circuit (see, for example, Patent Document 1).
JP-A-7-202966

  In TDMA systems such as digital mobile communications, synchronization is established in the initial state, that is, in the burst reception preamble pattern, and the data in the slot including the synchronization (unique word) pattern following the preamble pattern is stabilized. It must be received and played back. However, if the carrier frequency error is large, or if the phase of the input signal, that is, the phase of the symbol clock signal of the base station and the phase of the symbol clock signal of the mobile terminal itself are significantly different, the synchronized symbol clock signal can be easily Since it cannot be played back, there has been a problem that communication is not possible.

  Thus, if the phase pull-in of the burst signal is performed by widening the phase pull-in range and increasing the phase pull-in speed, there is a problem that the stability of the regenerated symbol clock signal is lowered and the characteristics of the regenerated symbol clock signal are deteriorated. It was. In addition, if the phase acquisition range is narrowed and the phase acquisition speed is slowed down to perform phase acquisition of the burst signal, it takes too much time to acquire the phase, and phase acquisition is not completed within the preamble pattern, and communication cannot be performed at all. There was a problem that.

  The present invention has been made to solve the above-described problems. When the carrier frequency error is large, the phase of the symbol clock signal of the base station and the phase of the symbol clock signal of the mobile terminal are greatly different. Even in such a case, an object is to obtain a symbol clock recovery circuit having a simple configuration capable of performing a phase pull-in operation at high speed and generating a stable recovered symbol clock signal.

A symbol clock recovery circuit according to the present invention is used in a demodulator such as a digital mobile communication terminal, and reproduces a symbol clock indicating timing for identifying data from a received signal. A phase detection unit that detects and outputs the phase of the signal, and a clock signal generation unit that generates and outputs a clock signal synchronized with the phase detected by the phase detection unit. performs detection of inverse phase state of the phase detected by the phase and the phase detector of the clock signal, when the inverse phase state during a symbol a predetermined number of consecutive detecting a predetermined number of times, the phase the phase of the clock signal to generate a shall to correct complement to be detected phase and phase detection unit.

More specifically, the clock signal generation unit detects a clock signal with a variable phase generated according to a counter value of a free-running counter having a predetermined count cycle, and a phase detection unit. And a phase detection unit that compares the phase of the clock signal output from the counter circuit unit and changes the count cycle of the free-running counter with respect to the counter circuit unit according to the comparison result. An anti-phase state between the detected phase and the phase of the clock signal output from the counter circuit unit is detected. When the anti-phase state is detected, the phase of the generated clock signal is set to the counter circuit unit. and a reverse phase detecting unit for correcting the counter value of the free-running counter so that the detected phase and in phase by the phase detector, the inverse phase detecting unit, while the number of consecutive predetermined symbol When the Kigyaku phase state detecting predetermined number of times, is shall be outputting a reset signal to reset to the initial value a count value of the free-running counter with respect to immediately counter circuit.

  According to the symbol clock recovery circuit of the present invention, the phase of the clock signal generated and output by the clock signal generation unit, specifically, the counter circuit unit having a free-running counter, is converted into the symbol clock signal obtained from the received signal. Synchronized with the phase and corrected to be in phase. For example, when it is detected that the phase of the clock signal generated by the counter circuit unit is opposite, the free-running counter value of the counter circuit unit is immediately reset to the initial value. Therefore, in the digital mobile communication terminal, it is possible to complete the phase pull-in operation at a high speed without pulling the recovered symbol clock signal in the phase opposite to the symbol clock signal of the base station in the initial state of burst reception. Thus, the synchronization holding speed can be increased and a stable reproduction symbol clock signal can be generated.

  Further, when it is detected that the phase of the clock signal generated by the counter circuit unit is opposite, the self-running counter value of the counter circuit unit is reset to a predetermined value without immediately resetting to the initial value. From this, even when the reverse phase is frequently detected in the initial state or no signal state of the burst, the phase of the bit clock signal generated by changing the cycle of the symbol clock signal does not change randomly, Since the frequency of the bit clock signal can be made constant, it is possible to eliminate the influence on the system that receives the bit clock signal.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
Embodiment 1 FIG.
FIG. 1 is a schematic block diagram showing an example of a symbol clock recovery circuit according to Embodiment 1 of the present invention.
In FIG. 1, a symbol clock recovery circuit 1 includes a timing extraction circuit 2 and a PLL circuit 3 so that the phase of a recovered clock signal that is an output signal matches the phase of an input modulated wave. Performs phase pull-in operation to achieve synchronization. The PLL circuit 3 includes a comparator 4, a counter phase detector 5, and a counter 6 having a free-running counter.

The timing extraction circuit 2 is connected to the comparator 4 and the antiphase detector 5 respectively, and the comparator 4 and the antiphase detector 5 are connected to the counter 6 respectively.
The timing extraction circuit 2 detects, for example, a zero cross point from the input modulated wave signal using delay detection that detects from the difference from the symbol one symbol before, and outputs a signal indicating the zero cross point to the PLL circuit 3. To the comparator 4 and the anti-phase detector 5. An output signal from the timing extraction circuit 2 is input to the comparator 4 and the antiphase detector 5 as a symbol clock signal.

  The comparator 4 compares the signal indicating the zero cross point from the timing extraction circuit 2 with the reproduced symbol clock signal input from the counter 6, detects the initialization timing of the counter 6 with respect to the free-running counter, and performs predetermined initialization. Outputs a timing change signal. In this manner, the comparator 4 performs a synchronization operation for synchronizing the symbol clock signal of the base station and the reproduced symbol clock signal with respect to the free-running counter of the counter 6.

  The anti-phase detector 5 detects the anti-phase state of the recovered symbol clock signal with respect to the phase of the symbol clock signal of the base station from the signal indicating the zero cross point from the timing extraction circuit 2 and the free-running counter value input from the counter 6. I do. When the reverse phase detector 5 detects the reverse phase state of the reproduced symbol clock signal, it instantaneously outputs a reset signal to the counter 6 to reset the free-running counter value of the counter 6 and return it to the initial value.

  The counter 6 generates and outputs a regenerated symbol clock signal and a regenerated bit clock signal generated by performing a synchronization operation so that the signal level changes with respect to a predetermined free-running counter value. For example, the counter 6 repeats counting up from the normal free-running counter values “00h” to “13h”, but is initialized with the normal free-running counter value “13h” in response to the initialization timing change signal from the comparator 4. Is initialized with the counter value “12h” or “14h”, thereby changing the phase of the reproduced symbol clock signal.

  Here, in π / 4QPSK modulation, a bit clock signal that is a clock signal that is twice as fast as the symbol clock signal is required to represent one symbol with two bits for a four-value symbol. That is, since 2-bit data is sent from the base station to one symbol clock signal, a signal having a half cycle of the symbol clock signal is used as the bit clock signal. In a normal system, the bit clock signal is a reference for operation.

Next, the operation of the antiphase detector 5 will be described in a little more detail.
FIG. 2 is a timing chart showing an operation example of the PLL circuit 3 shown in FIG. 1, and the operation of the antiphase detector 5 of FIG. 1 will be described with reference to FIG.
The counter 6 is constituted by a free-running counter having a counter cycle of “00h” to “13h”, and the comparator 4 indicates a zero cross point input from the timing extraction circuit 2 shown in FIG. The self-running counter value is adjusted so that the signal matches the initial value “00h” of the free-running counter value shown in FIG. That is, the comparator 4 performs an operation of synchronizing the free-running counter value “00h” with the rising edge of the symbol clock signal of the base station shown in FIG.

  On the other hand, when the pulse signal indicating the zero cross point is input in the section of the free-running counter value “07h” to “0Dh” shown in FIG. It is determined that the phase of the reproduced symbol clock signal is shifted by about 180 ° with respect to the phase, and a reset signal for instantaneously resetting the counter 6 to the initial value is output, as shown in FIG. The self-running counter value is reset to “00h”. For this reason, the phase of the regenerated symbol clock signal at the opposite phase can be synchronized with the phase of the symbol clock signal of the base station. The reproduced symbol clock signal output from the counter 6 at this time is shown in FIG. 2 (e), and the reproduced bit clock signal corresponding to the reproduced symbol clock signal shown in FIG. 2 (e) is shown in FIG. 2 (f). ing.

  In this way, the reverse phase state of the regenerated symbol clock signal with respect to the base station symbol clock signal is eliminated, and the base station symbol clock signal and regenerated symbol clock signal are compared with the free-running counter of the counter 6 by the comparator 4. A synchronization operation is performed to synchronize. 2 shows the case where only the operation by the anti-phase detector 5 is performed for easy understanding, the phases of the symbol clock signal of the base station and the recovered symbol clock signal are completely synchronized. In practice, however, the phase of the symbol clock signal and the recovered symbol clock signal of the base station is completely synchronized by the comparator 4.

  On the other hand, in FIGS. 1 and 2, when the reverse phase is detected by the reverse phase detector 5, a reset signal for resetting the free-running counter value is immediately output to the counter 6. A filter 11 such as an integration circuit may be provided between the counter 6 and the counter 6 to adjust the reset signal input to the counter 6. FIG. 3 is a schematic block diagram showing another example of the symbol clock recovery circuit 1 in such a case. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and only the differences from FIG. 1 will be described here.

3 differs from FIG. 1 in that the reset signal output from the anti-phase detector 5 is input to the counter 6 via the filter 11, and from this, the PLL circuit 3 in FIG. 1 is transferred to the PLL circuit 3a. The symbol clock recovery circuit 1 in FIG. 1 is replaced with a symbol clock recovery circuit 1a.
In a signal processing system circuit, it is conceivable that the characteristic is deteriorated due to the influence of quantization error or noise. Therefore, a filter 11 is provided at the next stage of the antiphase detector 5, and the reset signal to the counter 6 is adjusted by the filter 11 according to a plurality of symbol states. For example, the counter 6 is adjusted so as to output a reset signal only when the antiphase detector 5 detects the antiphase twice in three consecutive symbols. By doing so, a more stable reproduced symbol clock signal can be obtained.

  As described above, the symbol clock recovery circuit according to the first embodiment detects that the phase of the recovered symbol clock signal in the digital mobile communication terminal is opposite to the phase of the symbol clock signal of the base station. A phase detector, and when the anti-phase detector detects that the phase of the recovered symbol clock signal is in an anti-phase state, a reset signal for initializing the free-running counter value of the counter 6 is immediately output to the counter 6 I made it.

  Therefore, when the recovered symbol clock signal at the digital mobile communication terminal is in the opposite phase to the phase of the base station symbol clock signal, the recovered symbol clock signal is instantaneously synchronized with the phase of the base station symbol clock signal. Can be established. For this reason, in the digital mobile communication terminal, it is possible to complete the phase pull-in operation at high speed without performing the phase pull-in to the reverse phase with respect to the symbol clock signal of the base station in the initial state of burst reception. The synchronization holding speed can be increased, and a stable reproduction symbol clock signal can be generated.

Embodiment 2. FIG.
In the first embodiment, when the reverse phase detector 5 detects that the recovered symbol clock signal is in reverse phase with the base station symbol clock signal, the free-running counter value is immediately reset to the initial value. However, if it is detected that the recovered symbol clock signal is in reverse phase with the base station symbol clock signal, the free-running counter value is reset to the initial value when the free-running counter value reaches a predetermined value. This may be referred to as Embodiment 2 of the present invention.

  FIG. 4 is a timing chart showing an operation example of the symbol clock recovery circuit according to the second embodiment of the present invention. In the schematic block diagram showing the symbol clock recovery circuit according to the second embodiment of the present invention, the antiphase detector 5 of FIG. 1 is changed to the antiphase detector 5b, and accordingly, the PLL circuit 3 of FIG. 1 is the same as FIG. 1 except that the symbol circuit is a PLL circuit 3b and the symbol clock recovery circuit 1 of FIG. 1 is a symbol clock recovery circuit 1b. The operation of the detector 5b will be described.

  The reverse phase detection circuit 5b detects the reverse phase state of the recovered symbol clock signal with respect to the phase of the symbol clock signal of the base station from the signal indicating the zero cross point from the timing extraction circuit 2 and the free-running counter value input from the counter 6. I do. When the reverse phase detector 5b detects the reverse phase state of the reproduced symbol clock signal, the counter phase counter 5b counts a reset signal for resetting the free-running counter value to an initial value when the free-running counter value of the counter 6 reaches a predetermined value. 6 is output. 4 (a) to 4 (c) are the same as FIGS. 2 (a) to 2 (c). FIG. 4 (a) shows the symbol clock signal of the base station and FIG. ) Is a signal indicating a zero cross point output from the timing extraction circuit 2, and FIG. 4C shows a bit clock signal of the base station.

  When the anti-phase detector 5b detects the zero cross point in the section of the free-running counter values “07h” to “0Dh” shown in FIG. 4D, the recovered symbol clock is generated with respect to the phase of the symbol clock signal in the base station. It is determined that the phase of the signal is shifted by about 180 °. Based on this determination, the anti-phase detector 5b resets the free-running counter value when the free-running counter value “09h” is reached in FIG. 4, for example, as shown in FIG. 4 (f). A reset signal for returning to the initial value is output to the counter 6. Since the free-running counter value is reset by normal “13h” or 1/2 “09h”, the cycle of the bit clock signal, which is a 1/2 cycle of the symbol clock signal, can be made constant. .

  In this way, the phase of the recovered symbol clock signal at the opposite phase can be synchronized with the phase of the symbol clock signal of the base station, and the period of the recovered bit clock signal can be made constant. The reproduced symbol clock signal output from the counter 6 at this time is shown in FIG. Also, in FIG. 4, for the sake of easy understanding, the case where only the operation by the anti-phase detector 5b is performed is shown, so that the phase of the symbol clock signal of the base station and the phase of the recovered symbol clock signal are completely Although not synchronized, the phase of the symbol clock signal of the base station and the recovered symbol clock signal are completely synchronized by the comparator 4 in practice.

  As described above, the symbol clock recovery circuit according to the second embodiment detects that the phase of the recovered symbol clock signal at the digital mobile communication terminal is opposite to the phase of the symbol clock signal of the base station. A phase detector 5b, and when the anti-phase detector 5b detects that the phase of the regenerated symbol clock signal is in an anti-phase state, a predetermined free-running counter value is set so that the period of the regenerated bit clock signal is constant. Thus, a reset signal for initializing the free-running counter value of the counter 6 is output to the counter 6.

  Therefore, the same effect as that of the first embodiment can be obtained, and the reproduced bit clock can be obtained even when the antiphase detector 5b frequently detects the antiphase in the initial state or no signal state of the burst. Since the frequency of the regenerated bit clock signal can be made constant without the signal phase changing at random, it is possible to eliminate the influence on the system that receives the regenerated bit clock signal.

  In the first embodiment and the second embodiment, the case where the π / 4 QPSK modulation method, the TDMA method, and the zero cross detection method are used has been described as an example. However, the present invention is not limited thereto. It can be easily applied to other modulation schemes and detection schemes.

1 is a schematic block diagram illustrating an example of a symbol clock recovery circuit according to a first embodiment of the present invention. 3 is a timing chart showing an operation example of the symbol clock recovery circuit 1 of FIG. FIG. 6 is a schematic block diagram showing another example of the symbol clock recovery circuit according to the first embodiment of the present invention. 6 is a timing chart showing an operation example of the symbol clock recovery circuit according to the second embodiment of the present invention. FIG. 10 is a schematic block diagram showing a configuration example of a conventional symbol clock recovery circuit. 6 is a timing chart illustrating an operation example of the PLL circuit 104 in FIG. 5.

Explanation of symbols

1, 1a Symbol clock recovery circuit 2 Timing extraction circuit 3, 3a PLL circuit 4 Comparator 5 Anti-phase detector 6 Counter 11 Filter

Claims (2)

In a symbol clock recovery circuit that is used in a demodulator such as a digital mobile communication terminal and recovers a symbol clock indicating timing for identifying data from a received signal,
A phase detector that detects and outputs the phase of the symbol clock signal from the received signal;
A clock signal generator for generating and outputting a clock signal synchronized with the phase detected by the phase detector;
With
The clock signal generation unit performs detection of the opposite phase state between the detected phase by the phase and the phase detection unit of the generated clock signal and the inverse phase state during a symbol a predetermined number of consecutive detecting a predetermined number of times, symbol clock reproduction circuit according to claim Rukoto to correct complement the phase of the clock signal that generates so that the detected phase and in phase by the phase detector. The clock signal generator is
A counter circuit unit that generates and outputs a clock signal in a variable phase according to a counter value of a free-running counter having a predetermined count cycle;
A phase that compares the phase detected by the phase detection unit with the phase of the clock signal output from the counter circuit unit, and changes the count cycle of the free-running counter with respect to the counter circuit unit according to the comparison result A comparison unit;
Detects an anti-phase state between the phase detected by the phase detector and the phase of the clock signal output from the counter circuit unit, and generates the counter circuit unit when the anti-phase state is detected. An anti-phase detector that corrects the counter value of the free-running counter so that the phase of the clock signal is in phase with the phase detected by the phase detector;
Equipped with a,
When the anti-phase detection unit detects the anti-phase state a predetermined number of times in a predetermined number of consecutive symbols, it immediately outputs a reset signal for resetting the count value of the free-running counter to an initial value to the counter circuit unit symbol clock reproduction circuit according to claim 1, wherein to Rukoto.

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