JP2000151724A - Phase synchronizing control device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to generate a clock signal while reducing a jitter since a phase step out easily occurs and the clock signal including a lot of jitters are easier to be generated when a data signal of the same code continuation is inputted or the like because the clock signal is not fed back. SOLUTION: When a phase detector(PD) 13 detects a phase difference between a clock signal and an input data signal generated by a gated controlled oscillators(GCO) 11 and 12 and supplies an LPF 16 with it, this LPF 16 supplies the GCO 11 and the GCO 12 with a control signal while phase synchronizing the clock signal with the input data signal; so it becomes possible to prevent step out to the same code continuation and to generate the clock signal with few jitters.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a phase synchronization control device and a phase synchronization control method.

[0002]

2. Description of the Related Art Hitherto, a trunk system and a subscriber system receiving circuit in an optical communication system have been required to have a high-speed phase-locked loop circuit and to be stable to the same code continuation. PON
(Passive Optical Network)
In an optical subscriber transmission system typified by a system, it is necessary to be able to receive a burst signal, and the need for a high-speed response to a received signal which has not been available in a conventional synchronous network (a system for transmitting and receiving a continuous signal) has increased. ing. As a method for speeding up the clock extraction in the receiving circuit, a method using a digital PLL has been proposed, and a phase synchronization control device as shown in FIG. 5 is known as an example of this method.

[0003] The phase synchronization control device 100
0a and an LPF 110b, and an external reference signal source (RE
The oscillation frequency of the GCO 120 and the GCO 130, which are oscillation sources, is controlled by the PLL 110 synchronized with FCLK) to improve the accuracy of the oscillation frequency. In addition, LPF
A GCO 140 is connected to the output side of 110b, and feeds back an output signal from the LPF 110b to the PD 110a. DATAIN is an input data signal, and NRZ (Non Return to Zero)
Assuming o), the GCO 120 starts the oscillating operation at the rising edge of the input data signal and stops the oscillating operation at the falling edge.

On the other hand, the GCO 130 starts an oscillating operation at a falling edge of an input data signal and stops the oscillating operation at a rising edge. Therefore, the GCO 120 performs the oscillating operation when the input data signal is at the Hi level, and the GCO 130 performs the oscillating operation when the input data is at the Lo level. GCO120 and GCO1
When the output signal from 30 is input to the NOR circuit 150,
In the NOR circuit 150, these output signals are logically added, a clock signal synchronized with the input data is generated, and supplied to the D-FF 160 for identification and reproduction.

[0005]

In the above-described conventional phase synchronization control device, since a clock signal is not fed back, when a data signal having the same code is input, phase synchronization is likely to be lost, and jitter is reduced. It was easy to generate a clock signal containing many.

The present invention has been made in view of the above problems, and has as its object to provide a phase synchronization control apparatus and a phase synchronization control method capable of generating a clock signal while reducing jitter.

[0007]

According to a first aspect of the present invention, there is provided a clock generating means capable of generating a clock signal based on a data signal, and a clock generating means for generating a clock signal based on a control signal. Driving means for oscillating and driving in phase, and a phase synchronization control means for supplying a control signal obtained by synchronizing a clock signal with a data signal to the driving means and generating a clock signal phase-synchronized by the clock generation means; Is provided.

That is, when the driving means drives the clock generating means to oscillate at a predetermined phase based on the control signal, the clock generating means generates a clock signal based on the data signal. When the phase synchronization control means supplies a control signal obtained by synchronizing the phase of the clock signal with the data signal to the drive means, the drive means drives the clock generation means to oscillate based on the control signal, and the phase-synchronized clock signal Is generated.

The clock generation means only needs to be capable of generating a clock signal based on a data signal. As an example of the configuration, the invention according to claim 2 is the same as that of claim 1, The clock generation means includes an oscillation circuit that can generate a clock signal based on a rising edge or a falling edge of the data signal.

That is, when the oscillation circuit is oscillated by the driving means, the oscillation circuit generates a clock signal based on a rising edge or a falling edge of the data signal. As the oscillation circuit here, for example, GCO (G
added Controlled Oscillato
r) and the like.

The driving means may be any means that drives the clock generation means to oscillate at a predetermined phase based on the control signal. The driving means may generate the control signal based on the data signal. A control signal may be generated based on a clock signal or the like separately supplied from the outside. As an example of the configuration of the driving means in the latter case, the invention according to claim 3 is the phase synchronization control device according to claim 1 or 2, wherein the driving means receives a control signal from the phase synchronization control means. When not supplied, a control signal supply means for supplying a control signal based on the reference clock signal is provided. That is, the control signal supply unit supplies the control signal based on the reference clock signal when the control signal is not supplied from the phase synchronization control unit. Then, the control signal is supplied to the driving unit, and is used to drive the clock generation unit to oscillate.

As an example of the configuration for supplying the reference clock, the invention according to claim 4 is the phase synchronization control device according to claim 3, wherein the control signal supply means includes a PLL circuit. There is. That is, when no control signal is supplied from the phase synchronization control means, the PLL circuit generates a control signal based on the reference clock signal and supplies the control signal to the driving means. The phase synchronization control means includes:
A control signal obtained by synchronizing the phase of the clock signal with the data signal is supplied to the driving unit, and the clock generating unit may generate a clock signal whose phase is synchronized. For example, a PD (Phase Detector) and a PD may be used. An LPF may be provided that detects a phase difference between a clock signal and a data signal, synchronizes a clock signal with a data signal based on the phase difference, and obtains a control signal.

The clock generating means may generate the clock signal using the data signal as it is, or may generate the clock signal using the data signal after performing predetermined processing. May be. As an example of the configuration of the clock generation means in the latter case,
The invention according to claim 5 is configured such that the clock generating means includes frequency dividing means for dividing the frequency of the data signal. That is, when the divider divides the data signal, a clock signal is generated based on the divided data signal.

As described above, the method of generating the phase-synchronized clock signal is not necessarily limited to the above-described device, and as an example, the invention according to claim 6 is based on the predetermined signal based on the control signal. The clock generation means is driven to oscillate in phase to generate a clock signal based on the data signal, and the clock generation means is generated based on a control signal obtained by synchronizing the generated clock signal with the data signal. Oscillation driving is performed to generate a phase-synchronized clock signal. That is, the present invention is not necessarily limited to the form of the apparatus, and is effective as a method.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a phase locked loop circuit according to an embodiment of the present invention.

The phase synchronization circuit 10 is provided with a DATAIN terminal, and receives an input data signal from the DATAIN terminal. The GCO 11, GCO 12, PD 13 and D-FF 14 for identification reproduction are connected to the DATAIN terminal, and input data signals input from the DATAIN terminal are given to the respective terminals. DAT
An INV 15 is interposed between the AIN terminal and the GCO 12 to enable control by the rising of the input data signal.

The GCO 11 and the GCO 12 have exactly the same circuit configuration, and their oscillation frequencies are controlled by a control signal input from the LPF 16 or LPF 17a, and each of them is controlled by a NOR circuit 18 connected to the output side. The bit portions of the signal are logically added, and the added signal is output from the CLKOUT terminal as a clock signal.

The PD 13 is connected to the DATAIN terminal and also to the output side of the NOR circuit 18, and compares the phase of the input data signal from the DATAIN terminal with the phase of the clock signal from the NOR circuit 18 to determine the frequency. When the difference is output, the frequency difference is calculated by the LPF 16 and SW1.
9 is supplied as a control signal for the GCO 11 and the GCO 12.

Therefore, the GCO 11 and the GCO 12, which generate a clock signal based on the input data signal from the DATAIN terminal, constitute an oscillation circuit provided in the clock generation means according to the present invention in this sense.

The LPF 16 that supplies a control signal to the GCO 11 and the GCO 12 to oscillate and drive the GCO 11 and the GCO 12 constitutes a driving means according to the present invention in this sense.
The PD 13 that detects a phase difference between the clock signal output from the CO 12 and the input data signal, and the LPF 16 that synchronizes the clock signal with the input data signal based on the detected phase difference and outputs a control signal, In this sense, it constitutes the phase synchronization control means according to the present invention.

The SW19 includes a GCO 17b and a PD 17c.
And a PLL circuit 17 including an LPF 17a, which operates while synchronizing the phase with a reference signal (REFCLK), and supplies a control signal to the GCO 11 and the GCO 12 when the input data signal is cut off. GCO1
7b has the same circuit configuration as the GCO 11 and GCO 12, and the PD 17c connected to the GCO 17b has G
The phase difference between the output signal from the CO 17b and the reference signal from the REFCLK terminal is detected, and the LPF 17a and the SW 19
The control signal is supplied to the GCO 11 and the GCO 12 via the. At this time, the output signal from the LPF 17a is G
It is also supplied to CO17b and fed back.

Therefore, the input data signal supplied from the DATAIN terminal to the D-FF 14 for identification reproduction is latched by the output signal from the NOR circuit 18 as a clock signal, and data retiming is possible. As described above, when the input data signal is interrupted, the control signal is supplied to the PLL circuit 17 for supplying the GCO 11 and the GCO 12.
In this sense constitutes a control signal supply means according to the present invention.

Here, the GCO 11 as a transmission source is generated by both rising and falling edges of the input data signal.
When the input data signal is degraded in duty while controlling the GCO 12 and the GCO 12, the generated CLK signal is accompanied by jitter. Therefore, as shown in FIG. It is also possible.

In this case, the DATAIN terminal and the GCO 11
Ｇ frequency divider 20 is interposed between the GCO 12 and the GCO 12, and when the start / stop switching of the GCO 11 and the GCO 12 is performed, as shown in FIG. 3, only the rising edge of the input data signal is caused. Since the operation is performed, the clock signal can be generated without depending on the duty of the input data signal. Therefore, the 1/2 frequency divider 20 for dividing the frequency of the input data signal constitutes the frequency dividing means according to the present invention in this sense.

Next, the operation of the phase locked loop circuit according to the present embodiment will be described with reference to FIG. In the figure, DATAIN is an input data signal, and this input N
Assume RZ (Non Return to Zero). When the input data signal is input from the DATAIN terminal, the GCO 11 starts the oscillating operation based on the rising edge of the input data signal, and stops the oscillating operation based on the falling edge of the input data signal.

On the other hand, the GCO 12 starts the oscillating operation based on the falling edge of the input data signal, and stops the oscillating operation based on the rising edge of the input data signal. Therefore, when the input data signal is at the Hi level,
The GCO 11 performs an oscillating operation, and when the input data signal is at the Lo level, the GCO 12 performs the oscillating operation.

When the output signals from the GCO 11 and the GCO 12 are input to the NOR circuit 18, the output signals are logically added in the NOR circuit 18, and a clock signal synchronized with the input data is obtained as a NOR output.
When the PD 13 detects the phase difference between the generated clock signal and the input data signal and supplies it to the LPF 16, this L
The PF 16 removes high frequency components and supplies a control signal. Then, since the oscillation frequencies in the GCO 11 and the GCO 12 and the bit rate of the input data signal can be completely matched, it is possible to prevent loss of synchronization with the same code continuation and to generate a clock signal with less jitter.

Here, the operation when a burst signal is received will be described. If a non-signal section continues to the input data signal, the phase comparison is not performed in the PD 13, so that the LPF
No control signal is output from 16. in this case,
Only the control signal from the LPF 16 is transmitted to the GCO 11 and the GCO
When the signal is fed back to 12, the GCO 11 and the GCO 12 are not set to the operating state, and a bit error occurs immediately after the burst signal is input. In order to prevent this bit error, the GCO 17b, PD 17c and LPF 1
There is provided a PLL circuit 17 having a circuit 7a, and generates a control signal in synchronization with the reference signal.

When the input data signal is cut off, LP
The control signal output from F17a is G via SW19.
GCO11 is supplied to CO11 and GCO12.
And the GCO 12 are set to the operating state. When the input data signal is intermittently applied, the switch SW19 is switched from the LPF 16 to the LPF 17a.
The output from 16 is used as a control signal.

Therefore, a high-speed operation with respect to the input of the burst signal is realized, and while the burst signal is being received, loss of synchronization with the same code continuation is prevented, and a clock signal with less jitter can be obtained. . As described above, when the PD 13 detects the phase difference between the clock signal generated by the GCO 11 and the GCO 12 and the input data signal and supplies the same to the LPF 16, the LPF 16 synchronizes the clock signal with the input data signal, Since the control signal is supplied to the GCO 11 and the GCO 12, it is possible to prevent loss of synchronization with respect to continuation of the same code, and to generate a clock signal with less jitter.

[0031]

As described above, according to the present invention, it is possible to generate a clock signal while preventing loss of synchronization and reducing jitter even when a data signal having the same code continuation is input. It is possible to provide a simple phase synchronization control device. Further, according to the second aspect of the present invention, since the clock signal is generated based on the edge of the input data signal, the phase pull-in can be accelerated.

Further, according to the third aspect of the present invention,
It is possible to prevent a data signal from being input after a non-signal section continues and a bit error from occurring. Further, according to the invention, a PLL having a simple configuration is provided.
The circuit can provide a control signal based on the reference signal.

Further, according to the invention of claim 5,
A clock signal can be generated without depending on the duty of the input data signal, for example, by generating the clock signal based only on the rising edge of the input data signal. Further, according to the present invention, even when a data signal having the same code continuation is input, it is possible to prevent a loss of synchronization and to generate a clock signal while reducing jitter. A synchronization control method can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a schematic configuration of a phase locked loop circuit according to an embodiment.

FIG. 2 is a circuit diagram illustrating a schematic configuration of a phase synchronization circuit according to a modification.

FIG. 3 is a waveform diagram showing a signal waveform when a clock signal is generated based on a divided input data signal.

FIG. 4 is a waveform diagram showing a signal waveform when a clock signal is generated.

FIG. 5 is a circuit diagram showing a schematic configuration of a conventional phase locked loop circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Phase synchronous circuit 11, 12 GCO 13 PD 14 D-FF for discrimination reproduction 15 INV 16 LPF 17 PLL circuit 18 NOR circuit 19 SW

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5J106 AA03 CC03 CC06 CC21 CC38 CC52 DD09 DD43 FF02 KK03 KK25 KK29 KK39 5K029 AA01 CC04 DD02 HH26 LL10 5K047 AA02 AA06 AA12 AA15 BB02 GG09 GG24 GG45 MM46 MM46 MM46

Claims (6)

[Claims] A clock generating means for generating a clock signal based on a data signal; a driving means for oscillating the clock generating means at a predetermined phase based on a control signal; A phase synchronization control unit for supplying a control signal obtained in synchronization to the driving unit and generating a clock signal whose phase is synchronized by the clock generation unit. 2. The phase synchronization control device according to claim 1, wherein said clock generation means includes an oscillation circuit capable of generating a clock signal based on a rising edge or a falling edge of said data signal. A phase synchronization control device characterized by the above-mentioned. 3. The phase synchronization control device according to claim 1 or 2, wherein the driving unit transmits the control signal based on a reference clock signal when the control signal is not supplied from the phase synchronization control unit. A phase synchronization control device comprising control signal supply means for supplying. 4. The phase synchronization control device according to claim 3, wherein said control signal supply means includes a PLL circuit. 5. The phase synchronization control device according to claim 1, wherein said clock generation means includes frequency division means for frequency dividing said data signal. Control device. 6. A clock signal is generated by oscillating a clock generation means at a predetermined phase based on a control signal, generating a clock signal based on a data signal, and synchronizing the generated clock signal with the data signal. A phase synchronization control method comprising: oscillating the clock generation means based on the control signal to generate a phase-synchronized clock signal.