JP2821290B2 - PCM terminal device with frame aligner circuit and frame aligner method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame alignment method for synchronizing a frame phase when a multiplexed signal transmitted as a high-order group signal is separated into a low-order group original digital signal, and more particularly to a frame aligner circuit. Related PCM terminal equipment.

[0002]

2. Description of the Related Art Currently, a multiplexing technique is used to transmit many signals on one transmission medium. Frequency division multiplexing (FDM) is a multiplexing technique widely used in analog communication.
In n Multiplex, a plurality of signals occupy different frequency bandwidths, and a modulation technique for converting a frequency is a main technique.

In digital communication, on the other hand, time division multiplexing (TD) in which different signals use different time zones.
M: Time Division Multiple
x), which requires digital processing techniques such as pulse rate conversion.

There are two types of time division multiplexing: periodic multiplexing and burst multiplexing. In the periodic multiplexing, a periodic time division called a multiplex frame is formed on a multiplexed high-order group signal. This is a multiplexing method in which low-order group signals to be multiplexed are sequentially arranged in arbitrarily defined periodic time slots in the multiplexed frame.

In this time division multiplexing, bit synchronization and frame synchronization for grasping the time slot of a pulse signal between transmission and reception are required. One method for achieving this synchronization is network synchronization, which distributes unified clock pulses throughout the communication network and synchronizes all signals.

There is also a demultiplexer for separating an original digital signal from the multiplexed and transmitted multiplexed signal. In the demultiplexer, frame synchronization is required to separate the original digital signal for each channel. Frame aligner circuit. FIG. 3 shows a conventional example of the PCM terminal equipment with the frame aligner circuit.

In FIG. 3, a multiplexed signal transmitted from the outside is input to a digital signal processor (not shown) (not shown), and an input clock 1 is separated and extracted by a timing generation circuit in the DSP. At the same time, the input frame signal 3 for identifying the frame of the transmission signal and the input signal 3 that is a multiplexed signal are identified and output.

The input clock 1, the input signal 2, and the input frame signal 3 are input to the frame aligner circuit 9, and the multiplexed signal data of the input signal 2 is stored in a built-in memory such as a FIFO memory. The write address is written while incrementing the write address by the input clock 1 from the start address shown.

On the other hand, the phase-locked oscillator 4 to which the input clock signal 1 is input generates an internal clock 41 for the device which is phase-locked to the input signal 2 and is output to the counter circuit 7 and the frame aligner circuit 9. . The counter circuit 7 uses the internal clock 41 to generate an address signal 71 and outputs it to the read frame signal generation circuit 8. The read frame signal generating circuit 8 generates a read frame signal 81 from the address signal 71 and outputs the read frame signal 81 to the frame aligner circuit 9.
Output to

In the frame aligner circuit 9, the input signal 2
Frame signal 81 from the internal memory in which
The read address is read out from the memory address designated by (1) while being incremented by the internal clock 41, and is output as the output signal 11.

[0011]

However, in the above-mentioned conventional PCM terminal equipment with a frame aligner circuit,
Since there is no relation with the synchronization between the input frame signal 3 and the read frame signal 81 generated in the apparatus, the input signal 2 written by the input frame signal 3 in the internal memory of the frame aligner circuit 9 is read by the read frame signal 81 Until the data is stored, the data must be retained in the built-in memory. Therefore, if the phase delay of the read frame signal 81 from the input frame signal 3 is delayed so as to exceed the data storage capacity of the built-in memory, it becomes impossible to exchange data with the external data terminal providing the output signal 11. Become.

In order to avoid a state in which data cannot be transmitted / received to / from the data terminal due to the delay, the frame aligner circuit 9 must have a sufficient internal memory capacity to cover the possible delay time. Will be. As a result, when a signal is transmitted with a higher-order group signal by increasing the multiplexing, the capacity of the built-in memory for synchronizing the frame must be increased, and the delay time is indefinite. No matter how large the memory capacity, there is no possibility that the above trouble can be completely avoided. This is a worrying problem for today's advanced information communication systems aiming at high speed communication and multiplexing.

Therefore, in the present invention, in order to minimize the internal memory capacity of the frame aligner circuit 9 and to provide a less expensive PCM terminal device, an input frame signal from the DSP input to the frame aligner circuit is provided. It is an object of the present invention to provide a PCM terminal device with a frame aligner circuit and a frame aligner method for making the delay difference time between the internally generated readout frame signal and the readout frame signal constant.

[0014]

In order to solve the above-mentioned problems, a first solution of the present invention is to extract a transmission timing signal from a PCM multiplex signal transmitted through a transmission line and output the extracted signal as an input clock. Frame aligner means for synchronizing a frame phase of a PCM multiplex signal transmitted and received in a frame for use in the device, comprising: a DSP for outputting an input signal and an input frame signal; In a PCM terminal device having a phase synchronization transmitting means for generating an internal clock,
Counter means for generating an address signal for achieving internal synchronization from the internal clock; read frame signal generating means for generating a read frame signal for reading the internal memory of the frame aligner means from the address signal; Window comparing means for judging a phase difference between a signal and a reset pulse generated from the input frame signal, and controlling to output a reset pulse to the counter means when the phase difference exceeds a certain value; And writing the data of the input signal to the internal memory using the input frame signal and the input clock signal, and reading and outputting data from the internal memory with the read frame signal and the internal clock. Frame aligner means. .

A second solution of the present invention is to provide a DSP which extracts a transmission timing signal from a PCM multiplex signal transmitted through a transmission path and outputs it as an input clock, and outputs an input signal and an input frame signal. A frame aligner circuit comprising: a frame aligner circuit for synchronizing a frame phase of a PCM multiplex signal transmitted to a frame for use in the device; and a phase synchronization oscillator for generating an internal clock for use in the device synchronized with the input clock. With PCM
A terminal circuit for synchronizing the input frame signal with the internal clock to generate a reset pulse; a counter circuit for generating an address signal for synchronizing the device from the internal clock; A read frame signal generating circuit for generating a read frame signal for reading the internal memory of the frame aligner circuit from an address signal; a window pulse generating circuit for generating and outputting a window pulse that is active for a predetermined time from the address signal; A window comparison circuit for controlling the output of the reset pulse to the counter circuit by comparing the reset signal with the reset pulse, and the built-in memory using the input frame signal and the input clock signal to transfer the data of the input signal. Write to Characterized by comprising the said frame aligner circuit for outputting read data from said internal memory and the read frame signal and the internal clock.

A third solution of the present invention is to provide a digital signal for extracting a transmission timing signal from a PCM multiplex signal transmitted through a transmission line and outputting the extracted signal as an input clock, and outputting an input signal and an input frame signal. A frame aligner method having a processing step and a step of generating an internal clock for the apparatus synchronized with the input clock, and further synchronizing the frame phase of the transmitted PCM multiplex signal with the frame phase for the apparatus. Generating a reset pulse by synchronizing the input frame signal with the internal clock, generating a read address signal from the internal clock to read data in a memory area, Generating a window pulse that is active for a fixed time Controlling the resetting of the address signal for reading by comparing the window pulse with the reset pulse, and converting the data of the input signal using the input frame signal and the input clock signal. The method is characterized in that data is written to a memory area, and data is read from the memory area using the read frame signal and the internal clock and output.

[0017]

According to a first solution of the present invention, an input clock is extracted from a transmitted PCM multiplex signal by a DSP of a PCM terminal equipment, and an input frame signal and an input signal which is a multiplex signal are identified. And outputs the data to the built-in memory of the frame aligner means using the input frame signal and the input clock.

At the same time, a reset pulse is generated by adjusting the phase of the input frame signal to the separated internal clock signal synchronized with the input clock. At the same time, an address signal is generated by the counter means from the internal clock, and a readout frame signal is generated from the address signal by the readout frame signal generation means and supplied to the frame aligner means, before the internal memory of the frame aligner means. The input signal data written and stored is expressed as P
Reading is performed for each frame in synchronization with frame reading by another frame aligner or the like in the CM terminal device.

Then, the phase difference between the read frame signal and the reset pulse generated from the input frame signal is determined, and when the phase difference exceeds a certain value, the read frame to be given to the frame aligner means. To cover the delay difference between the signal and the input frame signal,
In order to prevent the capacity of the built-in memory for storing data from going over, the counter means is reset to correct the phase delay of the read frame signal. Thus, the phase delay of the read frame signal from the input frame signal can be suppressed within a certain range.

According to a second solution of the present invention, an input clock is extracted from a transmitted PCM multiplex signal by a DSP of a PCM terminal equipment, and an input frame signal and an input signal which is a multiplex signal are identified. And outputs the data of the input signal to the built-in memory of the frame aligner circuit using the input frame signal and the input clock.

At the same time, a reset pulse is generated by the reset pulse generation circuit from the input frame signal in synchronization with the internal clock signal generated by the phase synchronization oscillator, and is output to the window comparison circuit. In this window comparison circuit, an address signal is generated by a counter circuit from an internal clock, and a window pulse that is active at a low level for a certain period of time of the address signal is generated and input by a window pulse generation circuit.

In parallel with this, a read frame signal is generated from the address signal by the read frame signal generating circuit and output to the frame aligner circuit. The input signal written and stored prior to the internal memory of the frame aligner circuit is stored. Is read out frame by frame in synchronization with frame reading from another frame aligner circuit in the PCM terminal device.

Then, the phase difference between the window pulse generated in synchronization with the read frame signal and the reset pulse synchronized with the input frame signal is compared by the window comparison circuit, and the phase difference becomes large. When the reset pulse lags behind the active period of the window pulse, the counter circuit that outputs the address signal that is the basis of the read frame signal is reset to correct the phase lag of the read frame signal. This allows
The phase delay of the read frame signal from the input frame signal can be suppressed within a certain range.

According to a third solution of the present invention, in a digital signal processing step of a PCM terminal device, an input clock is extracted from a transmitted PCM multiplex signal, and an input frame signal and an input signal which is a multiplex signal are extracted. Identify
The data of the input signal is written into the memory area by the input frame signal and the input clock.

A reset pulse is generated from the input frame signal in synchronization with the generated internal clock signal, an address signal for reading is generated from the internal clock, and a window pulse that is active for a predetermined time is generated from the address signal.

In parallel with this, a read frame signal is generated from the address signal, and the data of the input signal previously written and stored in the memory area is read from another frame aligner means in the PCM terminal equipment. Read out frame by frame in synchronization with.

Then, the phase difference between the window pulse generated in synchronization with the read frame signal and the reset pulse synchronized with the input frame signal is compared. When the reset pulse has a delayed phase, the address signal, which is the basis of the read frame signal, is reset to correct the phase delay of the read frame signal. Thus, the phase delay of the read frame signal from the input frame signal can be suppressed within a certain range.

[0028]

Next, an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the circuit of one embodiment of the present invention.

The same components as those in the conventional example are denoted by the same reference numerals. In FIG. 1, a multiplexed signal transmitted from an external master station or the like is input to a digital signal processor (not shown) (not shown), and an input clock 1 is separated and extracted by a timing generation circuit (not shown). , The input frame signal 3 and the input signal 3 which is a multiplexed signal are discriminated and output from the DSP.

There is a phase-locked oscillator 4 to which the input clock signal 1 is input and a frame aligner circuit 9, and the input signal 2 and the input frame signal 3 are input to the frame aligner circuit 9. A reset pulse 51, which is an output signal of the reset pulse generation circuit 5 to which the input frame signal 3 is input, is input to the window comparison circuit 6. On the other hand, the internal clock 41, which is the output of the phase-locked oscillator 4 to which the input clock 1 is input, is provided by the frame aligner circuit 9, the reset pulse generation circuit 5, and the counter circuit 7.
Is input to The phase synchronous oscillator 4 is a circuit used for clock recovery or the like, and compares a frequency-divided signal of the input clock 1 with a frequency-divided signal of a signal transmitted within itself, and determines the phase difference. A circuit that applies a proportional voltage to a voltage-controlled transmitter to obtain a self-transmission signal.

The counter circuit 7 includes a window comparison circuit 6
Is input, and the address signal 71 output from the counter circuit 7 is input to the window pulse generating circuit 8 and the read frame signal generating circuit 10. A window pulse 81, which is an output signal of the window pulse generation circuit 8, is input to the window comparison circuit 6, and a read frame signal 101, which is an output signal of the read frame signal generation circuit 10, is output from the frame aligner circuit 9.
Has been entered. An output signal 11 is output from the frame aligner circuit 9 to an external device (not shown).
The frame aligner circuit 9 has a built-in memory.

The operation of the above configuration will be described below with reference to FIG. The data of the input signal 2 which is a multiplexed signal input to the frame aligner circuit 9 is sequentially written from the head address of a built-in memory such as a FIFO memory indicated by the input frame signal 3 while incrementing the write address by the input clock signal 1 while incrementing the write address. I get stuck.

On the other hand, the phase-locked oscillator 4 generates and outputs an internal clock 41 whose phase is synchronized with the input clock signal 1. The reset pulse generating circuit 5 generates a reset pulse 51 which is a one-shot pulse synchronized with the internal clock 41 from the input frame signal 3 and outputs it to the window comparing circuit 6.

In the counter circuit 7, the internal clock 4
An address signal 71, which is data obtained by counting up the count value from 0 in synchronization with 1, is output to the window pulse generating circuit 8 and the read frame signal generating circuit 10. The window pulse generation circuit 8 generates an active low level window pulse 81 when the data value of the address signal 71 is predetermined data, and outputs the window pulse 81 to the window comparison circuit 6 (window in FIG. 2). Pulse 81). The width of the low level of the window pulse 81 indicates an allowable amount of time for delaying the read frame signal 101 from the input frame signal 3, and when the time allowable amount is exceeded, the following correction means is executed. Reference signal for the

When the phase of the window pulse 81 matches the phase of the reset pulse 51, that is, when the reset pulse 51 overlaps while the window pulse 81 is at the low level, the window comparison circuit 6 generates the reset pulse 61. Do not output to the counter circuit 7 (FIG. 2
At time t2), conversely, the window pulse 81
If the reset pulse 51 does not overlap with the reset pulse 51, the reset pulse 61 is output to the counter circuit 7 as it is (FIG. 2).
Pulse 201), the count data of the counter circuit 7 is reset.

In the read frame signal generating circuit 10, based on the address signal 71 from the counter circuit 7, a memory address for reading data from the built-in memory in which the data of the input signal 2 has been written by the frame aligner circuit 9 is designated. The read frame signal 101 is generated and output. The frame aligner circuit 9 uses the internal clock 4 from the memory address designated by the read frame signal 101.
In step 1, the read address is incremented, data is sequentially read from the built-in memory in which the data of the input signal 2 is written, and output as an output signal 11.

As described above, since the active width of the window pulse 81 is created from the address signal 71 that determines the read frame signal 101, the active width of the reset pulse 51 generated in synchronization with the input frame signal 3 and the window pulse 81 are determined. If the active periods do not match, it means that the phase difference between the read frame signal 101 generated inside the device and the input frame signal 3 has become larger than a predetermined value, and at this time, the read frame signal 101 is generated. The counter circuit 7 that outputs the address signal 71 is reset so that the phase difference between the input frame signal 3 and the read-out frame signal 101 does not exceed a certain value.

In the above example, one PCM terminal device with a frame aligner circuit is shown, but a plurality of PCM terminal devices with a frame aligner circuit are arranged in parallel, and each PCM terminal device with a frame aligner circuit is arranged. The apparatus may be such that the station apparatuses synchronize between frames of the reproduction output signal. In that case, each read frame signal 101
In order to achieve the synchronization, a signal for achieving synchronization may be input to the readout frame signal generation circuit 10 or a circuit that is directly input to the frame aligner circuit 9 may be used.

[0039]

The read frame signal 101 generated in synchronization with the internal clock generated for the apparatus from the input clock separated and extracted from the transmitted multiplex signal is completely asynchronous with the input frame signal 3. In the past, the phase difference between the two signals was irregular, but according to the present invention, the phase difference between the two signals can be suppressed to a predetermined value or less, and external data due to the inability to synchronize the frame. The state in which data cannot be exchanged with the terminal can be avoided.

In addition, the built-in memory having a sufficient capacity required for frame synchronization in the related art can be made smaller.

Thus, a PC with a frame aligner circuit
The manufacturing cost of the M terminal device can also be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is an operation timing chart of one embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional frame aligner.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input clock signal 2 input signal 3 input frame signal 4 phase synchronization oscillator 5 reset pulse generation circuit 6 window comparison circuit 7 counter circuit 8 window pulse generation circuit 9 frame aligner circuit 10 readout frame signal generation circuit 11 output signal 41 internal clock 51 Reset pulse 61 Reset pulse 71 Address signal 101 Read frame signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 3/06 H04L 7/08 H04Q 11/04 301

Claims (2)

(57) [Claims] 1. A DSP for extracting a transmission timing signal from a PCM multiplex signal transmitted through a transmission path, outputting the transmission timing signal as an input clock, and outputting an input signal and an input frame signal. A frame aligner circuit for synchronizing the frame phase of the PCM multiplex signal transmitted to the PCM terminal, and a PCM terminal device with a frame aligner circuit having a phase synchronization oscillator for generating an internal clock for the device synchronized with the input clock. A reset pulse generation circuit for synchronizing an input frame signal with the internal clock to generate a reset pulse; a counter circuit for generating an address signal for synchronizing the device from the internal clock; and the frame aligner from the address signal Read frame signal for reading the internal memory of the circuit A read-out frame signal generating circuit that generates a window pulse generating circuit that generates and outputs a window pulse that is active for a predetermined period of time from the address signal; A window comparison circuit for controlling the output; writing the data of the input signal into the internal memory using the input frame signal and the input clock signal; and storing the internal signal with the read frame signal and the internal clock. A frame aligner circuit for reading data from a memory and outputting the read data; and a PCM terminal device with a frame aligner circuit. 2. A digital signal processing step of extracting a transmission timing signal from a PCM multiplex signal transmitted through a transmission path, outputting the transmission timing signal as an input clock, and outputting an input signal and an input frame signal. Generating a synchronized internal clock for the device, and transmitting the transmitted P to the frame phase for the device.
A frame aligner method for synchronizing a frame phase of a CM multiplex signal, wherein the input frame signal is synchronized with the internal clock to generate a reset pulse, and a read from the internal clock is performed to read data in a memory area. Generating an address signal for generating a window pulse that is active for a predetermined time from the address signal; and comparing the window pulse with the reset pulse to reset the read address signal. And writing the data of the input signal to the memory area using the input frame signal and the input clock signal, and reading data from the memory area with the read frame signal and the internal clock. Output Frame aligner wherein.