JP3031249B2 - Parallel data phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel data phase synchronizing circuit, and more particularly to a parallel data phase synchronizing circuit for synchronizing parallel data by absorbing a delay time difference in a transmission line and a difference in data transfer speed between an input side and an output side. The present invention relates to a data phase synchronization circuit.

[0002]

2. Description of the Related Art In general, in parallel data transmission, a delay time difference between respective transmission lines for transmitting each of these parallel data and a difference in data transfer speed between an input side and an output side are absorbed. It is necessary to synchronize phases between parallel data. In particular, in a data transfer method between clusters of parallel computers, phase synchronization between the parallel data is required.

An example of such a phase synchronization circuit between parallel data is disclosed in Japanese Patent Application Laid-Open No. 3-149331. In this example, a FIFO memory of a first-in first-out method is used as hardware for absorbing a difference in data transfer speed between an input side and an output side. A block diagram of this circuit is shown in FIG.

Referring to FIG. 6, between a transmitting circuit 1 and a receiving circuit 2, n (n is an integer of 2 or more) parallel data may be transferred via each of transmission lines 121 to 12n. It is shown. The transmission circuit 1 includes n CMI encoding units (COD) 101 to 10n, n transmitters (TR) 111 to 11n, and a frame generation unit (FGN) 10 that generates a frame signal for each cycle T. The data to be transferred is supplied in parallel to the input terminals SD1 to SDn in synchronization with the clock CK1.

The receiving circuit 2 includes n receivers (RC) 21
To 2n and n bit synchronization units (BSYN) 31 to 3n
And n CMI decoding units (DEC) 41 to 4n, and n
N phase synchronizing units (PSYNs) 51 to 5n, decode n n CMI coded signals received from the transmission lines 121 to 12n, and after synchronizing with each other by the clock CK2, n parallel The data is output as data RD1 to RDn.

In the transmission circuit 1, n parallel data are CMI-encoded by the CMI encoding units 101 to 10n at the frequency of the clock CK1, and are transmitted by the transmitters 111 to 11n.
Is output to each of the transmission lines 121 to 12n via the respective transmission lines. At this time, the frame generation unit 10 generates a frame signal every period T in synchronization with the frequency of the clock CK1, and outputs the frame signal to the encoding units 101 to 10n.

In the receiving circuit 2, the parallel CMI codes input from the transmission lines 121 to 12n are received by the receivers 21 to 2n, respectively, and supplied to the bit synchronization units 31 to 3n, respectively.
The bit synchronization units 31 to 3n output parallel data while synchronizing with the clock CK2 for each bit. These bit-synchronized parallel data are output to the CMI decoding units 41 to 4.
n are converted into NRZ signals, respectively, and
To 5n.

The phase synchronizers 51 to 5n all have the same configuration, and FIG. 7 shows a block diagram of the phase synchronizer 51.
Referring to FIG. 7, the phase synchronization unit 51 includes a synchronization protection circuit (SGD) 511 and a write counter (WCN) 512.
, A read counter (RCN) 513, and a FIFO memory 514.

Write and read counters 512, 5
Numeral 13 is initially set to different initial values "eH" and "gH" depending on the frame signal protected for synchronization. The FIFO memory 514 writes the output data from the decoding unit 41 to the address generated from the write counter 512 every cycle of the clock CK2, and outputs the memory contents from the address generated from the read counter 513.

With the above configuration, the transmission lines 121 to 12n
In the above, all the parallel data having different phases can be output as the same phase. For details of the synchronization protection circuit 511, refer to the above publication.

[0011]

In the conventional circuit shown in FIG. 6, in order to match the phase between n pieces of parallel data, N
Since the RZ signal is once converted into a CMI code and the skew between each data is measured based on the coding rule,
Since a CMI encoding unit and a CMI decoding unit are required for each data, there is a problem that the amount of hardware increases.

[0012] Further, since the transfer data is CMI-encoded, the transfer frequency is doubled, so that the transmission efficiency on the transmission line is reduced, which is not suitable for high-speed data transfer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel data phase synchronization circuit suitable for high-speed data transfer while absorbing skew caused by a transmission path between parallel data with a simple configuration.

[0014]

According to the present invention, a plurality of frame-formatted parallel data, each containing a synchronization signal, are transmitted by a corresponding transmission line, and the transmission between the received parallel data is transmitted. What is claimed is: 1. A parallel data phase-locked loop circuit which derives output parallel data synchronized with each other by absorbing delay fluctuations, comprising a plurality of FIFOs provided corresponding to each of the reception parallel data and capable of writing and reading corresponding reception parallel data. a memory, a plurality of write control means for respectively generating each write control timing signals of the memory by detecting the synchronization signal of each of the received parallel data,
At the timing after detecting the first signal of the write control timing signal and delaying it for a predetermined period from the first signal ,
Read control means for generating a read enable signal for commonly enabling all reading of the memory , thereby obtaining a parallel data phase locked loop circuit.

[0015] The read control means is characterized in that a predetermined delay time is set as the predetermined time.

Further, the read control means has time difference detection means for detecting a time difference between the first and last signals of all write control timing signals of the write control means, and the time difference is defined as the predetermined time. It is characterized by having such a configuration.

Further, according to the present invention, a plurality of frame-formatted parallel data, each including a synchronization signal, are transmitted by a corresponding transmission path to absorb a transmission delay variation between these received parallel data transmitted. A parallel data phase-locked loop derived as output parallel data phase-synchronized with each other, comprising a plurality of FIFO memories provided corresponding to each of the reception parallel data and capable of writing and reading the corresponding reception parallel data; and A plurality of write control means for detecting a synchronization signal of each of the received parallel data and generating a respective write control timing signal of the memory ; and a time difference between the first and last signals of the synchronization signal. and time difference detecting means for detecting, from the timing of the first signal generated in the memory after a delay time corresponding to the time difference Parallel data phase locked loop circuit characterized in that it comprises Te and read control means for generating a read enable signal to enable a common reading is obtained.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention will be described. Each of the parallel transmission data is formatted into a frame including a synchronization signal, and the receiving side detects the synchronization signal to calculate a maximum phase difference between the detected synchronization signals. Based on this, the read timing of the FIFO memory is determined so as to absorb the phase synchronization between the parallel data.

Instead of the maximum phase difference, a predetermined delay time may be added to the timing of the synchronization signal detected first, and the read timing of the FIFO memory may be determined.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the whole system showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a transmission unit, and reference numerals 111 to 11n denote transmission circuits which input and transmit each transmission data TXD1 to TXDn in synchronization with a clock TCLK1. Reference numeral 2 denotes a receiving unit, and 131 to 13n
Is a receiving circuit that receives transmission data from the transmission unit 1 and extracts a clock component from the data, and 141 is an inter-data synchronization circuit that synchronizes each data with a clock TCLK2. Reference numerals 121 to 12n denote transmission paths connecting the transmission unit 1 and the reception unit 2.

The frame format of the transmission data is shown in FIG.
As shown in (1), it comprises a synchronization signal SYNC and a valid data section, and is synchronized with the clock TCLK1 of the transmission section 1. Transmission data TXD1 to TXDn are output to transmission paths 121 to 12n through transmission circuits 111 to 11n for each byte.

This data is received by the receiving circuits 131 to 131 of the receiving section 2.
13n, and when the synchronization signal is received at a prescribed period, the synchronization detection flag SYNCIN and the reception data R
DI, and a reception clock RCLK extracted from the reception data.
Are output to the inter-data synchronization circuit 141.

FIG. 2 is a block diagram of the inter-data synchronization circuit 141 which is a feature of the present invention. In FIG.
21n is a write control circuit for controlling the writing of data to the FIFO memories 231 to 23n for each data.
Reference numerals 1 to 22n denote write start detection circuits for detecting that data has been written to the FIFO memories 231 to 23n.

231 to 23n are FIFs for holding data
O memory. 241 indicates which of the n pieces of data is the first
An inter-data write detection circuit for detecting whether data has been written to the O memory, 251 a read control circuit for controlling the reading of data from the FIFO memory, and 261 a read address RADR of the FIFO memory and a read clock RCLK
Is a read address counter.

The operation of the embodiment of the inter-data synchronization circuit will be described in detail. The reception data RDI1 to RDIn output from the reception circuits 131 to 13n are synchronized with the reception clock RCLK of each data. Receive clock RCLK1
RCLKn have the same frequency as the clock TCLK1 of the transmitting unit 1 and have different phases for each data.

By receiving the synchronization detection signal SYNCIN, the write control circuits 211 to 21n generate a write clock WCLK to the FIFO memory. Based on this write clock, the write address counter in the write control circuit is operated to generate a write address WADR to the FIFO, and the FIFO memories 231 to 231 of the specified address are generated.
The reception data RDI is written into address 23n in order from address 0. The write address counter is reset upon receipt of the synchronization detection flag and operates during reception of valid data.

The write detection circuits 221 to 22n detect that the value of the write address counter in the write control circuit has become "1" (address 1) and output a write start flag WSTF. The indication of 1, 2, 3 in the data section of the time chart of FIG. 3 indicates the address.

The above operation is performed in synchronization with the reception clock of each data. That is, data operates asynchronously and independently.

Next, the read operation will be described. The data output from the transmission unit reaches the reception circuit via transmission circuits 111 to 11n and transmission paths 121 to 12n such as optical fibers and electric cables. However, even if these are designed under the same conditions, manufacturing variations may occur. This causes a difference in delay time between the respective data, which results in skew. The maximum value of the delay time difference is estimated in advance from the specifications of the transmission circuit, the transmission line, and the like, and this is set as the skew T1 time.

The logical sum (OR) of the write start flag WSTF output from the write start detection circuit for each data is taken by the inter-data write start detection circuit 241 and is used as one of the n data. Detects whether data has been written and outputs (BWST
F).

In the read control circuit 251, after the first write is detected by the inter-data write detection circuit, the read control signal 251 is delayed by T1 of the skew value estimated in advance, and the read enable signal RE is output.
Enable. While the read enable signal is enabled, the read clock RCLK is output, and the read address counter 261 is operated in synchronization with the read clock. The read address is common to all data.

In synchronization with the read clock, reading from the register of the same designated address among all data is simultaneously started. The read clock is the clock TC of the receiver 2.
LK2 has the same frequency as the clock TCLK of the transmitting unit.
There is no operational problem even if it is different from 1.

With the above operation, in n parallel data transfers in which the clock frequencies of the transmitting unit and the receiving unit are different,
It is possible to synchronize the data having different phases among the data with one transmission clock and to match the start of the data. FIG. 3 shows a time chart of these operations.

Next, a second embodiment will be described with reference to FIG. In the first embodiment, the skew T1 between data
Has been estimated in advance from the specifications of the transmission circuit, the transmission line, and the like. This method has a problem that when the actual skew is sufficiently smaller than the estimated skew T1, an extra delay occurs, and the data transfer throughput decreases. In order to solve the problem, a skew measurement circuit 271 is added instead of the data write detection circuit 241 and the read control circuit 251 of FIG.

FIG. 5 is a block diagram of the skew measuring circuit 271. Reference numeral 401 denotes a time difference detection circuit for detecting a delay time difference between data, 402, a counter circuit for setting a delay time, and 403, a counter circuit 40.
2 is a delay generating circuit for generating a delay based on the output of the second circuit.

Next, the operation of the skew measuring circuit 271 will be described. The time difference detection circuit 401 detects a difference in arrival time between the earliest and latest write start flags WSTF1 to WSTFn of each data, and outputs a high level during that time. The counter circuit 402 operates the counter and counts up while the output of the time difference detection circuit 401 is at a high level.

In the delay generation circuit 403, the counter circuit 40
The number of flip-flop stages passing from the counter value of 2 is set by the selector, and after a delay of the skew time measured from the start of the first write, the read enable signal is enabled, and the same read operation as in the first embodiment is performed.

With the above operation, it is possible to set an optimum delay time that matches the actual skew time.

The write start flags WSTF1 to WSTFn are input to the time difference detection circuit 401 shown in FIG. 5 to detect the time difference between the first and last of these, but the synchronization detection signals SYNCIN1 to SYNCIN are used.
Similar processing may be performed using Nn as an input.

[0041]

The first effect is that the parallel data of a plurality of asynchronous data can be transmitted in synchronization with one clock, and the start of data between the data is made coincident. The reason is that the read operation is started after the skew time between data is delayed by using the FIFO memory.

A second effect is that synchronous transmission of parallel data can be realized with a smaller amount of hardware than in the prior art. The reason is that encoding of transmission data, which is performed in the related art, is not performed.

A third effect is that the transmission efficiency is increased as compared with the prior art. The reason for this is that, similarly to the second effect, the encoding of the transmission data performed by the conventional technique is not performed.

A fourth effect is that a delay time from data writing to data reading can be minimized.
The reason is that the skew measurement circuit automatically measures the skew between actual data and determines the delay time until reading based on the result.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing details of an inter-data synchronization circuit 141 of FIG. 1;

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 5 is a block diagram of a skew measurement circuit.

FIG. 6 is a diagram illustrating the operation principle of the related art.

FIG. 7 is a block diagram of a phase synchronization unit PSYN of FIG. 6;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission unit 2 reception unit 111 to 11n transmission circuit 121 to 12n transmission line 131 to 13n reception circuit 141 to 14n data synchronization circuit 211 to 21n write control circuit 221 to 22n write start detection circuit 231 to 23n FIFO memory 241 data Inter-write detection circuit 251 Read control circuit 261 Read address counter 271 Skew measurement circuit 401 Time difference detection circuit 402 Counter circuit 403 Delay generation circuit

Claims (4)

(57) [Claims] 1. A plurality of frame-formatted parallel data, each including a synchronization signal, are transmitted by a corresponding transmission path, and transmission delay fluctuations between these transmitted reception parallel data are absorbed to perform phase synchronization with each other. A parallel data phase-locked loop derived as output parallel data, comprising a plurality of FIFO memories provided corresponding to each of the reception parallel data and capable of writing and reading corresponding reception parallel data.
Mori and said detecting each synchronization signal of the received parallel data menu
A plurality of write control means for respectively generating each write control timing signals Mori, by detecting the first signal of the write control timing signal at a timing after a predetermined period delayed from the first signal
A read control means for generating a read enable signal for commonly enabling all reading of the memory ; and a parallel data phase synchronization circuit. 2. The parallel data phase synchronization circuit according to claim 1, wherein said read control means is configured to set a predetermined delay time to said predetermined time. 3. The read control means has a time difference detection means for detecting a time difference between a first signal and a last signal of all write control timing signals of the write control means,
2. The parallel data phase synchronization circuit according to claim 1, wherein said time difference is set to said predetermined time. 4. A plurality of frame-formatted parallel data, each including a synchronization signal, are transmitted by a corresponding transmission path, and transmission delay fluctuations between these received parallel data transmitted are absorbed to achieve phase synchronization with each other. A parallel data phase-locked loop derived as output parallel data, comprising a plurality of FIFO memories provided corresponding to each of the reception parallel data and capable of writing and reading corresponding reception parallel data.
Mori and said detecting each synchronization signal of the received parallel data menu
A plurality of write control means for respectively generating each write control timing signals Mori, and time difference detection means for detecting a time difference between the first and last signals generated among the synchronizing signal the synchronizing signal, the first generated And a read control means for generating a read enable signal for commonly enabling all reading of the memory after a delay time corresponding to the time difference from the timing of the signal.