JP2723078B2 - Asynchronous data transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous data transmission circuit, and more particularly, to a reception clock and a reception clock which transmit N data signal trains in synchronization with a transmission clock and which are asynchronous in frequency with the transmission clock. The present invention relates to an asynchronous data transmission circuit that receives a data signal sequence using a reception control signal for final call synchronized with a clock.

[0002]

2. Description of the Related Art Conventionally, this type of asynchronous data transmission circuit has been known to transmit alarm information and control information composed of a plurality of data signal strings output in synchronization with a transmission clock of a transmission line with a clock of the transmission line. Is used for monitoring and detection using an asynchronous clock. In the case of this type of circuit, it is sufficient to detect the data signal sequence at the time when the paging reception control signal synchronized with the reception clock is input, and the transmission amount of the transmitted data signal sequence is not necessarily between the transmission side and the reception side. It does not need to match exactly. However, if the transmission data signal sequence synchronized with the transmission clock is latched by the reception clock that is asynchronous with the transmission clock, there is a possibility that the change point of the transmission data may be captured, and the meaningful information in the mutual relationship of the multiple data signal sequences may be incorrect. May be detected
A protection circuit or the like having a function of eliminating erroneous detection data is required.

Further, a plurality of reception clocks having different phases are prepared, and the phases of the transmission clock and the reception clock are detected, and the reception clock is switched (Japanese Patent Laid-Open No. 4-1 / 1991).
There is also a configuration in which the change point of the transmission data is not latched by using the repetition frequency of the transmission clock and the reception clock, and only the bit phase needs to be matched. The circuit to be applied.

Next, the prior art will be described with reference to the drawings. FIG. 4 is a diagram showing an example of a conventional asynchronous data transmission circuit, and FIG. 5 is a timing chart for explaining the operation of FIG. In FIG. 4, for simplicity of description, the description will be made with four data signal strings to be transmitted, and the values of the data signal string to be transmitted will use the values shown in FIG.

In FIG. 4, transmission data signal strings 101 to 1
Numeral 04 denotes a transmission data latch circuit 1-1 to 1-1 which is constituted by a D-type flip-flop (hereinafter referred to as DF / F).
4 are latched at the rising edge of the transmission clock 200, and are transmitted as transmission data signal strings 111 to 114 in FIG.
Sent out as shown in -c).

[0006] Next, on the receiving side, the received data latch circuits 7-1 to 7-4 constituted by DF / Fs are shown in FIG.
The output transmission data signal sequences 111 to 114 of the transmission data latch circuits 1-1 to 1-4 are latched using the rising edge of the reception clock 200 shown in FIG. 5D which is asynchronous with the transmission clock shown in FIG. , And receive asynchronous data signal trains 171 to 174. At this time, the transmission data signal trains 111 to 114 and the reception clock 210
Are asynchronous, the data signal sequence latched by the reception data latch circuits 7-1 to 7-4 is shown in FIG.
At the timings shown in (1) and (2), the changing points of the transmission data signal strings 111 to 114 are latched.

At this time, the data value changes due to the characteristics of the reception data latch circuit that latches each transmission data signal sequence by the reception clock and the difference in the wiring length from the transmission data latch circuit to the reception data latch circuit. It is uncertain which value should be taken before or after the change of the data signal sequence. Therefore, as shown in FIG.
At the timing of (1), the transmission data signal sequence 11
Since the values of 1, 113 and 114 have changed, the received asynchronous data signal train 17 of the output of the received data latch circuit has been changed.
1 to 174 are “0000”, “0001”, “001”
0 ”,“ 0011 ”,“ 1000 ”,“ 1001 ”,
Eight possibilities of “1010” and “1011” exist.

Similarly, at the timing shown in FIG. 5B, since the values of the transmission data signal strings 111 and 114 change, the output reception asynchronous data signal strings 171 to 174 of the reception data latch circuit become “0100”, “0
101 "," 1100 ", and" 1101 ".

As described above, the reception data latch circuit 7-1
7-4 received asynchronous data signal trains 171 to 17-4
4 is a reception data protection circuit 8 which contains erroneous information.
Is input to

The reception signal control circuit 5 receives the reception clock 2
A final read pulse 410 for reading a reception latch data signal sequence from the reception control signal 400 synchronized with the reception clock 200 and the reception clock 200 is output to the reception data protection circuit 8.
The reception data protection circuit 8 monitors and receives the temporally consistent data of the reception asynchronous data signal strings 171 to 174 including erroneous information using the reception clock 210 and the final read pulse 410. By performing protection processing such as continuous coincidence reception, an erroneous data signal sequence is excluded, and final received data signal sequences 131 to 134 are output.

[0011]

In the above-mentioned conventional asynchronous data transmission circuit, a reception data protection circuit is provided because there is a possibility that an error has occurred in a reception asynchronous data signal sequence output from the reception data latch circuit. Therefore, it is necessary to determine the continuous coincidence of the final received data using the final read pulse and the received clock of the output of the received signal control circuit, and to output the data after protection is performed. However, there is a problem that the detection of the final received data signal sequence may be delayed depending on the processing time of the protection circuit.

Further, a configuration is provided in which a plurality of reception clocks having different phases are prepared, the phase of the transmission clock and the phase of the reception clock are detected, and the reception clock is switched so that a change point of the transmission data is not latched. Because the transmission clock and the reception clock are asynchronous, the phase of the transmission clock and the phase of the reception clock always change, so that a large number of reception clock phases are required to receive the data signal sequence without error. In addition, there has been a problem that not only the circuit configuration becomes complicated but also the circuit scale increases.

An object of the present invention is to provide an asynchronous data transmission circuit capable of accurately receiving transmission data with a reception clock asynchronous with a transmission clock without causing an error.

It is another object of the present invention to provide an asynchronous data transmission circuit capable of receiving and outputting transmission data by an asynchronous read signal having an arbitrary phase and period without causing an error.

Another object of the present invention is to provide an asynchronous data transmission circuit capable of accurately receiving and outputting transmission data with a simple configuration.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is to transmit N (N: an integer of 2 or more) transmission data using a reception clock having a period t smaller than the transmission clock period T of the transmission data. In the receiving asynchronous data transmission circuit, N data transition point detection circuits (data transition points) which detect a transition point of each data signal and output a detection pulse signal of a predetermined width r (t <r <T) from the data transition point An information generation circuit 2), an OR circuit (NOR23) for obtaining an OR of each output of the detection pulse signal, and a synchronization circuit (data change information detection circuit 3) for synchronizing the output of the OR circuit with a reception clock. , Sampling and outputting each of the N received data signals by the output of the synchronization circuit.
And an asynchronous data receiving circuit (latch circuit 4).

The present invention also provides a reception signal control circuit which receives a reception control signal and outputs a read pulse (final read pulse 410) having a trigger timing different from the synchronization timing of the synchronization circuit in synchronization with the reception clock; An output circuit (final data latch circuit 6) for sampling the outputs of the N asynchronous data receiving circuits by the read pulse and outputting the received data is provided.

Further, the present invention has at least one of the following items.

(1) It has N input circuits (latch circuits 1-1 to 1-4) for sampling transmission data by a transmission clock and outputting the transmission data.

(2) The data change point detection circuit (data change information generation circuit 2) includes a delay circuit that delays the transmission data, and an exclusive logic circuit that receives the transmission data and the output of the delay circuit as inputs. Sum circuit (EX-OR22-
1 to 22-4).

(3) The synchronous circuit is constituted by a first latch circuit (latch circuit 3) for latching the output of the OR circuit by the received clock, and the asynchronous data receiving circuit converts the transmission data into the asynchronous data. It is composed of second latch circuits (latch circuits 4-1 to 4-4) that latch by the output of the first latch circuit.

(4) The output circuit is composed of N latch circuits (latch circuits 6-1 to 6-4) which latch the outputs of the N asynchronous data receiving circuits by the read pulse.

Further, as more specific means of the present invention,
A transmission data latch circuit for latching the transmission data signal sequence with the transmission clock and outputting the transmission data signal sequence, and detecting a change point of the output transmission data signal sequence of the transmission data latch circuit for a time longer than a period of a reception clock described later. A data change information generating circuit that outputs data change information, a data change information detecting circuit that samples output data change information of the data change information generating circuit with a reception clock, and outputs a detection result as a data change detection pulse; An asynchronous data reception circuit that latches an output transmission data signal sequence of the transmission data latch circuit using an output data change detection pulse of a change information detection circuit and outputs a reception synchronization data signal sequence synchronized with a reception clock; and The received data signal train is wrapped in accordance with the reception control signal synchronized with the reception clock. A reception signal control circuit for generating and outputting a final read pulse to be output, and an output reception synchronization data signal sequence of the asynchronous data reception circuit latched by the output final read pulse of the reception signal control circuit and output as a final reception data signal sequence. It has a final data latch circuit.

[0024]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of the present invention.
The outline of this configuration example is as follows: a transmission data latch circuit 1 for inputting parallel transmission data; a data change information generation circuit 2 for synchronizing the latched data with a reception clock; a data change information detection circuit 3; An asynchronous data reception circuit 4, a reception signal control circuit 5 and a final data latch circuit 6 for outputting reception data at an arbitrary reception cycle.
It is composed of

FIG. 2 is a block diagram showing an embodiment embodying the above block diagram, and FIG. 3 is a timing chart for explaining the operation of the asynchronous data transmission circuit of FIG.

2 and 3, for the sake of simplicity, the description will be made assuming that four parallel data signal strings are transmitted, and the values of the data signal strings to be transmitted use the values shown in FIG. I do.

In FIG. 2, transmission data signal strings 101 to 104 shown in FIG.
-F / F).
At 1-4, the data is latched at the rising edge of the transmission clock 200 shown in FIG.
1 to 114 are transmitted as shown in FIG.

The data change information generation circuit 2 includes a delay circuit 21
-1 to 21-4, EX-OR circuits 22-1 to 22-4, and a NOR circuit 23. The output transmission data signal sequences 111 to 111 of the transmission data latch circuits 1-1 to 1-4. 114 is delayed by the delay circuits 21-1 to 21-4 as shown in FIG. 3D) for a time longer than the period of the reception clock described later, and then the EX-OR circuits 22-1 to 22-
4 and the logic of the transmission data signal trains 111 to 114 and the logic of the NOR circuit 23, the low level of the delay time of the delay circuit from the output transmission data change point of the transmission data latch circuit is obtained. The pulse change information 300 that becomes “L” is output as shown in FIG.

Next, on the receiving side, the data change information detecting circuit 3 composed of DF / F
At the rising edge of 10, the output data change information 300 of the data change information generation circuit 2 is sampled and output as a data change detection pulse 310. At this time, since the pulse width of the "L" state of the output data change information 300 is longer than the receiving clock cycle, the receiving clock 210
It does not disappear even if sampling is performed at
As shown in g), a data change detection pulse 310 is output.

The asynchronous data receiving circuits 4-1 to 4-4 receive the transmission data signal train 1 at the rising edge of the output data change detection pulse 310 of the data change information detection circuit 3.
11 to 114 are latched and the reception synchronization data signal trains 121 to 114 are latched.
124 is output. At this time, the rising edge of the data change detection pulse 310 corresponds to the transmission data signal train 1
Since there is a sufficient time interval from the transition points 11 to 114, as shown in FIG.
There is no latching of the change points 1-114.

The reception signal control circuit 5 receives the reception clock 2
10 and a reception control signal 400 having a desired read cycle synchronized with the reception clock, and a final read pulse synchronized with the falling timing of the reception clock 210 shown in FIG. The final data latch circuits 6-1 to 6-4 composed of DF / Fs output the output received synchronous data signal streams 121 to 124 of the asynchronous data receiving circuits 4-1 to 4-4 to the reception signal control circuit 5 respectively. And outputs the final received data signal strings 131 to 134 shown in FIG.

While the embodiment of the present invention has been described in detail, the outline of the above circuit operation will be summarized and described.

The transmission data latch circuit 1 latches, for example, a transmission data signal sequence 10n arriving via a transmission path or the like by a transmission clock, and detects and outputs the transmission data signal sequence 11n.

The data change information generation circuit 2 generates a pulse signal of a constant width from the change point of each data in the transmission data signal sequence 11n and outputs it as a data change point detection signal 300. Since the pulse signal 300 is not synchronized with the reception clock, the data change information detection circuit 3 synchronizes the pulse signal 300 with the reception clock 210 and generates a data change point detection pulse 310.

The asynchronous data receiving circuit 4 samples the transmission data signal sequence 11n at the rising timing of the reception clock by the data change point detection pulse, and sends out the data signal sequence 12n synchronized with the reception clock.

Furthermore, the final data latch circuit 6 samples the data signal sequence 12n already synchronized with the reception clock at the same or different reception timing with respect to the transmission clock period and sends out the reception data signal sequence 13n.

The reception control signal circuit 5 synchronizes with the reception clock based on the reception control signal 400 having the same cycle as the transmission clock as in the embodiment, and gives the data signal train 12n to give the reception timing. A final read pulse 410 having a trigger point at which there is no risk of coincidence with the change point of the received clock, for example, the falling point of the received clock, is output.

Since the data change information generation circuit 2 of the present invention is configured to detect the conversion point of the transmission data, if any of the plurality of transmission data changes every clock cycle, this will be the asynchronous data reception circuit 4. , The data is latched and received in synchronization with the reception clock, but if none of the data changes, no new data latch is performed. In this case, the latch circuit holds the state of the previous data.

In one embodiment of the present invention, the transmission data latch circuit 1 is provided on the input side to detect and reproduce the transmission data signal accurately at the correct timing. A final data latch circuit 6 and a reception signal control circuit 5 are provided so that data can be output at a desired read pulse cycle requested by a device or the like.
The synchronization of the transmission data with the reception clock as an asynchronous data transmission circuit is realized by the configuration of the data change information generation circuit 2, the data change information detection circuit 3, and the asynchronous data reception circuit 4, and Obviously, the input and output circuits can be variously modified.

[0040]

As is apparent from the above description,
According to the asynchronous data transmission circuit of the present invention, a detection pulse of a data change point which is synchronized with a reception clock and does not sample (latch) a change point of a transmission data signal sequence is generated and used. There is no possibility that an error based on sampling of a change point occurs in the received data signal sequence of the asynchronous data reception output.

That is, the present invention controls the sampling timing so that the data change time of the transmission data signal does not coincide with the latch time, so that an indefinite transmission data portion is not output. This is extremely advantageous in that the circuit configuration is complicated and there is no need to use a protection circuit or the like having a function of determining continuous coincidence of received data, which causes a delay in data output.

Further, according to the asynchronous data transmission circuit of the present invention, there is a remarkable effect in that data can be output without error by a readout signal having an arbitrary phase and period asynchronous according to the request of the output side as the final output. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the present invention.

FIG. 3 is a timing chart for explaining an operation of the asynchronous data transmission circuit of FIG. 2;

FIG. 4 is a block diagram illustrating an embodiment of a conventional asynchronous data transmission circuit.

FIG. 5 is a timing chart for explaining the operation of the asynchronous data transmission circuit of FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission data latch circuit 2 data change information generation circuit 3 data change information detection circuit 4 asynchronous data reception circuit 5 reception signal control circuit 6 final data latch circuit 7 reception data latch circuit 8 reception data protection circuit 21 delay circuit 22 EX-OR circuit 23 NOR circuit 101-104 Transmission data signal sequence 111-114 Transmission data signal sequence 121-124 Reception synchronous data signal sequence 131-134 Final reception data signal sequence 171-174 Reception asynchronous data signal sequence 200 Transmission clock 210 Reception clock 300 Data change Information 310 data change detection pulse 400 reception control signal 410 final read pulse

Claims (6)

(57) [Claims] 1. An asynchronous data transmission circuit that receives N (N: an integer of 2 or more) transmission data with a reception clock having a period t smaller than a transmission clock period T of transmission data. Width r (t <r
(T) N data transition point detection circuits that output detection pulse signals, an OR circuit that obtains a logical sum of the detection pulse signals, and a synchronization circuit that synchronizes the output of the OR circuit with a reception clock. , Sampling and outputting each of the N transmission data by the output of the synchronization circuit.
An asynchronous data transmission circuit comprising: a plurality of asynchronous data receiving circuits. 2. A reception signal control circuit for receiving a reception control signal and outputting a read pulse synchronized with the reception clock and having a trigger timing different from the synchronization timing of the synchronization circuit, and the N asynchronous signals are generated by the read pulse. 2. The asynchronous data transmission circuit according to claim 1, further comprising N output circuits for sampling an output of the data reception circuit and outputting received data. 3. The asynchronous data transmission circuit according to claim 1, further comprising N input circuits for sampling data by a transmission clock and outputting the transmission data. 4. A data change point detection circuit comprising: a delay circuit for delaying the transmission data; and an exclusive OR circuit that receives the transmission data and an output of the delay circuit as inputs. Claim 1, 2, or 3
An asynchronous data transmission circuit as described. 5. The synchronous circuit includes a first latch circuit that latches an output of the OR circuit in accordance with the received clock, and the asynchronous data receiving circuit stores the transmission data in the first latch circuit. 5. The asynchronous data transmission circuit according to claim 1, further comprising a second latch circuit that latches by an output. 6. The output circuit according to claim 2, wherein said output circuit comprises N output latch circuits for latching the outputs of said N asynchronous data receiving circuits by said calling pulse. Or the asynchronous data transmission circuit according to 5.