JP2512004B2 - Bit error rate measuring device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a code error measuring device for detecting and measuring a code error occurring in a code transmission system such as PCM communication,
In particular, the present invention relates to a code error rate measuring device using a signal having a variable mark rate made by an M-sequence pseudo-random signal as a test code.

(Prior Art) Conventionally, when measuring an error rate, an M-sequence pseudo-random generator, which can generate a code pattern with a mark rate of 1/2 close to an actual transmission line signal, is placed on the transmission side, and this code pattern is received. Send to measurement system. On the receiving side, as shown in FIG. 3, the data from the system under test is read into the internal shift register 2 of the M-sequence pseudo-random generator 1 having the same configuration as the transmitting side, and the reading operation is performed after synchronizing with the signal on the transmitting side. , And operated as an independent M-sequence pseudo-random generator, and compared with the input signal on a bit-by-bit basis to detect a code error. (Japanese Patent Publication No. 48-10885) This method (hereinafter referred to as the reading method) requires a relatively short time to pull in synchronization, and the test pattern is N
When a pseudo random pattern of stages is used, if there is no error in the input pattern, synchronization can be achieved with N bits, and the synchronization time does not change much depending on the number of stages of the pseudo random pattern.

On the other hand, in recent years, a high bit rate of PCM communication has progressed, and a logic circuit using a compound semiconductor such as GaAs has been developed, and an error rate measurement is performed to evaluate such a device alone or an apparatus incorporating them. When evaluating such an ultra-high-speed logic device or device by an error rate, it is not enough to use a conventional M-sequence pseudo-random signal with a mark rate of 1/2 as a test signal, and the randomness of the code is maintained and the mark rate is changed. Then, the error rate is measured under more severe conditions.

Therefore, the above-mentioned reading method cannot detect the code error of the test pattern whose mark ratio varies, and the method shown in FIG. 4 has been adopted. That is, in the transmitting unit 3, the pseudo random generation circuit 4 generates a pseudo random signal with a mark ratio of 1/2, and the output is added to the shift register 5. The number of stages of the shift register 5 is determined by the desired mark ratio. For example, when generating a pattern with a mark rate of 1/4, the shift register 5 has one stage and the mark rate is 1/8.
In case of generating the pattern, there are two stages. Since then mark rate
The case of 1/4 will be described. 1-bit delayed mark ratio 1 / shift register 1 input and shift register 1 stage
A pseudo random signal of 2 is added to the AND circuit 6 and the mark ratio is 1/4.
Get the signal of. On the other hand, the receiving section 7 comprises a reference pattern generator 11 including the same pseudo random number generator 8, shift register 9 and AND circuit 10 as the transmitting section 3, an error detecting circuit 12, a sync pull-in circuit 13 and a clock prohibiting circuit 14. Has been done. Marking rate from receiver 7 reference pattern generator 11 1/4
In order to synchronize the pseudo-random pattern with the same pattern input from the transmission unit 3, when the ratio of the error rate detected by the error detection circuit 12 is above a certain ratio, the clock added to the reference pattern is prohibited and The prohibition operation is released when the phases match and the error rate can be officially measured from this point. According to this method (hereinafter referred to as the clock prohibition method), the test pattern is not limited to a pseudo-random pattern with a mark rate of 1/2, and any pattern that has periodicity can be used for synchronization and error rate measurement. it can.

(Problems to be solved by the invention) However, in this clock prohibition method, the synchronization pull-in time required to synchronize the transmitting side pattern and the receiving side pattern becomes long in proportion to the repetition period of the test pattern. For example, if the mark ratios are the same, comparing the sync pull-in times of 15-step and 23-step pseudo-random patterns, it is 23
For stage 2 ²³ -1/2 ¹⁵ -1 ≒ 2 becomes ⁸ times longer than that of the 15-stage, consequently there is a disadvantage that the time required for error rate measurement becomes longer.

The present invention was devised to eliminate these drawbacks, and its purpose is to measure a mark rate of 1/2 ^m (or 1-1) made from a pseudo-random (2 ^N -1) signal as a test pattern in error rate measurement. / 2 ^m ) pattern (where N> m ≧ 1) can be used, and the synchronization pull-in time does not depend on the exponentiation of the number of stages of the pseudo-random pattern, and is shortened compared to the conventional clock prohibition method, resulting in extremely high performance. It is to provide an error rate detection method.

(Means for Solving Problems) A code error rate measuring apparatus according to the present invention comprises an M-sequence pseudo random pattern generator 24 having a (2 ^N -1) bit period and an output of the M-sequence pseudo random pattern generator. And a transmission side 1/2 ^m mark ratio pattern generating circuit 25 for generating a 1/2 ^m mark ratio pattern by taking the logical product of the m-phase bit-delayed data. Create a pattern with a mark ratio of 1/2 by creating m-phase bit-delayed data from the received signal from the system under test and the transmitter 21 that sends out a / 2 ^m mark ratio pattern and taking the logical sum of each data. Mark rate recovery circuit 28,
Read the output pattern of this mark ratio recovery circuit (2 ^N −
1) A synchronizing circuit 29 for synchronously reproducing an M-sequence pseudo random pattern having a bit period, and the transmitting side for generating a 1/2 ^m mark rate pattern from a pseudo random pattern with a mark rate of 1/2 output from this synchronizing circuit. and 1/2 ^m mark index pattern generator and the receiving side 1/2 ^m mark index pattern generator 34 of the same configuration, the code error from the output and the received pattern of the receiving-side 1/2 ^m mark index pattern generator The receiving unit 23 includes an error detection circuit 37 for detecting.

(Operation) According to the code error rate measuring device configured as described above,
1/2 ^m as a test signal from the transmitter to the system under test
The mark rate pattern is sent out. On the other hand, in the receiving section, the mark rate recovery circuit creates a pattern with a mark rate of 1/2 from the received signal through the system under test, and the synchronization circuit synchronizes the (2 ^N -1) bit synchronous M-sequence pseudo-random pattern Is played. Then, a 1/2 ^m mark rate pattern generation circuit on the receiving side generates a 1/2 ^m mark rate pattern, and an error detection circuit compares it with the received pattern to detect an error in the received pattern.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the code error rate measuring apparatus of the embodiment. In this embodiment, the test pattern transmitted from the transmitter 21 to the receiver 24 through the system under test 22 is set to a pseudo random pattern with a mark ratio of 1/8 (= 1/2 ³ , m = 3). Show.

That is, the transmitter 21 includes a mark rate 1 / 2M series pseudo-random pattern generator 24 and a mark rate 1/8 pattern generation circuit 25.
The mark rate is 1/8 pattern generation circuit 2
5 is composed of a two-stage shift register 26 and a logical product circuit 27, and the input of the logical product circuit 27 is delayed by 1 bit,
The pseudo random pattern signals 2a to 2c of the phases are added and the output 2d of the AND circuit 27, that is, the mark rate 1/8 pattern signal is obtained. FIG. 2 shows the waveforms 2a to 2d. From this waveform, the pulse is missing when there are two or less "1" continuations, and the preceding two bits are deleted when there are more than one.

The receiving section 23 receives the pattern signal and the clock signal from the system under test 22, and performs the synchronization and error detection operations. The receiving section 23 first performs a synchronous operation. This operation is performed by the mark ratio recovery circuit 28 and the synchronization circuit 29. The mark ratio recovery circuit 28 is composed of a two-stage shift register 30 and a logical sum circuit 31, and three-phase pseudo random pattern signals 4a to 4c delayed by one bit are added to the input of the logical sum circuit 31 to obtain a logical The sum output is 4d. FIG. 2 shows the waveforms 4a to 4d. Assuming that no error has occurred in the system under test 22, the waveform of 4d is compared with the mark rate 1/2 pseudo-random pattern before changing the mark rate on the transmitting side, and the number of consecutive "1" s is 3 or more. The places and zeros are faithfully reproduced. If this section continues for a number of pseudo random stages N or more, this section pattern is read into the pattern reading shift register 32 of the next synchronizing circuit 29 and synchronized. After synchronous pull-in, shift register 32 for pattern reading and exclusive OR circuit 33
To form a closed loop and an independent mark rate 1/2 pseudo-random pattern generator, which is added to the mark rate 1/8 pattern generation circuit 34. The synchronization control circuit 35 controls the switch 36 installed at the input of the pattern reading shift register 32, and includes the “0” pattern missing by the mark rate 1/8 pattern generation circuit 25 of the transmitter 21. Also, the section including the error pulse generated in the system under test 22 is input and the switch 36 is connected to the A side to perform the reading operation while the error rate is above a certain value. As soon as the error rate falls below a certain value, the switch 36 is switched to the B side so as to operate as an independent pseudo random pattern generator with a mark rate of 1/2.

The mark rate 1/8 pattern generation circuit 34 has the same configuration as the mark rate 1/8 pattern generation circuit 25 of the transmission unit 21, and obtains the mark rate 1/8 pattern signal synchronized with the pattern from the system under test 22. . The error detection circuit 37 has an input pattern,
An error is detected by bit matching the synchronized 1/8 pattern of mark rate. The error detection circuit 37 includes a shift register for delaying the reception pattern corresponding to the bit delay by the mark ratio recovery circuit 28 and the mark ratio 1/8 pattern generation circuit 34. Then, the error counting circuit 38 counts the number of error pulses detected by the error detecting circuit 37.

In FIG. 1, ^m of the mark rate 1/2 ^m is set to 3, but the number of stages of each shift register of each mark rate 1/2 ^m pattern generation circuit 25, 34 of the transmitter 21 and the receiver 23 is set. That is, it is possible to freely change the number of data fetch stages for the AND circuit by changing the number of stages with, for example, a change-over switch. In this case, the range of 1 ≦ m <N with respect to the number N of pseudo random patterns is sufficient.

Further, in the present embodiment, the mark rate 1/8 pattern generation circuit 25,
Although the delay of each pattern of each of the three phases of the 34 mark ratio recovery circuit 28 is set to 1 bit at a time, any value may be used as long as the circuits 25, 34 and 28 have the same bit.

Further, by providing a switch for the output of the multi-phase pulse of each circuit 25, 34, 28, it is possible to measure the error rate with variable mark rate. Further, for example, by reversing the respective output patterns can be created from a pattern of the mark ratio of 1/2 ^m the mark ratio of a pattern of (1-1 / 2 ^m).

Further, by combining the logical product circuit and the logical sum circuit, an arbitrary mark ratio such as 3/4 can be realized.

(Effects of the Invention) As described above, according to the present invention, it is possible to send and receive a test pattern signal having not only 1/2 but an arbitrary mark ratio to the system under test, so that the mark ratio can be improved. The error rate can be measured under varying and more severe conditions.

Further, by adopting the mark rate recovery circuit on the receiving side, the synchronization pull-in time is greatly shortened, and the test efficiency for the system under test is greatly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a code error rate measuring apparatus according to an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the same embodiment, and FIGS. 3 and 4 are conventional codes. It is a block diagram which shows an error rate measuring apparatus. 21 …… Sending section, 22 …… System under test, 23 …… Reception section,
24 …… Mark rate 1 / 2M series pseudo-random pattern generator,
25 …… Mark rate 1/8 pattern generation circuit, 28 …… Mark rate recovery circuit, 29 …… Synchronous circuit, 34 …… Mark rate 1/8 pattern generation circuit, 37 …… Error detection circuit, 38 …… Error count circuit.

Claims (1)

(57) [Claims] 1. A logical product of an M-sequence pseudo-random pattern generator (24) having a (2 ^N -1) bit period and an m-phase bit-delayed data received from the M-sequence pseudo-random pattern generator. 1/2 ^m mark ratio and a transmission-side 1/2 ^m mark rate pattern generating circuit for generating (25) a pattern, sends a 1/2 ^m mark index pattern to the measurement system (22) by taking A mark ratio recovery circuit that creates a pattern of m-phase bit-delayed pattern data from a received signal from the system under test and the logical sum of each data to create a pattern with a mark ratio of 1/2. (28), a synchronization circuit (29) that reads the output pattern of this mark ratio recovery circuit and synchronously reproduces an M-sequence pseudo random pattern having a (2 ^N -1) bit period, and the mark ratio output from this synchronization circuit. 1/2 pseudo-la The transmitting side for generating a 1/2 ^m mark ratio pattern from the dam pattern
1/2 ^m Mark rate pattern generation circuit same as receiving side 1/2 ^m
A receiver (23) including a mark rate pattern generation circuit (34) and an error detection circuit (37) for detecting a code error from the output of the reception side 1/2 ^m mark rate pattern generation circuit and the received pattern. A code error rate measuring device comprising: