SU613513A2 - Pseudorandom signal synchronizing device - Google Patents

Description

one

The invention relates to radio and can be used in space communications, radar systems for various purposes, and so on;

According to the main author. St. No. 423256, there is known a device for synchronizing pseudo-random signals, containing a discriminator at the input, to the inputs of which pseudo-random sequence generator outputs with a delay tracking circuit are connected, and a correlator, to one of the inputs of which additional outputs of the generator PSP are connected through an adder, and to the other input - directly the discriminator input.

However, in the known device, the timing of synchronization is significant.

The purpose of the invention is to reduce the time taken to synchronize.

To do this, a pseudo-random signal synchronization device containing a discriminator at the input, the inputs of which is connected to the outputs of the SRP generator with a delay tracking circuit, and a correlator, to one input of which additional outputs of the PRS generator are connected via an adder, and to another input - directly discriminator, a delay block is inserted between the corresponding outputs of the SRP generator and one of the inputs of the adder, and an additional output of the decisive is connected to the control input of the delay block block, and the adder is designed as a modulator two modulators.

The drawing shows a structural electrical circuit of the proposed device.

The device contains a discriminator 1 at the input, to the inputs of which the outputs of the PSP 2 generator with a delay tracking circuit are connected, and a correlator 3, to one input of which additional outputs of the PSP generator 2 are connected through the adder 4, and to the other input directly the discriminator 1 input a delay unit 5 connected between the respective outputs of the SRP 2 generator and one of the inputs of the adder 4, the auxiliary output of the decisive unit 6 being connected to the control input of the delay unit 5, and the adder 4 being designed as a modulo adder you two.

The device works as follows.

The control unit 7, together with the memory bandwidth generator 2, searches for the input signal delay, which can be performed by one of the known methods, for example, by tuning the clock pulse frequency or changing the bit status of the memory band register register. If the input signal matched the time delay with the reference signals supplied to the input

the discriminator 1, the decision block 6 puts the device into the accompanying input memory bandwidth mode. If the input signal coincides in time delay with any of the cyclically permutations formed at the output of adder 4 modulo two, then a correlation peak occurs at the output of the correlator 3. In the case of forming a reference signal of two pzs shifted by an amount multiple of 0.5 to, the input signal may coincide with one of the two X cyclic permutations. For the example used above, with permutations having 12to and 9to delays relative to the original sequence.

To determine with which permutation the input signal coincided, the decision block 6 sends to the delay block 5 a signal about reducing (within TO) the mutual time alignment of the reference signals at the input of modulator 4 modulo two and bringing it to the nearest multiple of the TO value (for example, instead of 1.5, a delay t is established. In this case, at the reference input of the correlator 3, one cyclic permutation of the bandwidth bandwidth is formed, namely, with a delay of 12 degrees. If the input signal coincides with this permutation, the signal at the output of the correlator 3 will double, if on the other, it will disappear completely.

Thus, the nature of the change in the output signal of the correlator 3 with a "test change in the delay of one of the unambiguous reference signals allows determining the delay of the input signal. Based on the comparison of the signs of the "test change of the delay and the change in this voltage at the output of the correlator 3, the decisive block 6, using the control block 7, sets the register of the PSP generator 2 to the state corresponding to the generation on the reference inputs of the discriminator 1 synchronous with the received one, and puts the device into synchronous tracking mode.

Claims (2)

1. Device for synchronizing pseudo-random signals by aut. St. No. 423256, characterized in that, in order to reduce the timing of synchronization, a delay block is inserted in it connected between the corresponding outputs of the pseudo-random sequence generator and one of the inputs of the adder, and an additional output of the decision block is connected to the control input of the delay block. 2. A device according to claim 1, characterized in that the adder is designed as a modulo two adder.