SU1092744A1 - Device for time synchronization of pseudorandom sequences - Google Patents

Abstract

1. A device clocked pseudorandom sequence comprising serially connected k.orrel torus, whose first input is the first input device, threshold unit, control unit and the search PN signal generator (ECP), whose first output is connected to the second input of the correlator, and also a switch and a serially connected discriminator and a controlled clock pulse generator, characterized in that, in order to shorten the clock synchronization time and rotation frequency Sheni precision tracking delay pseudorandom sequences introduced therein driver control pulses and a frequency divider, a first input of which is the second input device and the output of the frequency divider is connected to the first input switch, to the second and third. the inputs of which are connected respectively to the second input of the search control unit and the output of the controlled oscillator. clock pulse, the switch output is connected to the second input of the frequency divider and the first input of the control pulse shaper, to the second input of which the second output of the PSG generator is connected, the second output of the correlator is connected to the first input of the discriminator, and the first, second, third, the fourth, fifth and sixth outputs of the control pulse generator are connected respectively to the second input of the PSH generator, the second input of the search control unit, the second and third discriminator inputs, the third input do the correlator and to the fourth input of the correlator, combined with the second R w input of the threshold block. 2; An apparatus according to claim 1, characterized in that the discriminator comprises a delay element connected in series, a logic unit and an integrating unit with summation, the output of which is the output of the discriminator, the first input of which is the input of an electric delay element 4, combined with the second input of the logical block, the third and fourth inputs of which are .BTOpbJM and the third inputs of the discriminator. 3, the apparatus according to claim 1, characterized in that the correlator comprises a modulo two series-connected adder, an AND element and a counter, the output of which is the first code of the correlator, the second output of which is the output of the modulo adder two, and first, The second, third, and fourth inputs of the correlator are, respectively, the first and second inputs of gum.

Description

matora modulo two, the second input element And the second input of the counter.

4. The device according to claim 1, wherein the search control unit comprises a first counter connected in series and an OR element, the output of which is connected to the first input of the first counter and the first input of a second counter, the first output of which is connected to the second input of the OR element and the first input first trigger second vhbd

which is combined with the second input of the first counter and is the first input of the search control unit, the first output of which is the output of the first trigger, and the outputs of the first and second counters are connected respectively to the first and second inputs of the second trigger, the output of which is the second output of the control unit a search whose second input is the second input of the second counter.

The invention relates to the field of radio communication and can be used in correlation tracking digital information receivers related to discrete communication systems, telemetry, television, control, etc., using pseudo-random modulation of signals transmitted through a multi-beam path. variable parameters.

A pseudo-random sequence clock synchronization device is known that contains a serially connected multiplier, an integrator, a threshold unit, a switch, a tracking corrector, a controlled clock generator and a pseudo-noise generator, the output of the threshold unit is connected to the second input of the search control unit, and the pseudo-noise generator outputs are connected to the reference inputs of the multiplier and the following correlator of the torus tl.

However, the known device has a large time to synchronize at a clock frequency.

The closest technical solution to the proposed is a clock synchronization device of a pseudo-random sequence containing serially connected correlator, the first input of which is the first input of the device, the threshold unit, the search control unit and the pseudo-gum signal generator (), the first input of which is connected to the second input the correlator of the torus, as well as the switch and the serially connected discriminator and controlled clock pulse generator, sequentially connected

the first integrator and multiplier, to the second input of which the output of the second integrator is connected, the input of which is combined with the first input of the correlator and the second input of the switch, the third input of which pushes the multiplier output, the first input of the switch is combined with the input of the search control unit, and the second and third generator outputs

PSHS connected to the second and third inputs of the discriminator 2.

However, the known device is characterized by a large time to synchronize at a clock frequency and low

Accuracy of tracking pseudo-random sequence delays.

The purpose of the invention is to reduce the time taken to synchronize at a clock frequency and increase accuracy.

tracking the pseudo-random sequence.

The goal is achieved by the fact that in a clock synchronization device of pseudo-random sequences,

containing a serially connected correlator whose first input is the first input of the device, a threshold unit, a search control unit and a generator

a signal (AS), the first output of which is connected to the second G1 output of the correlator, as well as a switch and successively connect (isg) 1CH-11; discriminator and pulse (and clock generator, control driver and frequency divider, the first input of which is the second input of the device, and the output of the frequency divider are connected to the first input of the switch, the second output of the control unit is connected to the second input search and the output of the controlled clock generator, while the switch output is connected to the second input of the frequency divider and the first input of the driver of control pulses to the second input the second output of the PSG generator is connected, the second output of the correlator is connected to the first input of the discriminator, and the first, second, third, fourth, fifth and sixth outputs of the control pulse generator are connected respectively to the second input of the PSG generator, second input of the search control unit the second and third inputs of the discriminator, the third input of the correlator, and the fourth input of the correlator combined with the second input of the threshold unit.

The discriminator contains a serially connected delay element logic unit and an integrating unit with summation, the output of which is the output of the discriminator, the first input of which is the input of the delay element combined with the second input of the logic unit, the third and third inputs of the discriminator.

The correlator contains a modulo two serially connected adder, an AND element and a counter, the output of which is the first output of the correlator, the second output of which is the output of the modulo two adder, and the first, second, third and fourth inputs of the correlator are respectively the first and the second inputs of the modulo two, the second input of the element And the input of the counter.

The search control block contains a first counter connected in series and an OR element, the output of which is connected to the first input of the first counter, the first input of the second counter, the first output of which

connected to the second input of the OR element and the first input of the first trigger, the second input of which is combined with the second input of the first counter and is the first input of the search control unit, the first output of which is the output of the first trigger, while the outputs of the first and second counters are connected respectively to the first and the second inputs of the second trigger, the output of which is the second step of the search control unit, the second input of which is the second input of the second counter.

Fig. 1 is a block diagram of a pseudo-random sequence clock synchronization device; FIG. 2 are timing charts explaining his work.

The device for clock synchronization of pseudorandom sequences contains switch 1, discriminator 2, containing delay element 3, logic unit 4, integration unit 5 with summation, control clock generator 6, correlator 7, containing adder 8 modulo two, element 9, counter 10, threshold block 11, search control block 12, comprising first and second counters 13, 14, element 15, first and second triggers 16, 17, pseudo-noise signal generator 18 (PSG), frequency divider 19, pulse control driver 20 owls,

The clock synchronization device of pseudorandom sequences works as follows. The information sequence of opposite pseudo-random signals transmitted from the information portable signal in the form of a double video sequence and a sinusoidal reference oscillation is fed to the device inputs: respectively, to the first input of the correlator 7 and to the first input of the frequency divider 19,

In the initial state, the threshold unit 11 has no effect on the first input of the search control unit 12 connected to its output (the second inputs of the first counter 13 and the first trigger 16), which indicates that a pseudo-random signal was not detected at the search-51 points of the search shaft. In this case, at the second output of the search control unit 12 (at the output of the second trigger 17), the installation signal of the switch 1 appears in a state where the output controlled clock pulse generator is connected to the first input of the control driver 20, produced in the form of a block containing a pulse counter, the inputs of which (counting input and installation input) at zero state are the inputs of the synchronizer and the decoder, and to the second input of the frequency divider 19, and the output of the frequency divider 19 is disconnected from the first About the input of the driver 20 of control pulses and from the second input of the frequency divider 19. The impact of the clock pulses of the controlled generator 6 clock pulses at the first input of the driver 20 of the control pulses leads to working on the first form output

world of 20 control pulses of clock synchronization of the generator 18 pseudo-noise ratio X2X X VX X2XjX VX X2X35

-; . 35 I where x-, i -1j2,3,4 is variable, taking the value O and 1 and displaying an arbitrary value of the binary signal acting on the i-input of logic unit 4 containing the logical elements OR, AND NOT necessary dialing and communication between which are established according to the well-known method of synthesis of finite automata for the implementation of specified logical fuctions, and the input of the delay element 3, made in the form of an inverter, the input and output of which are connected through differentiating circuits and limiters from above (zero) with zero threshold, in series nnym monostable and flip-flop input. An exemplary view of the signals acting on the first and second inputs of the correlator 7 is shown respectively in FIG. 2c1 and 25, and an approximate view of the signals fed to the second input

the second and the second input of the correlator 7, which is performed in the adder 8 modulo two, includes a pseudo-random sequence supplied to the second input of the logic unit 4, realizing two logical functions 4 square-wave pulses, followed by the second input of the corrector of the 7 , and at the second output - a pulse of fixation of a certain state of the generator 18 of PShS, arriving at the second input of the driver 20 control pulses, Effect of clock pulses of the controlled generator 6 clock pulses at the second input of the frequency divider 19 s leads to the correction of the state of the frequency divider 19, providing phase matching of two sequences of clock synchronization pulses, one of which is output at the frequency divider 19 as a result of recalculating the sinusoidal pulses of the reference oscillation received at its first input, and the other at the output of the controlled oscillator generator 6 clock pulses. At the second output of the correlator 7 as a result of summing modulo ddd signals acting on the perlogical block 4 and the input of the delay element 3 is shown in FIG. 2B. The third input of logic unit 4 is supplied with a sequence of square-shaped pulses formed at the third output of the driver 20 of control pulses, the temporal position of the fronts of which (FIG. 2E) is determined by the position of the time points lying on the boundaries and in the middle part of the generation intervals of the PSH generator 18 pseudo-random sequence. The fourth input of the logic unit 4 is supplied with a sequence of square-shaped pulses formed at the fourth output of the control driver 20, the temporary position of the fronts (Fig. 2e) is determined by the position of the leading edge of the quarter-period oscillation of the square pulse sequence allocated at the third the output of the driver 20 controlled pulses / To the first input of logic unit 4, delayed using a delay element 3 consecutive pulses is applied rightly th form acting on the second input of the logic unit 4. An exemplary view of a sequence of pulses acting on the first input of logic unit 4 at the optimum delay time of delay element 3, equal to the fourth part of the generation interval of the pseudo-random sequence element generated at the first output of PSHS generator 18, is shown in FIG. . 2g. The influences exerted on the inputs of a logic unit 4, constructed, for example, according to the indicated equations, generate at its outputs two streams of binary pulses of rectangular shape, the approximate form of which is shown in FIG. 2 F and 2H. The binary pulse streams generated at the outputs of the logic block 4 are fed to the corresponding inputs of the integration block 4 with the summation of the input values, made in the form of a block containing three input resistance circuits, the outputs of which are combined with the input of the operational amplifier, the feedback circuit a capacitor, and a constant voltage source, the polarity sign of which is opposite to the polarity sign of the input voltage, while the output of the specified voltage source is connected to the input retey input circuit active resistor unit 5 is an integration with summation. As a result, a voltage is generated at the output of the own adder of the block 5 integrated with the summation of the input values, the approximate form of which is shown in FIG. 2m and at the output of the own integra-ora of the integration unit 5 with the summation of the input values, a control voltage is generated (Fig. 2k) acting on the control element of the controlled oscillator 6 clock pulses. The meaning of the considered transmission of actions on a ring-controlled center of frequency control of a controlled generator of 6 clock pulses consists in forcing a change in the rate of operation of the driver of control pulses 20 in the direction leading to the alignment of the temporal boundaries of the element of the reference pseudo-clock sequence generated at the first output of the HSG generator 18 , with the temporal boundaries of the element of the pseudo-random sequence, fed to the first input 1 of the relay torus 7. At the same time, the entered elements and connections provide An increase in the transform coefficient of discriminator 2 increases, which is a factor in reducing the time required for combining the temporal boundaries of the elements of the reference produced by the generator. 18 PSES and the received (input) pseudo-random sequences. Following the installation of switch 1 into the first, indicated state, following a command following the first output of the search control unit 12 (from the output of the first trigger 16) to the first input of the PSG generator 18, the pseudo-random sequence of the PSG generator 18 is changed by a certain amount, repeat after a predetermined time interval. At the same time, multiple measurement of the delay in the code sequence of the PSG generator 18 leads to the overlapping of the pseudo-random time boundaries arriving at the first and second inputs of the correlator 7, at which the pseudo-random sequences correlate and respond at the first output of the correlator 7, reaching the threshold value, cause the formation the threshold block 11 signal prohibit the search time limits of a pseudo-random signal, after which the change in the delay of the pseudo-random sequence of the PSG generator 18 ekraschaets and clock synchronization device goes into a synchronous tracking mode signal parameters. In the proposed device for clock synchronization of pseudo-random sequences, the decision on the presence or absence of a pseudo-random signal at the point of the search interval is made based on the result of comparing the contents of counter 10 with thresholds e, and e in the pulse action interval. 1 incoming to the second inputs of the counter 10 and the threshold unit 11 from the sixth output of the driver 20 control pulses. The content of the meter W at the time of decision is determined by the number of short duration pulses arriving in the PSH generator 18 generation interval of the pseudo-random sequence from the fifth output of the control pulse generator 20 to the second input of the AND 9 logical element and the first input of the counter 10. At the same time, the logical element AND 9, in accordance with the logical function of coincidence performed by it, passes only those pulses to the output of the acting on its second input s, temporal position of which coincides with the temporal position of the binary pulse finds schihs in a single state, to a first input of the AND gate 9 to output sous Matora 8 modulo two. The optimal tracking frequency of the control pulses generated at the fifth output of the driver 20 corresponds to the tracking frequency of the code elements of the pseudo-random sequence generated by the PSG generator 18. The reset signal of the counter 10 to the zero state and the formation at the output of the threshold unit 11 of the secondary impulse, reflecting the acceptance of one hypothesis or another, is the surge voltage of the falling edge of the pulse, which affects the second inputs of the counter 10 and the threshold block. 11. The search control unit 12 works as follows. The second input of the second counter 14, which is the second input of the search control unit 12, is supplied with a sequence of pulses generated at the second output of the control pulse generator causing an increase in the reading of the second counter 14. If the number of pulses received at the input of counter 14 reaches the number where r - the number of binary bits of the second counter 14, then on the first output of the second counter 14 (at the output of the high bit trigger of the second counter 14) a reverse 410 communication signal is supplied through the logical element OR 15 to the input The settings of the second counter 14 and the first counter 13 are set to the zero state, under the action of which the counters 13 and 14 go to the zero state, and directly to the first input of the first trigger 16, passing to the output state of the output installation of the generator 18 PSHS. In the mode of measurement of the delay generated code sequence. Applying pulse signals to the second inputs of the first counter 13 and the first trigger 16, reflecting the decision to have the pseudo-random sequences matching the first and second inputs of the correlator 7, causes the state of the first trigger 16 to change, leading to output at its output voltage setting of the 18 PSHS generator in the mode of generating a pseudo-random sequence and a fixed delay and an increase in the reading of the first counter 13. If the number of pulses received at the second input of the counter 13 reaches em number N2 2. . where Z is the number of binary bits of the first counter 13, then the output of the first counter 13 (at the output of the high bit trigger of the first counter 13) is a feedback signal applied through the logic element OR 15 to the installation inputs of the counters 13 and 14 in the zero state, under the action of which the counters 13 and 14 go to the zero state, and directly to the first input of the second trigger 17, which then transitions to the operating state at the voltage output of the installation of the switch 1 to the state at which the output divider 19 frequency render ts connected to the first input of the frequency divider 19, and the output of the controlled generator 6 clock pulses - disconnected from the first input of the shaper 20 frequency divider and from the second input of the frequency divider 19. If the number of pulses received at the second input of counter 14 exceeds the number of Nj 2, then at the second output of the second counter 14 (at the exit | of one of the triggers of the counter 14 or at the output of the own decoder of the counter 14) a signal of the second trigger 17 appears This is a condition in which the switch 1 controlled by the second trigger 17 switches the circuit connecting the output of the clock controlled generator 6 to the first input of the driver 20 and the second frequency divider 19. Choosing the frequency, following the pulses generated at the second output of the control pulse generator 20, and selecting the number of bits of the first counter 13 and the number of bits of the second counter 14 ensures the required probability of a false transition of the pseudo-random sequence clock device to the position re-search mode in time received pseudo-random signal. Switching the first input of the control pulse generator 20 from the output of the controlled generator 6 clock pulses to the outputs of frequency divider 19 leads to the formation of clock synchronization pulses from a sinusoidal reference oscillation, extracted from the radio signal by a voltage reference circuit (not shown in Fig. 1). From this point on, the clock frequency adjustment of the pseudo-random sequences and the carrier oscillation frequency comes from a single voltage of the own discriminator of the reference voltage shaping circuit, which ensures high accuracy of tracking the time delay of the received pseudo-random signal. Switching the first input of the control pulse generator 20 from the output of the frequency divider 19 to the output of the controlled oscillator 6 clock pulses indicates a decrease in the signal-to-noise ratio at the receiver input below the value determined by selecting the threshold value of the second counter reading 14 1 Na displayed by the corresponding signal, generated at the second output of the second counter 14, or about the unsatisfactory accuracy of tracking the pseudo-random signal delay. From this point on, the adjustment of 10 12 according to the clock frequency of the pseudo-random sequences and according to the frequency of the carrier oscillation is made from different voltages of independently working discriminators. In this case, the flow of clock clock synchronization, controlled by the generator, 6 clock pulses to the second input of the frequency divider 19, the effect of which leads to the correction of the phase of the clock synchronization pulse sequence generated at the output of the frequency divider 19 and correction, (or test) the pseudo random sequence, generated by the generator 18 HSPs. Thus, in the proposed technical solution, ensuring the reduction of the search time for the phase of the pseudo-random sequence of the phase manipulation of the signal with a low signal-to-noise ratio and the multipath nature of radio wave propagation is achieved by introducing the servo system into the synchronous tracking mode of the signal and clock synchronization of pseudo-random sequences are performed at the same time and (unlike the prototype) with increasing the noise immunity of the clock synchronization of the PSA random sequences. The increase in the noise synchronization of clock synchronization is due to an increase (by half compared to the prototype) of the discriminator's conversion coefficient in that case when the time shift between the phase of the reference pseudo-random sequence and the phase of the pseudo-random sequence of intrapulse modulation (phase shift) of the received signal is greater than the duration of the element of the impulse modulation (phase shift) of the received signal, the element length of the element of the impulse modulation (phase shift) of the received signal is greater than the duration of the element of the received signal modulation (phase shift of the received signal). In the proposed technical solution, in addition, the effect of increasing the accuracy of tracking the signal parameters is achieved, which is caused by the transition from adjusting the carrier frequency and the clock frequency of the pseudo-random sequence from the voltages of two discriminators to adjusting the single voltage of the own 13 discriminator of the formation of the reference voltage wives The technical effect of the implementation of the proposed device is to reduce the clock synchronization time by increasing the discriminator conversion rate and by increasing the accuracy of tracking the time delay of the information flow of pseudo-random signals by adjusting the clock frequency and frequency of the carrier oscillation from the same frequency signal. reference voltage shaping circuit. TO

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Claims (4)

1. DEVICE FOR TACT SYNCHRONIZATION OF Pseudo-Random Sequences, comprising a correlator in series, the first input of which is the first input of the device, a threshold block, a search control unit and a pseudo-noise signal generator (PSH), the first output of which is connected to the second input of the correlator, as well as a switch and sequentially connected discriminator and controllable clock generator, characterized in that, in order to reduce the time of entering synchronism in clock frequency and increase t chnosti tracking delay pseudorandom sequences introduced therein driver control pulses and a frequency divider, a first input of which is the second input device and the output of the frequency divider is connected to the first input switch, to the second and third. the inputs of which are connected respectively to the second input of the search control unit and the output of a controlled clock generator, while the output of the switch is connected to the second input of the frequency divider and the first input of the driver of the control pulses, the second input of which is connected to the second output of the PCB generator, and the second output of the correlator is connected to the first discriminator input, and the first, second, third, fourth, fifth and sixth outputs of the control pulse generator are connected respectively to the second input of the generator RPS, the second input of the search control block, the second and third inputs of the discriminator, the third input of the correlator and the fourth input of the correlator, combined with the second _β input of the threshold block. © 2. The device according to claim 1, characterized in that the discriminator comprises a delay element connected in series, a logic unit and an integration unit with summation, the output of which is the output of the discriminator, the first input of which is the input of the delay element, combined with the second input of the logical unit, the third and the fourth inputs of which are the second and third inputs of the discriminator. 3. The device according to p. 1, characterized in that the correlator contains a series-connected adder modulo two, an element And and a counter whose output is the first output of the correlator, the second output of which is the adder modulo two, and the first, second, third and the fourth inputs of the correlator are respectively the first and second inputs of the sum SU, No. 1092744 which is combined with the second input of the first counter and is the first input of the search control unit, the first output of which is the output of the first trigger, while the outputs of the first and second counters are connected respectively to the first and second inputs of the second trigger, the output of which is the second output search control unit, the second input of which is the second input of the second counter. two modules, the second input of the AND element and the second input of the counter. 4. The device pop. 1, characterized in that the search control unit comprises a first counter and an OR element connected in series, the output of which is connected to the first input of the first counter and the first input of the second counter, the first output of which is connected to the second input of the OR element and the first input of the first trigger, second input ’