SU1275747A2 - Device for selecting clock pulses - Google Patents

Abstract

The invention relates to a communication technique and can be used in receiving equipment for digital information, namely, in a synchronization and gating system of a multipath signal convolved in a matched filter, followed by processing in a digital computer. The invention is additional to the invention in accordance with the author. St. No. 1157676. The purpose of the invention is to improve the noise immunity of the device for the extraction of clock pulses. The goal is achieved by introducing into the device the prototype of consecutively connected logical elements: one OR element and the second element I. Operation of the device is explained according to the functional diagram and diagrams of timing diagrams in the description of the invention. 2 Il. with (

Description

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 The invention relates to a communication technique; p can be used in receiving digital information equipment, namely, in a synchronization system and gating a multipath signal rolled up in a matched filter, followed by processing in a digital computer, and is an improvement of the invention in accordance with the authors. St. No. 1157676. The purpose of the invention is to improve noise immunity. FIG. 1 is a block diagram of a clock extraction device; Fig. 2 shows timing diagrams explaining the operation of the device. The device contains a series-connected rectifier 1, a delay line 2, a subtraction device 3, the second input of which is connected to the output of the rectifier 1 "recirculator 4, the second delay line 5, an adder 6, the second input of which is connected to the output of the recirculator 4, and a shaper 7, an AND 8 element connected in series, whose input is combined with the first output of the device, and a synchronization unit 9, the first output of which is connected to the second input of the AND 8 element and is the second output of the device, and the gross output — to the second line inputs 2 and 5 delays and recirculator 4, and AND 10, connected in series, the first, second and third inputs of which are respectively the first, third and fourth outputs of the synchronization unit 9, and the OR element 11, the second input of which is connected to the output of the imager 7, and the output is with the first input of the element 8. 8. The recycler 4 comprises a series-connected adder 12, a rectifier 13, a delay element 14 of the amplifier 15, a subtraction unit 16 and a second amplifier 17, the output of which is the output of the recirculator 4 and connected to the first the input of the adder 12, The second input of which is the first input of the recirculator 4, while the second input of the subtraction unit 16 is connected to the second output of the delay element 14, the second input of which is the second input of the recirculator 4. The synchronization unit 9 contains serially connected discriminator 18, controlled) a clock pulse generator 19, a divider 20, a trigger 21 and a one-shot 22, the input of which is connected to the input of the discriminator 18, wherein the second input of the trigger 21 is the input of the synchronization unit 9, the first, second, third and fourth outputs of which respectively, the output of the one-shot 22, the output of the controlled oscillator 19 clock pulses, the first and second outputs of the splitter 20, are shown. In FIG. Figure 2a shows the signal at the output of the imager 7. A wide pulse generated by a direct communication signal, the other two - by reflected signals, the dashed line shows the temporal position of the pulse 7 that was tracked at the output of the imager of the monitored pulse; pulse on the time axis. In addition, the voltage forms at the outputs of the one-shot 22 (5), the element And 8 (B) and the element And 10 (g), the pulse sequences at the input of the divider 20 (a), the second (e) and the first (the outputs of the divider 20, the voltage | yp iprymoe at the trigger output 21 (g), the pulse sequence at the output of the element OR 11 (and) and the voltage form at the output of the discriminator 18 (k), the device works as follows. The information stream of multipath pseudorandom signals passing through matched filter, enters the input of the device (at the input of the rectifier 1) The response to the input action obtained at the output of a circuit of serially connected rectifier 1, delay line 2, subtractive device 3, recirculator 4, second delay line 5, adder 6 and former 7 is a sequence of square-shaped pulses, the duration of each of which does not exceed half the period of the carrier frequency of the input signal, and the position of the fronts reflects the boundaries of the time interval shifted by half the period of the carrier frequency from the interval of the same duration in which The point of optimal moment of decision about the value of the informative parameter of the input signal is turned on.

The first impulse received at the output of the imaging unit 7 through the series-connected elements OR 11 and AND 8 acts on the input of the synchronization unit 9. As a result, the impulse is formed at the first output of the synchronization unit 9 (the position of the fronts coincides with the window time interval), which includes at the output of the imaging unit 7 in the shedding direct pulse, which arrives at the first input of the input second element And 10, simultaneously the second and third inputs of the second element And 10 receive pulses of one the voltage, respectively, from the first and second outputs of the divider 20,

The duration of the pulse generated at the second output of the splitter 20 should be part of the pulse generation interval generated at the output of the driver 7, which is provided by using the splitter 20, which includes the shift register and the decoder. In this case, the central point of the interval occupied by the pulse generated at the output of the divider 20 must coincide with the central point of the time interval occupied by the pulse generated at the output of the driver 7.

As a result of the implementation of the logical operation of multiplying the input variables at the output of the element And 10, a short pulse appears whose form coincides with the form of the pulse generated at the second output of the divider 20. This pulse arrives at the first input of the element OR 11, the second input of which is affected by the pulse generated at the output of the driver 7, As a result of the implementation of the logical addition operation over the input variables at the output of the element OR 11, a pulse is produced, the form of which completely coincides with the form of the pulse, price 757474

the element 11 acting on the second input. In this mode, the additionally entered elements do not affect the operation of the device.

5 At the moment of the disappearance of the monitored pulse emitted at the output of the driver 7, the flip-flop 21 is transferred to the new state by the pulse generated at the high end of the element 10 that goes to the second input of the trigger 21 along the circuit connecting the first input of the element 11 s element output is AND 8. This provides protection for the device against loss of clock pulses. If the tracked pulse disappears for a long time, the device can go into synchronism with any pulse emitted by the output of the imaging unit 7, which is formed as a result of the arrival of the signal at the receiving point along the reflected beam. But, since the probability of the disappearance of this impulse

25 is relatively high, synchronization of the operation of the device may be disrupted. In this case, the device goes into the search mode and is in this. state to the point in time when

The ep pulse generated at the output of the imager 7 as a result of the arrival of a signal at the point of reception along the main beam will coincide in time with the pulse generated at the output of the And 10 element.

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Claims (1)

Invention Formula The device selection clock pulses auth. St. № 1157676, about t - 0 with the fact that, in order to increase noise immunity, a second AND element and an OR element are inputted into it, the first input of the AND element is connected to the first output of the synchronization unit, and the second and third inputs are respectively to the third and fourth outputs of the synchronization unit , while the second input of the OR element is connected to the driver output, and the output is connected to the first input of the first element I.