SU1499456A1 - Clocking device - Google Patents

Abstract

The invention is intended for use in telemechanic systems containing a control point and a number of controlled points connected by long lines of communication. The goal is to increase reliability by allowing the synchronization mode to change depending on the nature of the information signal. The device contains triggers 1, 5, 8 and 9, a pulse counter 3, elements AND 6, 10 and 11, an element OR 17, an operation mode switch 18, a pulse shaper 19, inverters 7 and 14, a delay element 16 and shapers 12 and 15 short pulses. The device has a bus 13 clock pulses, information bus 20, bus 21 control and output tires 2 and 4. 1 sludge.

Description

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The invention relates to a pulse technique and can be used in telemechanics systems with time-division signals, in which the moments of a level sienna in the information pulse sequence, coming from the communication line, are used to correct the phase of clock signals, gating information input to the receiver.

The purpose of the invention is to increase reliability by allowing the synchronization mode to change depending on the nature of the information signal.

The drawing shows an electrical block diagram of a clock synchronization device.

The device contains the first trigger 1, the direct output of which is connected to the first output bus 2, the clock input with the output of the counter 3 pulses, the second output bus 4, the information input of the Second trigger 5, the direct output of which is connected to the first input of the first element I 6 and through the first inverter 7 with the information input of the third trigger 8, the direct output of which is connected to the information input of the fourth trigger 9, the direct output of which is connected to the first input of the second element I 10, the output of which is connected to the reset input of the third a trigger 8, an inverse output of which is soy; dinene with the reset input of the fourth trigger 9 and the first input of the third element 11, the second input of which is connected to the clock input of the fourth trigger 9 and through the first generator 12 short pulses to the front 13 clock pulses 5 which through the serially connected second inverter 14 and the second shaper 15 short pulses connected to the second input of the second element And 10 and the second input of the first element And 6 whose output through the delay element 16 is connected to the reset input of the second trigger 5 and directly to the first input ele OR 17, the second input of which is connected to the output of the third element 11, the output to the counting input of the pulse counter 3, the reset input of which is connected to the first output of the operation mode switch 18, the second output of which is connected to the clock inputs of the trigger 5 and 8, input through shaper 19

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pulses with data bus 20, and with information input of the first trigger 1, control input — with control bus 21. The pulse shaper 19 generates short pulses at YOUR output at the time of the appearance of a pulse front and cut on the bus 20. It can be performed using the EXCLUSIVE OR element and the delay element 23.

The device works in the following way.

The device bus 20 is provided with an information sequence of signals from a telecommunications transmitter (shown) located relative to the receiver on the opposite side of the communication line, and to pin 13, a periodic sequence of signals from a local clock generator (not shown) is transmitted.

On the bus 2 of the device passes the teleinformation synchronized with the receiver's clock pulses, formed by the counter 3, which are fed to the bus 4.

Consider the operation of the clock synchronization device for the case when the phase of the receiver clock pulses on im 4 is ahead of the transmitter clock on the bus 20. In this mode, the signal level change on bus 20 is fixed after the time the logic level O is set on bus 4. B mode in question The switch 18 by the signal from the bus 21 is set to transmit signals from the input to the second output, i.e. on clock inputs of triggers 5 n 8.

The trigger 5 remains in the zero state, the trigger 8 by the signal from the output of the imaging unit 19, since the information input of the trigger 8 has a unit level from the output of the inverter 7, switches to the unit state. When this signal from the output of the imaging unit 15 does not pass to the output of the element b, the signal from the output of the imaging device 12 to the output of the element 11 also does not pass, since the first input of the element 11 from the inverse output of the trigger 8 receives a zero level. The first pulse at the output of the driver 12 after setting the trigger 8 to the single state sets the trigger 9 to the single state, after which the first pulse at the output of the driver 15, the passage to the output of the element 10,

returns the trigger 8 to the zero state, which ensures the return to the zero state and the trigger 9. With the reduced phase relations of the signals on the buses 20 and 13, it is provided (if the change in the input signal level is fixed) one pulse from the generator 12 output, i.e. . decreases by the value of the total number of pulses arriving through element 17 to the counting input of counter 3. It is obvious that after this the instant of formation of the next front is

the optimum phase shift between the transmitter and receiver clock signals, so that the signals on bus 4 can be used to strobe the information sequence and receive (with the help of flip-flop 1) binary code signals synchronized with respect to the generated clock pulses. The output signals of the counter 3 and trigger 1 are fed to the output of the device for further processing and analysis of the conditions for receiving information (for example,

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ta (decay) of the signal on the bus 4 delayed the number of recorded failures). It appears by an amount equal to the period of the signals on the bus 13. Consequently, the device corrects the phase of the receiver clock pulses in the direction of compensation of the phase of the clock pulses of the transmitter fixed by them.

Consider the operation of the clock synchronization device for the case when the phase of the receiver clock on bus 4 lags behind the phase of the transmitter clock on bus 20. In this case, when the signal level changes on bus 20 on bus 4, there is a single level, Ichulse, coming from the output shaper 19 to clock inputs of triggers 5 and 8, trigger 5 is set to one

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The result of the reception and processing of the bus 2 with information by the noise level analyzer (not shown) can be a control signal determining the optimal {th synchronization mode. The specified signal is fed to the device bus and determines the current signal of the switch 18. At one signal level, the switch 18 transfers the signals from the output of the shaper 19 to the second output, while the inertial correction of the phase of the clock pulses of the receiver is performed with the other - the switch 18 transfers the input signals to the first output echiva holding device inertialess synchronization. Thus, in accordance with the actual conditions for the transmission and reception of information

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the state, and the trigger 8 remains in the zero state. The first impulse from the output of the imaging unit 15 (after the trigger 5 is set to one state) passes to the output of the element 6. The trigger 8 is at zero zero. through element 11, the control signal that determines the optimal {synchronization mode) can be formed through the reception and processing of the information sequence received from bus 2 by an interference level analyzer (not shown). This signal is fed to the device bus 21 and determines the current state of the switch 18. At one signal level, the switch 18 transfers the signals from the driver 19 to the second output, while the inertial phase of the receiver clock pulses is corrected, while the other switch 18 transmits the input signals on the first exit, ensuring that the device conducts inertialess synchronization. Thus, in accordance with the actual conditions of transmitting and receiving information, an optimal synchronization mode is established - with a higher level of interference (frequent faults detected by the analyzer), the device implements a slow inertial algo pulse from the output of a 12 V clock pulse phase correction. As a result, one additional pulse passes through the output of element 17, which causes the front of the next pulse to be formed at the output of counter 3. earlier by a time equal to the period of the pulses on the bus 13. Since the pulse from the output of element 6 is delayed by element 16 for a time shorter than the duration of the pulse from the output of the driver 15, the trigger 5 returns to the zero state. The indicated correction of the phase of the signal on the bus 4 is performed once when each change of the logic level is fixed on the bus 20,

In both cases considered, the clock synchronization device is inertial, i.e. the method of successive approximation sets

The receiver’s receiver, with a low level of interference (rare or absent “with failure x), is a fast inertialess correction algorithm. If for any steam

 b of transmitters and receivers within the same telemechanics system a priori the real level of interference is set, the signal of the bus 21 of the device may be unchanged - in accordance with

50 with known conditions for transmitting and receiving information.

Consider the operation of the elements of the device in the mode of inertial 55 (shock) synchronization. In this mode, the triggers 5, 8, and 9 are held in the zero state, and a periodic sequence of pulses arrives at the counting input of the counter 3.

the number of recorded failures). By

As a result of receiving and processing the information sequence received from bus 2 by an interference level analyzer (not shown), a control signal can be generated that determines the optimum {synchronization mode. This signal is fed to the device bus 21 and determines the current state of the switch 18. At one signal level, the switch 18 transfers the signals from the driver 19 to the second output, while the inertial phase of the receiver clock pulses is corrected, while the other switch 18 transmits the input signals on the first exit, ensuring that the device conducts inertialess synchronization. Thus, in accordance with the actual conditions of transmitting and receiving information, an optimal synchronization mode is established — with a higher level of interference (frequent faults detected by the analyzer), the device implements a slow inertial algorithm.

rhythm of correction of the phase of the clock pulses of the receiver, with a small level of interference (rare or absent with “cx”) - a fast inertia-free correction algorithm. If for any steam

 b of transmitters and receivers within the same telemechanics system a priori the real level of interference is set, the signal of the bus 21 of the device may be unchanged - in accordance with

50 with known conditions for transmitting and receiving information.

Consider the operation of the elements of the device in the mode of inertial 55 (shock) synchronization. In this mode, the triggers 5, 8, and 9 are held in the zero state, and the counter input of the counter 3 receives a periodic sequence of pulses

the frequency of which is equal to the frequency of the pulses on the frequency 13. As a result, the output of the counter 3 generates clock pulses whose frequency is equal to the frequency of the clock pulses of the transmitter. Since each pulse from the output of the former 19, the counter 3 is set to zero, the receiver is synchronized.

Claims (1)

The invention is a clock synchronization device containing a pulse counter, the first trigger, the direct output of which is connected to the first output bus, the second trigger, the direct output of which is connected to the first input of the first element And, the third and fourth triggers, the bus pulse, information bus The second and third elements are AND and the OR element, characterized in that, with a safety chain by providing a change in the synchronization mode depending on the nature of the information signal, the first and second inverters, second output bus, delay element, first and second short pulse shapers, pulse shaper, control bus and mode switch, the input of which is connected through the pulse shaper to the data bus and the information input of the first five 0 five 0 five trigger, control input — with control bus, first output — with a pulse counter reset input, the output of which is connected to the clock input of the first trigger, information input of the second trigger, and through the first inverter with information input of the third trigger, a clock input connected to a clock input of the second trigger and a second output of the operation mode switch, a reset input with an output of the second element I, the first input of which is connected to the direct output of the fourth trigger, whose information input is connected to the right m output of the third flip-flop, the inverse output of which is connected to the reset input of the fourth flip-flop and the first input of the third element I, the second input of which is connected to the clock input of the fourth flip-flop and through the first shaper of short pulses with a bus of clock pulses, which through serially connected second inverter and shaper of short pulses connected to the second inputs of the second and first elements, the output of the latter through the delay element connected to the reset input of the second trigger and directly the first input of the OR gate, a second input coupled to an output of the third AND gate, the output - to the pulse counting input of the counter.