SU983978A1 - Frequency-phase comparator - Google Patents

Description

The invention relates to a technique of comparing the frequencies and phases of pulsed signals and can be used as an error sensor in phase synchronization systems for transmitting binary information, in particular, in the channels of playback of digital recording equipment. Closest to the proposed phase-phase comparator, built. On the basis of two triggers, which has a linear discrimination of the 1 GK character in the ZbO range When used as a mismatch sensor for an astatic phase locking system, such a comparator provides a system acquisition band equal to the containment band, as well as the synphasicity of the compared signals in the set mode Cl3. At the same time, this cno comparator can only work with regular compared signals, i.e. it cannot be used for phase comparison when working with random information signals. Thus, its functionality is limited. The purpose of the invention is to improve the functional and shonal possibilities due to the phase comparison of random information signals. This goal is achieved by the fact that 8 a frequency-phase comparator containing two main triggers connected by w of inputs to the corresponding inputs of a logic element, the output of which is connected to the first inputs of the main triggers, is inserted into the additional delay element, and the first input of the additional trigger is connected to the output of the logic element, the input terminal of the first compared signal is connected to the input of the delay element and the second input of the additional trigger, the output of the delay element is connected to the second 1 input of the first main latch, the second input of the second flip-flop is connected to the ground input terminal of the second srav3 .983 NIWA signal optional trigger output connected to third inputs of the main triggers, and the third input latch further connected to a bus control signal. FIG. 1 shows the structural scheme of the device; in fig. 2 - 3 are timing diagrams illustrating the operation of the circuit in the frequency-in-phase comparison mode; on fnr. 4 is the same in phase comparison mode. The device contains ocHOBHbte triggers 1, 2 and additional trigger 3,. a logical element that can be executed in the form of AND-NOT 4 scheme, an element of 5delay. The delay element can be a delay line, a one-shot, a control signal bus 6, the input terminals of the first 7 and second 8 compared signals, output buses 9 and 1 O of the device. The operation of the device is as follows. Depending on the level of control CHrHiana on bus 6, the frequency-phase comparator compares the signals at terminals 7 and 8, either in frequency and phase, or only in phase. The result of the comparison is represented by the pulse width, cellulose on the output buses 9 and lO. In the timing diagrams of FIG. 2–4, the letters A ... And the signals are formed, which are formed in the nodes of the circuit of FIG. 1. In the frequency-phase comparison mode, the level of the control signal A on the bus 6 corresponds to a logical zero. This level keeps the trigger 3 in the cocked state, so the logical unit is constantly present on the D inputs of triggers 1 and 2 (diagram D nafkGo2, Situation, when the frequencies of the compared signals are not equal, shown in Fig. 2. Empty frequency signals B on terminal 7 is higher than the frequency of signals C on terminal 8. Signals B are sent to the trigger input of trigger 2 directly, and

Claims (2)

signals B to the trigger input trigger; bus 8. Hera 1st delay t of delay element 5 (Fig. 2 D). the inequality of the compared frequencies trigger 1 is always cocked before trigger 2; a sequence of pulses E of different width is formed at its output. The beginning of these pulses, indicated in the E diagram by an oblique hatching, coincides with the moment of arrival of the delayed 1 signal of a higher frequency B, and the end - with the time of arrival of the pulses B of a lower frequency. A reset of both triggers occurs after both of them are cocked. At the same time, the AND 4 4 4 scheme makes it possible to match the logical logic on the outputs of the flip-flops 1 (Fig. 2E) and 2 (Fig. 2 G) and generate an impulse AND, resetting the flip-flops 1 and 2. Reset trigger 3 does not occur, because on its S-input there is a logical zero. Thus, in the considered situation, on the output bus 9, pulses are generated with a duration, the current time delay Ai (Fig. 2) of signal B relative to signal G. trigger 2, compared with the period can be neglected. In the alternative case, when the frequency of signals B is lower than the frequency of signals B, a sequence of pulses will form already on the output bus 1O. If the frequencies of the compared signals are equal, the device compares their phases. FIG. 3 shows three characteristic cases: the first signal G is ahead of the second signal B (4 / O), the signal G is lagging behind the signal B (a × O) j and the compared signals arrive simultaneously (IC 0). In the first case, signals with a duration of dt are formed on the output bus 9, in the second - on the output bus 1O. In the case of phase matching of the compared signals on both output mKiiax, pulses are neglected. small, shchelichnosti. In the phase comparison only mode, the control signal level A (Fig. 4) is one. Let the bus 7 on the bus 6 of the device receive information code pulses (Fig. 4B) located at random intervals from each other7 and on the bus B - regular sync signals. The device makes a comparison of the phase of the incoming code pulse with the phase of the nearest sync signal to the next sync signal using the delay element 5 and trigger 3 as follows. Each pulse arriving at terminal 7 coaxes trigger 3 and a single-level voltage level is allowed at D inputs of triggers 1 and 2 (phase diagram D in Fig. 4). After that, depending on the order of arrival of the compared signals on the output bus 9, or on the output bus 10, a signal is generated reflecting the result of the phase comparison (Fig. 4E, g). At the end of the output signal with a pulse. And from the output of the AND-NO 4 circuit, all the triggers, including trigger 3, are reset and the circuit returns to its original state. Thus, the proposed device is distinguished by wide functional possibilities, since it allows working with random signals. The invention has a Frequency Phase Comparator, containing two main triggers, connected by outputs with the corresponding inputs of a logic element, the output of which is connected to the main inputs of the main three characters, characterized in that in order to expand the functionality of the functions by phase comparison of random information signals, an additional trigger and a delay element are introduced, the first input being up-. the additional trigger is connected to the output of the logic element, the input terminal of the first compared signal is connected to the input of the delay element in the amp input of the additional trigger, the output of the delay element is connected to the second input of the first main trigger, the second input of the second main trigger is connected to the input terminal of the second trigger “ signal being output, the output of a two-flip-flop trigger is connected to the third inputs of the main triggers, and the third BXOJK of the additional trigger is connected to the control signal bus. Sources of information taken into account in the examination 1. US Patent No. 3710140, cl. 328-133,1973. Fi & / Sh..SH 1 n Thebes. 2 (0 п.ШШ п п и и and II Л. 5 1-. П ll