SU1298943A1 - Bipulse signal receiver - Google Patents

Abstract

Invention m. used in digital communication systems. The purpose of the invention is to increase the noise immunity to edge distortion. The receiver contains matching unit 1, latch 2 transitions, counting trigger 4 and keys 6 and 7. The divider 3, key 5, inverter 8 and RS trigger 9 are reintroduced. Incorrect setting of the phase of the signal at the output of the trigger 4. In this case, upon receipt of information. units at the output of key 6, boundary impulses appear, at the output of the key random mid-impulses. With the addition of information the zero output of the RS flip-flop 9 generates an extended control impulse arriving at the key 5. At this, the impulse from the output of the key 6 through the inverter 8 arrives at the key 5. At the output of the key 5, the impulse is set to zero of the trigger 4. At this, the trigger 4 em phase and thereby eliminates the mode of false phasing. 1 il. about s (l

Description

one

The invention relates to the field of telecommunications and can be used in digital communication systems.

The purpose of the invention is to increase the noise immunity to edge distortion.

The drawing shows a block diagram of the receiver.

The bi-pulse signal receiver contains matching unit 1, latch 2 years, divider 3, counting trigger 4, additional key 5, first and second keys 6 and 7, inverter RS-flip-flop 9.

The receiver works as follows.

The input information bi-pulse signal is fed to the input of matching unit 1, which performs the function of matching the input resistances of the physical line and the receiver of bi-pulse signals. From the output of the matching unit 1, the bi-pulse signal is fed to the input of the clamp 2 transitions, the allocated fronts of the bi-pulse signal are sent to the second (reverse) input of the divider 3, the first input of the divider 3 receives high-frequency pulses, where FT is the clock frequency of the bi-pulse signal; n is an integer. The number and which determines the sampling error is chosen

large (usually n 5; 8), BECAUSE

a bi-pulse receiver is used as a butt circuit as part of a larger device,

This.fg is accessed from a common crystal oscillator, which is not specified in the circuit of the receiver itself.

At the output of the divider 3, a signal is generated in the form of a meander with a frequency of 2E, - equal to twice the clock frequency. The phase of this signal turns out to be tied to the fronts of the bi-pulse signal due to the fact that the fronts of the bi-pulse signal are for the divider 3 bump signals. The doubler frequency clock frequency is fed to the input of the counting trigger 4, which operates from a positive voltage drop. At the outputs of the counting flip-flop 4, strobe signals are formed, which are removed for separation from a sequence of pulses of random middle and regular boundary pulses. For this, the selected fronts of the bi-pulse sequence

five

 ABOUT

arrive in parallel to the second, inputs of keys 6 and 7, the first inputs of which receive signals from the outputs of the counting trigger, From the output of key 6 to the RS-trigger 9, only random middle pulses are received, and from the output of key 7 to regular granite pulses. RS-flip-flop 9 generates positive pulses, equal in duration to half a cycle and corresponding to units in the information signal. The leading edge of these pulses is formed under the positive differential of random median pulses, and the rear front - under the negative differences of regular boundary pulses. The output signal from the RS flip-flop 9 is the output information signal and the signal from the first output of the counting flip-flop is the sync signal.

When the device is turned on or during operation, under the influence of interference, the phase of the signal at the output of the counting trigger 4 may be incorrect. In this case, when the information units arrive, the keys 6 and 7 return, ie at the output of key 6, there are

15

25

regular boundary impulses on

key output 7 - random median pulses.

At the appearance of the first information zero (the disappearance of the middle pulse in the sequence of fronts of the bi-pulse signal), at the output of the RS flip-flop 9, an elongated control pulse is generated that arrives at the additional key 5. At the same time, the pulse

from the output of the key b through inverter 8

- with

enters an additional key 5.

At the output of the additional key 5, a pulse of setting to zero of the counting trigger 4 is formed. In this case, the counting trigger 4 changes the phase and thereby eliminates the false phasing mode.

Claims (1)

Invention Formula A bi-pulse receiver containing a matching unit, whose input is the first receiver input, junction lock, counting trigger and two keys, is used so that, in order to increase the noise immunity to edge distortion, a divider, an RS flip-flop, an inverter and an additional key are entered, with the output of the matching unit che312989434 Cutting the junction lock is connected to the inverter and an additional key to the second inputs of the first and second switching inputs of the counting trigger, whose divider is also connected to the second input, the first output of which is connected to the first input of which is the second - the receiver input, and the output is connected 5 Pogo is connected to the S-input of the RS-flip-flop, to the input of the counting flip-flop, the first output of which is connected to the second output of which is connected to the first input of the additional key and the input of the first key whose output is infor The operational output of the receiver is connected to the R-input of the RS trigger of the Ik, the sync output of which is via the serially connected input output of the counting trigger.