SU1282317A2 - Device for synchronizing pulses - Google Patents

Abstract

The invention relates to a pulse technique. It is additional to auth. No. 1070687. The purpose of the invention is to improve the accuracy of the device. The introduction of the elements EXCLUSIVE OR 8 and the trigger 9, the formation of new functional connections allows to achieve the goal. At the input of the device, a signal is generated, the synchronous clock frequency, the duration of which corresponds to the duration of the input signal, and the front coincides with the first edge or cut of the clock pulse following the front of the input signal. This ensures the accuracy of its formation, not exceeding half the period of clock pulses. 5 il. o “9

Description

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The invention relates to a pulse technique and is an improvement of the device according to the authors. No. 1070687.

The aim of the invention is to improve the accuracy of the device.

Fig, 1 shows a functional diagram of the proposed device; in fig. 2-5 are time diagrams illustrating his work.

The device contains the first 1, second 2 and third 3 triggers, element OR 4, bus 5 clock pulses, input 6 and output 7 tires, element EXCLUSIVE OR 8, quarter trigger 9, D-and S-inputs of trigger 1 are connected respectively to a common bus and input bus 6, D-INPUT trigger 3, C-input trigger 9, and the output from D-BXO trigger house 2, the R-input of which is connected to the trigger trigger 3 and the first input of the element OR 4, the output of which is connected to the output bus 7, and the second input is connected to the output of the trigger 2. Moreover, the C inputs of the flip-flops 1-3 are connected to the output of the element. EXCLUSIVE OR 8, the first and second circuits of which are connected respectively to the bus 5 clock pulses, the D-input and the output of the trigger 9.

The device works as follows.

Let a pulse be received on the input bus 6 (Fig. 2 Q), the duration of which (kg) is less than the period of clock pulses (T,), and the clock edge of the clock (Fig. 2 &) does not appear during the input signal . At the output of trigger 1, a unit level appears (Fig. 2c). If trigger 9 is in the zero state (Fig. 2 d), then the C inputs of the triggers 1–3 until the input signal appears, receive pulses (Fig. 2 e), common-mode clock pulses (Fig. 26) o The front of the input signal (Fig. 2a) trigger 9 is set to one, and from the output of the EXCLUSIVE OR 8 element, the C-inputs of the flip-flops 1-3 receive pulses (Fig. 2e), which are out-of-phase clock pulses, arriving on the clock 5 pulses pulses. During the action of the input signal, the first edge of the pulse from the output of the SCREW ORDER 8 element (Fig. 2e) coincides with the cut of the clock pulse received on the bus 5 clock pulses during the action

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the input signal, the trigger 3 is set to - a single state (Fig. 2f), and a single state of the trigger 1 is confirmed (Fig. 2 p.). The signal from the output of the trigger 3, holding on the R-input trigger 2 in the zero state Ffig. 2k), simultaneously through the element OR 4 enters the output bus 7 of the device (Fig. 2e). The next edge of the pulse from the output of the EXCLUSIVE OR 8 element, the flip-flops 1 and 3 are set to the zero state (Fig. 2c) and (Fig. 2 f) and on the output bus 7 of the device appears the zero level (Fig. 2k). Thus, a pulse is formed on the output bus 7 of the device, a synchronous clock frequency, the duration of which is equal to the period of the clock pulses, and the front coincides with the first cut of the clock pulse following the front of the input signal.

Let a signal enter the input bus 6 (FIG. Over), the duration of which, ,,, is shorter than the clock pulse period (T), with the clock edge (FIG. 3b) appearing during the input signal. Then at the moment the input signal appears (Fig. 3a), a single level appears at the output of trigger 1 (Fig. 3c). and the trigger 9 is set to the zero state (Fig. 3d). The C-inputs of triggers 1-3 from the output of the EXCLUSIVE SHI 8 element (Fig. Ze) receive pulses in-phase to the clock pulses (Fig. 36). The first edge of the pulse from the output of the EXCLUSIVE OR 8 element sets the trigger 3 to a single state (Fig. 3). The output of the trigger 1 is held at the unit level (Fig. 3c), the signal from the output of the trigger 3 is blocked by the R input of the trigger 2 (Fig. 3k), simultaneously through the OR element enters the output bus 7 of the device (Fig. 3), By the next pulse front from the output of the EXCLUSIVE OR 8 element, the triggers 1 and 3 are set to the zero state (Fig. 3, f) and the zero level is formed on the output bus 7 of the device (Fig. WE). Thus, on the output bus 7 of the device, a pulse is formed, synchronous to the clock frequency, the duration of which is equal to the period of the clock pulses, and the beginning coincides with the first front

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clock pulse following the front of the input signal.

Let the input bus signal,., Whose duration is greater than the period of clock pulses (Fig. 4s (Trigger 1 is set to one (Fig. 4c) s) and trigger 9 is kept in the zero state (Fig. AC). Consequently, impulses (Fig. 4e), in-phase clock pulses (Fig. 4 &), are impressed at the output of the EXCLUSIVE OR 8. The first edge of the pulse from the output of the EXCLUSIVE OR 8 trigger 1 is held (Fig. 4c ), and the trigger 3 is set (Fig. 4O in one state. Output signal Hera 3, holding the trigger 2 in the R input the zero state (Fig. 4k), simultaneously through the element OR 4 enters the output bus 7 of the device (Fig. 4 (). When the next pulse edges come from the output of the EXCLUSIVE OR 8 element at the output of trigger 1 and 3 (and, therefore , at the output of the device, the unit state is confirmed. After the end of the input signal, the first edge of the pulse from the output of the EXCLUSIVE OR element 8 triggers 1 and 3 are set to zero (Fig. 4, I) and a zero level is formed on the output bus 7 (FIG. 4f). Thus, at the output of the device, a signal is formed that is synchronous to the clock frequency, and the front coincides with the first edge of the clock pulse, next to the front of the input signal. Let a signal enter the input bus (Fig. 5 o), the duration of which is less than T / 2, and neither the front nor the cut of the clock pulses (Fig. 5B) appear during the input signal. At the time of the appearance of the input signal at the output of trigger 1, the unit level is set to (Fig. 5c). The trigger 9 is then set to one (FIG. 5 d). At the output of the element EXCLUSIVE OR 8, pulses appear (Fig. 5.e), which propagate to Tavet pulses. 1 m pulse front from the output of the item

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NEXT OR 8, the unit level from the output of flip-flop 1 is rewritten into flip-flop 2 (Fig. 5k) and through the HSS 4 enters the output bus 7 of the device (Fig. 5E), and the flip-flop 1 returns to the zero state (Fig. 5c). The next pulse front from the output of the EXCLUSIVE OR 8 element, trigger 2, returns to the zero state (Fig. 5k) and a zero level is formed on the output bus 7 of the device (Fig. 5f). In this case, trigger 3 does not affect the operation of the device and is in the zero state.

Consequently, a signal is formed on the output bus 7 of the device, a synchronous clock frequency, the duration of which is equal to the period of the clock pulse, and the front coincides with the first cut of the clock pulse following the front of the input signal.

Thus, at the input of the proposed device, a signal is generated that is synchronous to the clock frequency, the duration of which in any case corresponds to the duration of the input signal, and the front coincides with the first edge or cut of the clock pulse following the front of the input signal, which ensures the error in its formation, do not exceed shakuyu half the period of tact pulses.

Claims (1)

Invention Formula A device for synchronizing pulses according to auth. No. 1070687, due to the fact that, in order to improve accuracy, the EXCLUSIVE OR element and the fourth trigger are introduced into it, the EXCLUSIVE SHS element is connected between the clock pulse busbar and the C inputs of the first, second and third trigger points, the second input of the element The CLARK OR is connected to the output of the fourth trigger, the C input of which is connected to the input bus and the D input to the third trigger, and the D input is connected to the clock pulse bus. FIG. g Fig.Z