JPS63125029A - Start-stop synchronizing signal generation circuit - Google Patents

Abstract

PURPOSE:To easily execute data communication even if a clock frequency and a data length are not previously set between a transmission side and a reception side by inserting a preamble bit including clock components one bit before the start bit and the stop bit of a start-stop synchronizing signal. CONSTITUTION:A preamble bit generation means 15 is provided in a start-stop synchronizing signal generation circuit so as to insert the preamble bit including the clock components one bit before the start bit and the stop bit. Since the reception side can easily decide the clock frequency and the data length by detecting the preamble bit, the data communication can be possible even if they are not previously set on the transmission side and the reception side. Thus the communication between equipments whose data lengths are different can be easily executed.

Description

[Detailed Description of the Invention] [Summary] In the asynchronous signal generation circuit, by inserting a preamble bit containing a clock component one bit before the start bit and stop bit of the asynchronous signal, the transmission side and the receiving side can be This allows data communication to be easily performed between the computer and the computer without setting the clock frequency and data length.

[Industrial application field]

The present invention relates to an improvement of an asynchronous signal generating circuit.

Generally, start-stop synchronization signals are used for data communication between personal computers, etc., but they enable mutual communication without having to set the clock frequency and data length between the sending and receiving sides in advance. This is desirable.

[Conventional technology]

FIG. 4 is a block diagram of an asynchronous communication device using a conventional example. FIG. 4(a) is an asynchronous signal generating circuit of the conventional example, and FIG. 4(b) is a receiving circuit for FIG. 4(a). FIG. 5 shows an explanatory diagram of the operation of FIG. 4. Note that the numbers on the left side of FIG. 5 indicate the waveforms of the portions with the same numbers in FIG. Below, the fifth
The operation shown in FIG. 4 will be explained with reference to the drawings.

First, in order to communicate using the start-stop synchronization method, the counter 2 in FIG. When the first predetermined value is reached, the selector 5 uses the output from the decoder 3 to select the L level start bit ST indicating the start of data and
It is output via a type flip-flow knob (hereinafter abbreviated as D-FF) 6. As a result, narrow pulses (commonly known as whiskers) caused by the operation of the selector are removed.

Next, the data from the data generator 4 synchronized with the clock frequency f, at a second predetermined value, is successively selected by an 11 level stop pixel (SP) indicating the end of this data at a third predetermined value. The start-stop synchronization signal for one unit of data as shown in Figure 5-■ is sent out, and by repeating this, the data is sent to the receiving side.

Now, in the receiving circuit shown in Fig. 4, the received asynchronous signal is sampled by the D-FF 7 using the high-speed clock from the high-speed clock generator 8, and an asynchronous signal that is almost the same as that on the transmitting side is obtained. (See Figure 5-○, ■).

Then, the output of the terminal Q of the D-FF7 is applied to the AND circuit 13 and the falling detector IO, and the latter produces a falling detection signal as shown in Figure 5-0, which is an asynchronous signal. Indicates the beginning.

This detection output is the reset set FF (hereinafter referred to as R5-FF).
) 111 n frequency divider 9. Data length counter 1
However, as shown in Fig. 5-■, R5-FF is set, the @ child Q becomes the IK level, and the AND circuit 13 is turned on, so the asynchronous signal added here becomes D. - Output via FF14.

On the other hand, the fall detector is reset by the output of R5-PF, and the n frequency divider 9 divides the high speed clock according to a preset frequency division ratio.

The rising edge of the frequency-divided pulse is placed in the middle of the asynchronous signal.

Furthermore, since the data length counter 12 is configured to send out an output after counting a preset number of counts, it starts counting the output of the n frequency divider 9 with the output of the falling edge detector 10, After counting, the output is sent to R5-FF ti as shown in Figure 5-■, and this 5R-FF
(See Figure 5-■). Then, the AND circuit 13 is turned off and one unit of data can be extracted as shown in FIG. 5--.

[Problem that the invention seeks to solve]

However, as mentioned above, before starting data communication, the transmitting and receiving sides have to set the clock frequency (i.e.

There is a problem in that the frequency division ratio) and data length must be set in advance. This makes operation cumbersome.

[Means for solving problems]

The above problem is solved by the asynchronous signal generating circuit shown in FIG.

Reference numeral 15 denotes a preamble bit generating means for generating a preamble bit containing a clock component, and this means generates a signal in which a preamble bit is inserted one bit before the start bit and stop bit in the asynchronous signal.

[Effect]

In the present invention, a preamble bit generating means 15 is provided in the asynchronous signal generating circuit to insert a preamble bit containing a clock component one bit before the start bit and stop bit.

Therefore, since the receiving side can easily determine the clock frequency and data length by detecting this preamble bit, data communication is possible without having to set these in advance on the transmitting and receiving sides.

〔Example〕

FIG. 2 is a block diagram of an asynchronous communication device using an embodiment of the present invention, FIG. 2(a) is an asynchronous signal generation circuit of the embodiment of the present invention, and FIG. FIG. 3 shows the receiving circuit for (a), and FIG. 3 is an explanatory diagram of the operation of FIG. Note that the same reference numerals indicate the same objects throughout the figures. The operation shown in FIG. 2 will be explained below with reference to FIG.

First, the asynchronous signal generating circuit of FIG. 2(a) uses the counter 161. By controlling the selector 171 using the decoder 162, the preamble bit generator 1 is generated one bit before the start bit ST and stop bit SP in the asynchronous signal.
Preamble bit P of frequency Ha transmitted from 51
Insert 1 bit of RE-1 and PRl-2, D-FF6
A signal as shown in Fig. 3-■ is sent to the outside via the

Here, the clock frequency is assumed to be fo.

Next, in the receiving circuit shown in FIG. Rise detector 2
The rising and falling edges are detected at 0 and added to the bit count enable detector (hereinafter abbreviated as BCE) 22 (see FIG. 3--). Therefore, a pulse equal to the interval between the falling edge and the rising edge of the preamble bit PRE-1 is outputted from here, which indicates a two-clock period (see FIG. 3--).

Since this output is added to the up counter 24.

The counter 24 counts the high-speed clock only during this output, and after adding the count value to the latch circuit 25 and latching it, the latched value is added to the down counter 26 as a load value.

Note that launching and loading of the count value at this time is performed by the output of the differentiating circuit 23.

Therefore, the down counter 26 counts down directly from the low toy and when it reaches O, the load pulse 2 is applied from the decoder to the down counter via the OR circuit 27.
The count value latched by the latch circuit is loaded into the down counter again, and the same countdown operation as described above is repeated.

Also, the 0 detection output 2 shown in FIG. 3-■ from the decoder 28
is divided by two by a frequency divider 30, and a clock having a frequency r0 as shown in FIG. 3-2 is automatically reproduced.

Next, a preamble bit (hereinafter referred to as PRE) is inserted one bit before the stop bit SP to determine the data length.
It is necessary to detect the falling edge of (abbreviated as -2), and for this purpose, a window with a width in the middle of the data is opened as shown in FIG.

This means that in the case of data, the state in the middle does not change, but
In the case of PRE-2, there is a falling edge in the middle, so if you detect whether or not there is a falling edge in the window, you can detect the falling edge of the data in PRE-2.
It will not be mistakenly detected as RE-2.

These windows are created by extracting every other 0 detection output inside the decoder 28 and decoding the values before and after it.
Create a pulse as shown in Figure-■ and apply it to the PER-2 detector 21.

Therefore, if the output of the falling detector 10 is input to the PRE-2 detector when this pulse comes, PRE! -2 falling edge is detected (see Figure 3 - [Phase]).

Incidentally, this PRE-2 detector sends out an H level signal at the first output from the falling edge detector 10, and PRI! -2 is detected, the signal changed to an L level signal is sent to the outside as a valid bit, and this is sent to the AND circuit 29.
Since it is added to the D-FF only during the ■ level signal.
The start-stop synchronization signal output from 1B passes through the AND circuit 29, is re-inputted by the D-FF, and the start-stop synchronization signal shown in FIG. 2-2 is output.

That is, the preamble bits PER-1 and PER-2 are used as the start bit and stop bit of the asynchronous signal.

By adding 1 bit before the data length, data communication can be easily performed without setting the clock frequency and data length in advance. Communication can be done easily.

〔Effect of the invention〕

According to the present invention, as described above in detail.

Even if the clock frequency and data length are not set in advance, the effect is that data communication can be easily performed. This allows easy communication between devices with different data lengths.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. block diagram of the ivy diagram, FIG. 5 shows an explanatory diagram of the operation of FIG. 4. In the figure, 15 is a preamble bit generating means; 16 is a controller; 17 indicates a selector. Unexploded Kishi J-ribu dead... Kaya 1 diagram OOO■■■OO■■■■ ax 4 garden

Claims (1)

[Claims] Start-stop synchronization is performed by selecting input start bits, data, and stop bits with a selector (17) driven by the output of a controller (16), and arranging the start bit, data, and stop bit in this order. In the asynchronous signal generation circuit that generates the signal, a preamble bit generating means (15) that generates a preamble bit including a clock component is provided, and the preamble bit is inserted one bit before the start bit and stop bit in the asynchronous signal. An astop synchronization signal generation circuit characterized by the insertion of an asynchronous signal generator.