JPS5980047A - Biphase code demodulator - Google Patents

Abstract

PURPOSE:To eliminate the reception unable state of a burst signal due to noise, by resetting a demodulator to its initial state when a signal which is free from phase inversion is detected. CONSTITUTION:When a normal signal burst is supplied to an input terminal 1, the biphase code has phase inversion at the converting point of each element. Therefore, the output signal of a D type FF151 is set at logic 0. Then a start- stop synchronizing means is not reset and delivers an output signal. When noise is inputted to the terminal 1, the output signal of an exclusive OR circuit 11 is set at logic 1. The output signal of the FF151 is also set at logic 1. This output signal resets latch circuits 3 and 6, a dividing circuit 8, and D type FF9, 10 and 13 respectively and is delayed by a delay circuit 152 to reset the FF151. As a result, a demodulator is reset to its initial state when the start-stop synchronizing means is started by noise and the demodulation is started.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a bi-phase code demodulation device used in a baseband transmission method using bi-phase codes, and particularly to a bi-phase code demodulation device used in a baseband transmission system using bi-phase codes, and in particular, The present invention relates to a bi-phase code demodulator equipped with a start-stop synchronization means in a burst transmission system.

[Technical background of the invention]

As shown in Fig. 1, a biphase code is a code in which there is no phase inversion within the width T of a unit element (bit), for example, a logic 1 (or O), and a code in which there is a phase inversion, a logic 0 (
or 1) is one of the expression formats of a binary code, which always involves a phase inversion at the conversion point of each element. A system for intermittently transmitting signal blocks S1, S2, .

In such a burst transmission method, it is necessary to perform readout taroming, or synchronization, in accordance with the transmission timing of the code on the transmitter side.
A start-stop synchronization method is generally used in which a start element (bit) is used as a start element (bit), and synchronization is pulled in using this start element.

FIG. 3 is a block diagram showing a conventional pi-phase demodulator equipped with a start-stop synchronization means applied to such a burst transmission system, and FIG. 4 is a time chart showing its operation.

In FIG. 3, 1 is an input terminal, 2 is a level detector that outputs a signal when the input signal exceeds a predetermined level, 3 is a launch circuit that stores the output of level detector 2, and 4
5 is an AND circuit; 6 is a latch circuit that stores the output of the AND circuit 5 and controls the frequency dividing circuit 8; 7 is a high-order clock pulse 8 is a frequency divider circuit as an astop synchronization means that generates various timing pulses based on clock pulses; 9 and 10 are D-type flip-flops forming a shift register; 11 is an exclusive OR circuit;
12 is an inverter, 13 is a D-type flip-flop, 14
In a configuration in which is more than an output, an input signal PA (FIG. 4A) consisting of a biphase code to which a start element ST is added inputted to an input terminal 1 is input to a level detector 2.
is input to the waveform shaping circuit 4, and when the input signal exceeds a predetermined level, the level detector 2 drives the launch circuit 3, and outputs the output signal PB from the latch circuit 3 (Fig. 4B).
is output. The waveform shaping circuit 4 has a Schmitt function and shapes the waveform of the input signal PA into a signal Pc (FIG. 4C).

Signals pB and Pc are input to an AND circuit 5, and its output signal PD (D in FIG. 4) drives a latch circuit 6, and the latch circuit 6 uses its output signal PE (E in FIG. 4) to drive a frequency divider circuit 8.
When the signal PE is logic O, the frequency divider circuit 8 is kept in a reset state, and when the signal PE is logic 1, the frequency divider circuit 8 divides the high-order clock pulse to output the timing signal PF (FIG. 4F) and Pc. (Figure 4G) is output.

10,000, the signal Pc (FIG. 4C) is input to a shift register composed of D-type flip-flops 9 and 10,
It is sampled at the rising edge of the timing signal PF (FIG. 4F). The output signal PR of the D-type flip-flop 9 (H in FIG. 4) and the four-part output signal PJ (J in FIG. 4) of the D-type flip-flop 10 are input to an exclusive OR circuit 11, and both inputs Logic 0 if they are equal, logic 1 if they are different
output signal PK (K in FIG. 4). This output signal pK is input to the D-type flip-flop 13 and sampled at the rising edge of the inverted signal of the timing signal PG (FIG. 4G).

The output signal PL (FIG. 4L) of the D-type flip 70 knob 13 is a demodulated data signal and is output from the output terminal 14.

The above is an explanation of the process in which a data signal is demodulated from a biphase code to which a start element ST has been added. When the (number of bits) is reached, the frequency divider circuit 8 and its peripheral circuits may be reset to return to the initial reception standby state.

[Problems with background technology]

By the way, in the conventional bi-phase code demodulator configured as described above, when noise exceeding a predetermined threshold level is input in the reception standby state (an interval where no signal burst exists), the noise is started.・There was a drawback that the demodulation circuit started operating when it was mistaken as an element. That is, as shown in FIG. 5A, when a synchronization clock started due to noise and a signal burst overlap, a problem arises in that the function of demodulating the signal burst stops.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a novel pi-phase code demodulation circuit that eliminates the inconvenience of malfunction due to noise.

[Summary of the invention]

Therefore, the present invention focuses on the fact that a biphase code necessarily involves a phase inversion at the conversion point of each element (bit), and provides a phase detection circuit to detect the phase inversion. The above object has been achieved by resetting the start-stop synchronization means and its peripheral circuits to return the demodulator to the initial reception standby state when the input signal is noisy, that is, when the input signal is noise.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to FIG.

FIG. 6 shows an embodiment of the biphase demodulation circuit according to the present invention, except that a phase detection circuit 15 consisting of a D-type flip-flop 151 and a delay circuit 152 is provided. Since it has the same configuration as
Common parts are denoted by the same reference numerals, and detailed explanations will be omitted.

In FIG. 6, the output signal PK(
4K) is input to the D-type flip-flop 51 and sampled at the rising edge of the timing signal Pc (FIG. 4G). If a normal signal burst is input to input terminal 1 at this time, the D-type flip 7
The output signal PM of the 0 knob 151 (M in Figure 4) is always logic 0.
becomes. This output signal PM is applied to the latch circuits 3 and 6, the frequency divider circuit 8, the D-type flip 70 and the reset terminal of the switch 3, respectively, or the signal PM is always logic qo, so the asynchronous synchronization means I hope it gets reset (
, the output signal PL is output 1- similarly to the conventional bi-phase demodulation circuit shown in FIG.

Next, the operation when noise is input to the input terminal 1 will be explained with reference to FIG. In addition, Figure 7A-M is the same as Figure 4A.
-M, and in FIG. 7, the signal in FIG. 4 is shown with a dash.

The demodulation operation is started by the noise input PA□ (Fig. 7A) in the same way as when inputting the signal burst described above, but at this time,
In the D-type flip-flop 151, the exclusive OR circuit 1 is sampled at the rising edge of the timing signal PG'.
The output signal PK' (K in FIG. 7) of 1 becomes logic 1, and the D-type flip-flop frequency divider circuit 8 and the D-type flip-flop divider circuit 9
．． 1o and 13, and further delay circuit 152
is delayed to reset the D-type flip-flip 151. Note that the delay circuit 152 includes a D-type flip-flop 1
It can be omitted when using the internal delay of 51.

Therefore, when the start-stop synchronization means is activated by noise and a demodulation operation is started, it is immediately reset, returns to the initial state, and enters the reception standby state. This state is shown in Figure 5B.
Shown below.

[Efficacy of invention]

As explained above, according to the present invention, each element (
A phase detection port +I is provided to detect a phase reversal at the transition point of each element. In this case, the asynchronous synchronization means and its peripheral circuits are reset, and the demodulation device returns to the initial reception standby state. If the asynchronous synchronization means misidentifies the noise as a start element and starts demodulation operation. Since the demodulator is immediately returned to its initial state, it is possible to eliminate the inconvenience of not being able to receive signal bursts due to noise.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the Pi-Phase' code, Fig. 2 is an explanatory diagram of the burst transmission method, Fig. 3 is a block diagram of a conventional biphase code demodulation device, and Figs. A timing chart showing the signal waveforms of each part when a signal burst is input in the device, FIG. 5A1B is an explanatory diagram showing the operation when noise is input, FIG. 6 is a block diagram of the biphase code demodulation device according to the present invention, and FIG. is a timing chart showing signal waveforms of various parts when noise is input. 1...Input terminal, 2...Level detector, 3.6...
・Latch circuit, 4... Waveform shaping circuit, 7... High-order clock pulse generator, 8... Frequency dividing circuit, 9.1o,
13.151...°D type flip-flop, 14...
Output terminal, 15...phase detection circuit, 152...delay circuit. Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] In a bi-phase code demodulator equipped with a start-stop synchronization means that starts start-stop synchronization operation by receiving a start element of a signal burst composed of a bi-phase code, presence or absence of phase inversion at a conversion point of each element of a received signal and detecting that the phase inversion does not exist, the phase detection circuit is configured to generate a reset signal that resets the start-stop synchronization means to return to a reception standby state. Bi-phase code demodulator.