JP3248382B2 - FM decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM decoder for decoding data in an FM format (hereinafter, referred to as FM format data), which is one of encoding systems in serial transmission of data communication.

[0002]

2. Description of the Related Art First, the above-mentioned FM format data will be described with reference to FIG. In this figure, transmission data D is an NRZ (nonrr) consisting of a combination of "0" and "1" assigned to each bit cell BC.
return to zero) data.

The FM format data is obtained by replacing "0" and "1" of the transmission data D with a long-period bit BL and a short-period bit BS, respectively. The FM format data has two types of formats depending on whether the short cycle bit BS (or the long cycle bit BL) is replaced with “0” or “1”. In the FM format data DFM0 in FIG. 5, "0" of the transmission data D is replaced by short-period bits BS and "1" is replaced by long-period bits BL. On the other hand, the FM format data DFM1 is obtained by replacing "0" of the transmission data D with the long-period bit BL and "1" with the short-period bit BS. Since the FM format data has each bit inverted at the boundary of the bit cell BC (however, the short-period bit BS is also inverted at the center of the bit cell BC), the transmission data D and the synchronous clock must be transmitted. Can be.

In the case where the above-mentioned FM format data is used for data transmission, as shown in FIG. 6, a data in which a preamble composed of continuous long-period bits of 4 bits or more is added before data to be originally transmitted is used. . This preamble is used when synchronizing on the receiving side. The details of this synchronization pull-in will be described later.
The reason for using long-period bits for the preamble is that short-period bits cannot be synchronized because they are inverted not only at the bit cell boundaries but also at the center of the bit cells as described above.

Next, from the FM format data, the NRZ
A configuration of a conventional FM decoder that decodes transmission data of the scheme will be described with reference to FIG. Note that a preamble composed of long-period bits that are continuous for at least 4 bits is added to the FM format data described below. In this figure, a DPLL (digital phase locked loop) 1 is for generating a synchronization signal SD synchronized with FM format data DFM, and includes an edge detection unit 3, an edge filter 4, a synchronization shift detection unit 5, It comprises a counter 6 and a decoder 7.

The edge detector 3 detects rising and falling edges of the FM format data DFM supplied to the input terminal a as shown in FIG. 8 and detects pulses corresponding to the detected edges Sea1, Sea2,. And generates an edge detection signal Sea. The edge filter 4 removes the pulse located at the center of the bit cell BC from the pulse of the edge detection signal Sea (see the arrow in FIG. 9), and the edge signal S′e
Generate a. In the edge detection signal Sea shown in FIG. 8, since there is no pulse located at the center of the bit cell BC, the edge signal S'ea has the same waveform as the edge detection signal Sea.

In FIG. 7, a reference clock Ck supplied to an input terminal b supplies a clock having a cycle eight times as long as one bit, and is counted by a 3-bit octal counter 6.

[0008] The out-of-synchronization detecting section 5 checks the count value of the counter 6 when the edge signal S'ea is supplied, and when the count value is "1" to "3", When the decrement signal SDT for decrementing the count value is “4” to “7”, the counter 6 outputs an increment signal SIT for incrementing the count value of the counter 6.

The counter 6 is a 3-bit counter, which always counts up the reference clock Ck. When a decrement signal SDT is supplied from the synchronization deviation detecting unit 5, the count value is decremented and the increment signal SIT is incremented. Is supplied, the count value is incremented. The decoder 7 reads the count value of the counter 6 and outputs a synchronizing signal SD which becomes "H" level when the count value is "0".

Next, the operation of the above-described synchronization pull-in will be described with reference to a time chart shown in FIG. In this figure, assuming that the count value of the counter 6 at the time when the pulse S'ea1 of the edge signal S'ea is supplied is "4", the synchronization shift detecting unit 5 outputs the increment signal SIT
Is supplied to the counter 6. Thereby, the counter 6
The count value is incremented from “4” to “5”. Thereafter, the synchronization shift detecting unit 5 supplies the increment signal SIT to the counter 6 every time the pulse S'ea2, the pulse S'ea3, and the pulse S'ea4 of the edge signal S'ea are supplied. As a result, the counter 6 increments the count value from “5” → “6”, “6” → “7”,... Then, at time t0, synchronization is established when the count value of the counter 6 changes from "7" to "0".

Next, the configuration of the decoding unit 2 shown in FIG. 7 will be described. In the figure, a counter 8 is a 3-bit octal counter, and a reference clock Ck supplied to an input terminal b.
And the decoder 7 of the DPLL · 1
The count value is cleared each time the synchronization signal SD supplied from the CPU becomes the "H" level. When the count value is “0” to “3”, the counter 8 is at “L” level,
The reception clock signal CJ which goes to "H" level at "7"
(See FIG. 9).

The decoder 9 outputs the FM format data D
This is for decoding the reception data DNRZ of the NRZ system from FM, and when the count output of the counter 8 is “2” and “6”.
In each case, the value of the FM format data DFM is checked, and if the values match, "0";
1 ". Then, the reception data DNRZ shown in FIG. 9 is output according to the recognition result.

[0013]

By the way, in the above-mentioned conventional FM decoder, DPLL · 1 and decoding unit 2
Therefore, there is a problem that the circuit is large and complicated. In addition, conventional FM
In the decoder, the count value of the counter 6 is incremented or decremented at the time of synchronization pull-in. Since the counter 6 is a 3-bit octal counter, a maximum of 4 bits of edges of the FM format data DFM are required until synchronization is established. Therefore, there is a disadvantage that it takes time to establish synchronization. The present invention
It is an object of the present invention to provide an FM decoder having a simple circuit configuration and capable of establishing synchronization in a short time.

[0014]

According to the first aspect of the present invention,
F for decoding NRZ data from FM format data
In the M decoder, an edge detection circuit for detecting a rising edge and a falling edge of the FM format data and outputting an edge signal; and a 1 bit time longer than half a 1 bit time of the FM format data, reset by the edge signal. Counting means for counting a shorter time; a synchronizing signal output circuit for outputting a synchronizing signal when the edge signal is received after the output of the counting means rises; and a synchronizing signal for resetting the FM format data. A counter for counting clock pulses having a cycle shorter than one bit time; and decoding means for decoding the NRZ data from the FM format data based on an output of the counter.

According to a second aspect of the present invention, the F
In the M decoder, the edge detection circuit includes the FM decoder.
First to detect rising edge of format data
, A second detection circuit for detecting a falling edge of the FM format data, and the first and second detection circuits.
And an OR circuit for calculating the logical sum of the outputs of the detection circuits.

[0016]

According to the first aspect of the present invention, the edge detection circuit detects a rising edge and a falling edge of the FM format data and outputs an edge signal, and the counting means is reset by the edge signal, and the FM format data is reset. The time longer than half of the 1-bit time is counted. The synchronization signal output circuit is
When the edge signal is received after the output of the counting means has risen, a synchronizing signal is output, and the counter is reset by the synchronizing signal and counts clock pulses having a cycle shorter than one bit time of the FM format data. The decoding means decodes the NRZ data from the FM format data based on the output of the counter.

According to the second aspect of the present invention, the first detection circuit detects a rising edge of FM format data, the second detection circuit detects a falling edge of FM format data, and an OR circuit As a result, the logical sum of the outputs of the first and second detection circuits is obtained.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating an embodiment of the present invention.
FIG. 9 is a block diagram illustrating a configuration of an M decoder. In this figure, portions corresponding to the respective portions in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted. In the FM decoder shown in this figure, a long-period bit detector 10 is newly provided in place of DPLL · 1 in FIG. Further, the FM format data D'FM supplied to the input terminal a includes the above-described preamble (see FIG. 6). There is no need to provide it, and at least one long-bit bit is sufficient.

Next, the configuration of the long-period bit detector 10 will be described with reference to the block diagram shown in FIG. In this figure, D-FF (delay-flip flop) 11 is
FM format data D'FM is supplied to the terminal and CL
A reference clock Ck is supplied to a K (clock) terminal.
The D-FF 12 has a D terminal supplied with an output Q11 from a Q terminal of the D-FF 11, and a CLK terminal supplied with a reference clock Ck.

The AND gate 14 has one input terminal supplied with the output Q11 from the Q terminal of the D-FF 11 via the inverter 13, and the other input terminal supplied with the output Q12 from the Q terminal of the D-FF 12. You. AND gate 16
The output Q11 of the Q terminal of the D-FF 11 is supplied to one input terminal, and the D-FF 11
An output Q12 from the Q terminal of the FF12 is supplied.

The OR gate 17 has one input terminal supplied with the output Q14 of the AND gate 14 and the other input terminal supplied with the output Q16 of the AND gate 16. Counter 1
Reference numeral 8 denotes a 3-bit octal counter. The output Q17 of the OR gate 17 is supplied to the CLR terminal, and the reference clock Ck is supplied to the CLK terminal. Counting result of the counter 18, the 2 ⁰ QA terminal, 2 ¹ from QB terminal, 2 ² are taken out from each QC terminal.

The AND gate 19 has one input terminal supplied with the output of the QB terminal of the counter 18 and the other input terminal supplied with the output of the QC terminal of the counter 18.
When the count output of 8 becomes “6”, the output is set to “H” level. RS-FF (reset set-flip flop) 20
Is the output Q of the AND gate 19 at its S (set) terminal.
19 is supplied, and OR gate 1 is connected to its R (reset) terminal.
7 output Q17 is provided. The AND gate 21 has one input terminal supplied with the output Q20 from the Q terminal of the RS-FF 20 and the other input terminal supplied with the output Q17 of the OR gate 17.
Is supplied. Then, the AND gate 21 supplies the output to the counter 8 shown in FIG. 1 as a synchronization signal S'D.

Next, the operation of the above-described FM decoder will be described with reference to time charts shown in FIGS. First, when a power supply (not shown) is turned on, the counter 8 and the counter 18 of the long cycle bit detector 10 start counting the reference clock Ck supplied to the input terminal b. Subsequently, when FM format data D'FM is supplied to the input terminal a, the D-FF 11 captures the FM format data D'FM at the rising edge of the reference clock Ck as shown in FIG. D-FF1
2 to the Q terminal.

The D-FF 12 is the output Q11 of the D-FF 11
At the rising edge of the reference clock Ck,
The output Q12 is output. AND gate 14 is a D-FF1
When the output Q11 of 1 is at the "L" level and the output Q12 of the D-FF 12 is at the "H" level, the output Q14 is set at the "H" level. That is, the AND gate 14 detects the falling edge of the FM format data D'FM.

The AND gate 16 determines that the output Q12 of the D-FF 12 is at the "L" level and the output Q11 of the D-FF 11
Is "H" level, the output Q16 is set to "H" level. That is, the AND gate 16 detects the rising edge of the FM format data D'FM.

The OR gate 17 ORs the output Q14 of the AND gate 14 and the output Q16 of the AND gate 16, and outputs the result as an output Q17 (see FIG. 3). This output Q
Reference numeral 17 is a pulse corresponding to the rising and falling edges of the FM format data D'FM.

The counter 18 always has a reference clock Ck
Are counted up, and each time a pulse of the output Q17 of the OR gate 17 is supplied to the CLR terminal, the count value is cleared. When the count result of the counter 18 becomes "011"("6"), the AND gate 19 changes its output Q19 to "H" level.

When the output Q19 of the AND gate 19 goes high, the RS-FF 20 is set to hold the output Q20 (see FIG. 3) at the high level, and the output Q17 of the OR gate 17 goes high. When it becomes "H" level, it is reset and its output Q20 is held at "L" level.

When the output Q17 of the OR gate 17 is at the "H" level and the output Q20 of the RS-FF 20 is at the "H" level, the AND gate 21 outputs a synchronizing signal S 'whose output is at the "H" level. D is supplied to the counter 8. The synchronization signal S'D is a signal composed of pulses corresponding to the rising edge and the falling edge of the long-period bit BL of the FM format data D'FM.

As shown in FIG. 4, when the synchronization signal S'D is at "H" level at time t'0, the count value of the counter 8 is cleared. Thereby, synchronization is established. Thereafter, the count value of the counter 8 is cleared every time the synchronization signal S'D becomes "H" level. When the count value is "0" to "3",
It outputs the receiving clock CJ which becomes "H" level when the level is "L" level and "4" to "7".

The decoder 9 outputs the FM format data D
This is for decoding the reception data DNRZ of the NRZ system from FM, and when the count output of the counter 8 is “2” and “6”.
In each case, the value of the FM format data DFM is checked, and if the values match, "0";
1 ". Then, the reception data DNRZ shown in FIG. 9 is output according to the recognition result.

[0032]

As described above, according to the present invention, it is possible to decode received data from FM format data with a simple circuit configuration and to establish synchronization within one bit period of FM format data. Therefore, synchronization can be established in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an FM decoder according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a long-period bit detector 10 shown in FIG.

FIG. 3 is a time chart for explaining the operation of the long cycle bit detector 10 shown in FIG. 1;

FIG. 4 is a time chart for explaining the operation of the FM decoder according to one embodiment of the present invention;

FIG. 5 is a time chart illustrating FM format data.

FIG. 6 is a diagram illustrating a preamble.

FIG. 7 is a block diagram showing a configuration of a conventional FM decoder.

FIG. 8 is a time chart illustrating synchronization pull-in in a conventional FM decoder.

FIG. 9 is a time chart illustrating an operation after synchronization is established in a conventional FM decoder.

[Explanation of symbols]

 8 Counter 9 Decoder 10 Long-period bit detector D'FM FM format data S'D Synchronization signal Ck Reference clock CJ Receive clock DNRZ Receive data

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshinori Okajima 150 Motoyashiki, Miyamachi, Toyohashi-city, Aichi Prefecture Shinko Electric Machinery Co., Ltd. (56) References JP-A-4-316126 (JP, A) JP-A-57-6423 (JP, A) JP-A-62-271263 (JP, A) JP-A-8-204759 ( JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 5/14

Claims (2)

(57) [Claims] 1. An FM decoder for decoding NRZ data from FM format data, comprising: an edge detection circuit for detecting a rising edge and a falling edge of the FM format data and outputting an edge signal; Counting means for counting a time longer than half of one bit time of the format data and shorter than one bit time; a synchronizing signal output circuit for outputting a synchronizing signal when receiving the edge signal after the output of the counting means rises A counter that is reset by the synchronization signal and counts a clock pulse having a cycle shorter than one bit time of the FM format data; and a decoding unit that decodes the NRZ data from the FM format data based on an output of the counter. , An FM decoder comprising: 2. An edge detection circuit comprising: a first detection circuit for detecting a rising edge of the FM format data; a second detection circuit for detecting a falling edge of the FM format data; 2. An OR circuit for calculating a logical sum of outputs of the second detection circuit.
The FM decoder as described.