SU1252961A1 - Device for in-phase reception of pulse signals - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve noise immunity. The device contains a D-flip-flop I, an element AND 2, an element AND-NOT 3, a block 5 of a phase AFC, the goal is achieved by the introduction of an element AND-NOT 4, Block 5 consists of an element NOT 11, two D-triggers 6 and 7 and three elements AND -NO 8 to 10. If another input is received at the 1st input signal (EC), then the phasing process is repeated. In the absence of an EU, a D-flip-flop 6 is set to state O. If the EU is ahead in phase of the clock signal, then at the output of the NAND element 10 also forms signals in-phase with clock pulses. In this case, phasing is carried out with the help of the HE 11 element, the D-flip-flop 1, the D-flip-flop 7, the Y-HE 4 and I 2 elements, the 9 and 10 elements. f-ly, il.

Description

The invention relates to radio engineering and can be used in the construction of devices for the in-phase reception of pulse signals.

The purpose of the invention is to improve noise immunity.

The drawing shows a structural electrical circuit of the proposed device.

A common-mode device for receiving pulse signals contains D-Trigger 1, Element I 2, Elements N-NE 3 and 4, Block 5 of the phase-locked loop (PLL) consisting of D-Triggers 6 and 7, Elements N-NE 8-10 and item 11,

The device works as follows.

Suppose that the input signal from the communication line arriving at the clock input of the D-flip-flop 1 is lagging in phase from the signal arriving at the clock input of the PLL unit 5. In this case, the leading edge of the input signal sets the D-flip-flop 1 to the state. The output signals from the D-flip-flop 1 with a logic level 1 are received at the information inputs of the D-flip-flop 6 and 7 of the PLL 5, the clock inputs of which are supplied to the clock pulses respectively and the input element HE 11. The leading edge of the pulse from the element NOT 1 D-flip-flop 6 is set to state 1, the output of the D-flip-flop 6 is fed to the second inputs of the AND-HEY elements 3 and 8. The first inputs of these elements are. clock pulses are given from the output and input of the element NOT 11. At the third input of the element AND-NO 3, a leading pulse forms a negative impulse, which is passed through the set input of the D-trigger I and sets it to the O state. The pulses from the output of the element AND-NE 8 through the element AND-NOT 10, which acts as the element OR, arrive at the output of the device, IF another phase is repeated after the first input signal, this phasing process repeats. In the absence of an input signal, the first D-flip-flop is set to state O.

If the input signal is ahead of the clock in phase, then the output of the NAND 10 element is also formed

common-mode signals with clock pulses. In this case, the process of phasing is similar to that indicated and is carried out with the help of the element HE 1, the D-flip-flops AND-NOT 4, the element AND-AND-HE 9 and 10.

1 and 7, element 2, elements

to

Claims (2)

1. A common-mode device for receiving pulse signals containing a series-connected D flip-flop and a phase-locked loop 5 frequencies (PLLs), as well as serially connected first NAND element and AND element, the output of which is connected to the setup input of the D-trigger, the clock input of which is the cyclic input of the device, the clock input of which is the second input of the PLL, The second outputs of which are connected to the first and second inputs of the first NAND element, the third output of the PLL unit is the output of the device, characterized in that, in order to increase noise immunity, a second AND NAND element is inserted into it, and the D-flip-flop output is connected to third input of the first AND-NO element and to first input of second AND-NO element, second and third inputs connected respectively to the clock input of the fourth output device and the PLL unit, an output of second AND-NO element is connected to another input of the I. 2. A POP.1 device, characterized in that the PLL unit consists of a NOT element, two D-flip-flops and three NAND elements, the input of the element NOT being the second input of the PLL unit and combined with the first input of the first NAND element and the clocking input of the second D-flip-flop, the information input of which is combined with the information input of the first D-flip-flop and is the first input of the PLL, the output element NOT connected to the clock input of the first D-flip-flop and the first input of the second NAND element and is the first output of the PLL, the output of the first D-flip-flop is connected to the second input of the first N-NF element and is the second output of the PLL, the output of the second D -trigger connected to 3125296 4 the second input of the second element AND-NOT cops are AND-NOT connected to the inputs and is the fourth output of the block of the third AND-NOT element, the output of which is FAGH, the outputs of the first and second ele- ral is the third output of the FAPCH