SU1293848A1 - Clock synchronization device for nrz-l signal receiver - Google Patents

Abstract

The invention relates to telecommunications and provides higher speed. The device contains inverters 1, 2, delay unit 3, elements AND-NOT 4, 5, D-triggers 6, 7, elements OR-NOT 8, OR 9, voltage divider 10, subtraction unit 11, low pass filter 12 , controlled oscillator (UG) 13. The device receives the pulse sequence of the NRZ-L signal. Elements AND 5, 4 form pulses of duration equal to the period of the code pulse of the 5 INPUT signal, which correspond to transitions of the input signal, respectively, and. D-flip-flops 6, 7 form pulses, the leading edges of which correspond to the O transition of the timing sequence, and the falling edges - to the transition to the R-inputs of the D-flip-flops 6, 7. When the phase of the zononiruyushchy oscillations at the output of the low-pass filter 12 are ahead or lagging constant value of phase mismatch signal. Under the action of this signal, the controlled generator 13 sets the initial phase. 2 Il. and S (L 1C co od 00 4ih 00

Description

one

one

The invention relates to telecommunications and can be used for clock synchronization of NRZ-L signal receivers in radio relay communication systems and fiber optic communication systems.

The aim of the invention is to increase speed.

Figure 1 shows the structural electrical circuit of the clock synchronization device of the NRZ-L signal receiver; Fig. 2 shows time diagrams of the signals explaining the operation of the clock synchronization device of the NRZ-L signal receiver.

The device clock synchronization receiver signals NRZ-L contains the first and second inverters 1 and 2 block 3 delay, the first and second elements AND-NOT 4 and 5, the first and second D-flip-flops 6 and 7, the element OR-NOT 8, the element OR 9 , voltage divider 10, subtraction unit 11, low-pass filter 12, controlled oscillator 1 3 o

The device clock synchronization receiver signal NEZ-L works as follows.

The input of the clock synchronization device of the NRZ-L signal receiver (FIG. 1) receives the pulse sequence of the NRZ-L signal (FIG. 2a, which is inverted by the second inverter 2 and fed to the first input of the second AND-NE element 5 (FIG. 26), and the second the input of which enters the signal delayed by the value of the period of the code pulse after the delay unit 3 (Fig. 2c).

At the output of the second element AND-NOT, pulses of duration equal to the period of the code pulse of the input signal are formed, which correspond to transitions of the input signal (FIG. 2 e). The first input of the first IS-NO 4 receives a pulse sequence inverted by the first inverter I (FIG. 2d), and the second input of the first AND-NO 4 input pulse sequence. At the output of the first element 4, pulses of duration equal to the period code pulse of the input signal, which correspond to the "transitions 1 input signal (fig.2e).

On the sync inputs of the first and second D-flip-flops 6 and 7 served the logical unit, when

five

0

five

5 0 5

the formation of the leading edge of the pulse at the output of the first and second Dtriggers 6 and 7 begins when the timing sequence transitions (Fig. 2g), and the formation of the trailing edge upon the transition to the R inputs of the first and second D-flip-flops 6 and 7, At the output of the second Dtrigger 7 a pulse sequence is formed (fig. 2z), at the output of the first D-flip-flop 6 - a pulse sequence (fig.2i), which is fed to the inputs of the element OR 9, the output of which is formed by the pulse sequence (fig.2k) to the first input of the block 11 deduct ani The inputs of the element OR NOT 8 receive pulse sequences from the outputs of the first and second elements AND-NOT 4 and 5 (Figure 2e) and (Figure 2e).

At the output of the element OR NOT 8, a pulse sequence is formed (FIG. 2L), which is fed to the second input of the subtracting unit 11 through a voltage divider 10 with a transfer coefficient equal to 0.5 (FIG. 2m). At the output of the subtraction unit 11, pulses are formed (FIG. 2n), corresponding to cTB Toimle of the signal differences at its first and second inputs.

If the phase of the clock oscillation at the output of the controlled oscillator 13 has not changed, then the pulses at the input 5 of the low-pass filter 12 (fig.2n) will have the same areas of positive and negative polarities and the constant component of the phase error signal at the output of the filter 12 of the lower frequencies will be zero. When the phase of the oscillating oscillation advances or lags, the areas of the pulses of positive and negative polarities will change (fig.2n) and, therefore, the output component of the low-pass filter 12 will receive a constant component of the phase error signal, under the action of which the controlled oscillator 13 will set initial phase.

Claims (1)

Invention Formula The clock synchronization device of the NRZ-L signal receiver, containing a series-connected delay unit, the first inverter and the first NAND unit, a series-connected subtraction unit, a lower filter 0 0 frequency, controlled oscillator and the first D-flip-flop, the second inverter and the second NAND unit connected in series, as well as the OR element and the second D-flip-flop, the synchronizing input of which is connected to the output of the controlled oscillator, the output of the delay unit is connected to the second input of the second the NAND element, and the combined inputs of the second inverter and the delay unit are connected to the second input of the second NAND element, with the input of the delay unit and the output of the controlled generator being the input and output of the device, I 93848 ten 15 four characterized in that, in order to improve speed, an OR-NOT element and a voltage divider are introduced in series, while the outputs of the first and second AND-NOT elements are connected respectively to the R inputs of the first and second D-flip-flops, the outputs of which through the OR element connected to the first input of the subtractor, the second input of which is connected to the output of the voltage divider, and the inputs of the OR element are NOT connected to the outputs of the first in which the AND elements are NOT. 9fae. one Well } and to i n n JT-nJTJTJTJTnjTJTJTJTJTJTJTJTj-L Editor A.Gulko F1 / yr Compiled by V.Orlov Tehred V.Kadar Order 397/59 Circulation 639Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader M. Samborska