SU915267A1 - DEVICE OF INFLUENTIFIC RECEPTION OF PULSE SIGNALS G - Google Patents

Description

The invention relates to radio engineering and can be used when building devices of the in-phase reception of pulse signals.

A device of in-phase reception of pulsed signals, containing the first trigger connected in series, the phase locked loop (PLL) and the phasing unit, the input of the first trigger and the second input of the PLL are a cyclic input, and the third PLL input and the second input of the phasing unit are a clock input RU

However, the reliability of the reception of the pulse signals of the known device is low.

The purpose of the invention is to increase the reliability of reception.

The goal is achieved by the fact that _m-phase device receiving pulse signals introduced serially connected and a second AND _gate; trigger whose output is connected to

2

the fourth input of the PLL, the other outputs of which are connected to the inputs of the element And, the output of which is connected to the third input of the phasing unit,

• while the second input of the second trigger is connected to the third input of the PLL, the PLL is designed as a first trigger, the outputs of which are connected via the second and third triggers to the inputs of the OR element, while the output of the inverter is connected to the second input of the second trigger, moreover, the inputs of the inverter, the first, second and third flip-flops are the corresponding inputs of the PLL unit, and the outputs of the first trigger and the output of the OR element are the corresponding outputs of the PLL unit, and the phasing unit is designed as a sequence internally connected to the inverter, the trigger and the element And, the second input of which is combined with the input of the inverter, with the other inputs of the trigger, the input of the inverter and the output of the element15267

I

3

That AND are respectively the inputs and output of the phasing unit.

The drawing shows a structural electrical circuit of the device.

The device of in-phase reception of pulse signals contains a phase locked loop (PLL), a phasing unit 2, a first trigger 3, an AND 4 element and a second trigger 5, and the PLL 1 contains the first, second and third triggers 6-8, an inverter 9 and an OR element 10, and the phasing unit 2 comprises a trigger 11, an AND element 12 and an inverter 13.

The device works as follows.

In the initial state, the first trigger 3 is set to the zero state, and the first trigger 6 of the PLL 1 is set to one. Since from the communication line pulse signals (logical units) do not arrive at the clock inputs of the second and third triggers 7 and 8 of the PLL 1, logical zeros are set at their outputs due to the presence of signals from the output of the second trigger 5 at their installation inputs. Trigger 11 is also in a state of logical zero. At the output of the device information is missing. When the first pulse signal from the communication line appears, its leading edge records a unit in the first trigger 3 · Thus, a single switch occurs in each cycle of the first trigger 3 on the leading edge of only the first pulse signal of this message.

This unit enters the clock input of the first trigger 6.

If at the moment when the leading edge of the first pulse signal arrives at the information input of the first. Trigger 6 there was a signal in the form of a logical zero, the first trigger 6 is switched. ⁴⁵ At the same time, the element 4 forms a reset signal, which prevents false recording in the second trigger 7 and trigger 11 of the logical unit by the leading edge of the received first pulse of the ^50th signal. This received information signal is now recorded with the falling edge into the third trigger 8. The recorded pulse signal through the element OR 10 is fed to the information input of the trigger 11. With the arrival of the next trailing edge of the clock pulses to the input of the inverter 13

The mating signal is recorded by the trigger 11. And with the arrival of the next clock pulse, an information signal is formed at the output of the And 12 device, in phase with the clock pulses. At the time of recording by the trigger 11 of the information signal, the third trigger 8 is reset, which is again ready to receive the next 10 pulse signal. If another one has arrived after the first informational impulse, then the third trigger 8 again writes a logical unit and the trigger 11 rewrites 15 again, without transferring it to the zero state. If the first pulse signal was not followed by the next information pulse, then the third trigger 8, and after it through the element OR 10, and the trigger 11 record a logical zero. In the case when the switch of the first trigger 6 did not occur, the second trigger 7 works.

All other blocks function 25 similarly. In this case, the logical unit will be recorded to the second trigger 7 immediately on the leading edge of the received pulse signal. And then the phasing process is repeated _anaergically when the next pulse signals arrive at the device input.

Using the proposed Arrange CTBA in telecontrol systems for alignment yn ₃₅ different television devices over long communication lines with different phase characteristics ensures stable operation of the digital device with high reliability reception.

Claims (3)

Claim 1 o A common-mode pulse receiving device containing the first trigger connected in series, a phase locked loop (PLL) and a phasing unit, with the input of the first trigger and the second input of the PLL being a cyclic input, and the third PLL input and the second input of the phasing unit are a clock input , characterized by the fact that, in order to increase the reliability, the serially connected And element and the second trigger, the output of which is connected to the fourth input of the PLL, are introduced; whose moves are connected to the inputs of the element I, the output of which is connected to the third input of the phasing unit, while the second input of the second trigger is connected to the third input of the 5 ΦΑΠΜ block. 2. The device according to p. ^ Characterized in that the PLL is made in the form of the first trigger, the outputs of which, respectively, through ^{, the} second and third triggers are connected to the inputs of the OR element, while the inverter output is connected to the second input of the second trigger, the first, second and third- <5 th triggers are the corresponding inputs of the PLL unit, and the outputs of the first trigger and the output of the element OR 67 6 are the corresponding outputs (PLL unit., 3. The device according to claim 1, which is based on the fact that the phasing unit is made in the form of successively connected inverter, trigger and element, the second input of which is combined with the input of the inverter, and other inputs of the trigger, input of the inverter and output of the element And respectively, the inputs and output of the phasing unit.