JPH05252147A - Phase controller - Google Patents

Abstract

PURPOSE:To prevent a readout data error from occurring due to the fluctuation of a reception signal by providing sufficient phase difference between a write synchronizing signal and a readout synchronizing signal when reception is started. CONSTITUTION:When the reception is started, a write enable coincidence signal S17 is outputted by detecting coincidence between a real write synchronizing signal S13 and a write enable signal S21 by a write enable coincidence detection circuit 32, and a synchronous coincidence signal S16 is outputted by detecting the coincidence between the real write synchronizing signal S13 and the readout synchronizing signal S20 by a synchronizing signal coincidence detection circuit 31 in the case other than the start of the reception. Also, a coincidence signal switching circuit 13 selects the write enable coincidence detection signal S17 when the reception is started while monitoring a signal state signal, and selects the synchronous coincidence signal S16 n the case other than the start of the reception, and outputs as switching signal S15. A synchronizing signal switching circuit 12 receiving the switching signal S15 outputs the readout synchronizing signal S20 and the write synchronizing signal with sufficient phase difference as the real write synchronizing signal S13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase controller, and more particularly to a phase controller for serially transmitting a plurality of time division multiplexed digital signals.

In recent years, with the increase in the number of communication lines and various data transmission equipment such as facsimiles, the amount of transmitted information is increasing dramatically. In such a situation, as a method of increasing the amount of information transmitted without impairing the quality of the data to be transmitted, measures have been taken such as using an optical cable for the communication line, increasing the communication frequency, and time division multiplexing. There is.

Among these measures, in time division multiplexing,
The following data processing is performed in the transmitter and the receiver. The transmitter converts a plurality of digital signal data into a serial signal by time division multiplexing and transmits the serial signal. Further, the receiving device recognizes each signal included in the received serial signal (hereinafter, referred to as “received signal”) and restores the original plurality of digital signalized data. At the time of this restoration, the communication speed of the received signal and the processing speed of the receiving device generally differ. Therefore, the receiving device needs to convert the phase of the received signal in order to output the received signal at a predetermined timing that is easy to handle.

A device for converting the phase of the received signal is a phase control device, and two conventional phase conversion methods are known. One is a method of converting the phase of a received signal to a predetermined timing by passing it through a delay circuit, and the other is a method of writing the received signal in a memory and reading the written received signal at a predetermined timing. ..

However, in the phase control device for converting the phase through the memory, there may occur a case where the timing of writing the received signal in the memory and the timing of reading the written received signal from the memory coincide with each other. Specifically, the received signal is written in the memory and, at the same time, the written received signal is read out. Therefore,
Since the internal state of the memory is read before it is determined, the read reception signal (hereinafter referred to as "output signal") becomes indeterminate and a read data error occurs.

[0006]

2. Description of the Related Art Conventionally, when the timing of writing a received signal to a memory and the timing of reading an output signal from the memory match, writing of the received signal is delayed until a safe timing.

FIG. 4 is a schematic block diagram of a conventional phase control device. In the figure, the conventional phase control device includes a signal receiving unit 10, a write sync signal generating circuit 11, a sync signal switching circuit 12, a digital memory 21, a write address signal counter 22, a read address signal counter 23, and a sync signal coincidence detection. It is composed of a circuit 31.

The signal receiving unit 10 receives a communication signal S10 transmitted through a transmission medium such as a communication cable, detects a synchronization pattern such as a leading pulse of the communication signal S10, and outputs a reception signal D1 and a frame synchronization signal S11. To do.
The write sync signal generation circuit 11 receives the frame sync signal S11 and outputs two write sync signals S12a and S12b which are shifted from each other by a half cycle. The length of one cycle of the two write synchronization signals S12a and S12b is the same as the length of the frame synchronization signal S11. Sync signal switching circuit 1
2 is a switching signal S14, and two write synchronization signals S1
Either one of 2a and S12b is output as the actual write synchronization signal S13.

The write address signal counter 22 starts counting by the actual write synchronization signal S13 and outputs the write address signal AD1. The write address of the digital memory 21 is sequentially selected by the write address signal AD1, and the received signal D1 is written in the digital memory 21 bit by bit. On the other hand, the read address signal counter 23 starts counting by the read synchronizing signal S20 and outputs the read address signal AD2. The read address of the digital memory 21 is sequentially selected by the read address signal AD2, and the output signal D2 is read from the digital memory 21 bit by bit. Digital memory 21 temporarily stores reception signal D1 in synchronization with write address signal AD1 and outputs output signal D2 in synchronization with read address signal AD2.

Further, the sync signal coincidence detection circuit 31 outputs a switching signal S14 when the actual write sync signal S13 and the read sync signal S20 match. The synchronization signal switching circuit 12 selects, for example, the write synchronization signal S12a when the switching signal S14 is at the low level and selects the write synchronization signal S12b when the switching signal S14 is at the high level for actual writing. It is output as the synchronization signal S13.

With such a configuration, when the timing of writing the received signal D1 to the digital memory 21 and the timing of reading the output signal D2 from the digital memory 21 coincide with each other, the synchronization signal coincidence detection circuit 31 detects the coincidence. To do. That is, the synchronization signal coincidence detection circuit 31
Detects an overlap between the actual write synchronization signal S13 and the read synchronization signal S20 and outputs the switching signal S14. By this switching signal S14, two write synchronization signals S12a and S1 are generated.
Of 2b, a write sync signal having a cycle different from that of the read sync signal S20 is selected and output as a new actual write sync signal S13. Therefore, since the writing address signal counter 22 and the reading address signal counter 23 start counting differently, the output signal D2 can be read correctly without the addresses of the writing address signal AD1 and the reading address signal AD2 overlapping. ..

FIG. 5 is a time chart of signals by the conventional phase control device. The same signals as those in FIG. 4 are given the same signal names. In the figure, the read synchronization signal S20, the read address signal AD2, and the output signal D are sequentially arranged from the top.
2, the received signal D1, the frame synchronization signal S11, the write synchronization signals S12a and S12b, the actual write synchronization signal S13, the switching signal S14, and the write address signal AD1 are shown.

In the figure, at time t11, the pulse of the actual write synchronization signal S13 and the pulse of the read synchronization signal S20 overlap. Therefore, the sync signal coincidence detection circuit 31 detects the coincidence of the signals and switches the switching signal S14, which was initially at the low level, to the high level as indicated by the arrow X11. Due to the change in the switching signal S14, the synchronizing signal switching circuit 12 switches the previously selected writing synchronizing signal S12a to the writing synchronizing signal S12b. Therefore, as shown by the arrow X12, the actual writing synchronizing signal S13 is written. Embedded sync signal S1
2b is output. Further, at time t12, the write address signal counter 22 is driven by the actual write synchronization signal S13.
Are reset, and the address value of the write address signal AD1 is initialized from "6" to "1".

Thus, the actual write sync signal S13 and the read sync signal S20 overlap each other, that is, the timing of writing the received signal D1 into the digital memory 21 and the output signal D.
It is possible to prevent coincidence with the timing of reading 2 from the digital memory 21.

However, the communication signal S10 is easily affected by noise and the like, and accordingly, the received signal D1 also suffers from fluctuations of several bits generally called "timing jitter". Therefore, after a considerable amount of time has passed, the timing of writing the reception signal D1 in the digital memory 21 and the timing of reading the output signal D2 from the digital memory 21 may coincide.

FIG. 6 is a time chart when fluctuation occurs in the received signal. Note that the same signals as those in FIG. 5 are given the same signal names, and description thereof will be omitted. In the figure,
The pulse of the read synchronization signal S20 rises at time t21 and falls at time t22. Also, the actual write synchronization signal S
The pulse of 13 rises at time t22 and falls at time t23. Therefore, the synchronization signal coincidence detection circuit 31
No overlap between the pulse of the read sync signal S20 and the pulse of the actual write sync signal S13 is detected.

However, when the communication signal S10 fluctuates over time, the received signal D1 and the actual write synchronization signal S13 also fluctuate. Finally, at the time t24, the read synchronization signal S
The pulse of 20 and the pulse of the actual write synchronization signal S13 may overlap. At time t25, the write address signal counter 22 is reset by the actual write synchronization signal S13, and the address value of the write address signal AD1 is initialized from "6" to "1". In the vicinity of this time t24,
At the same time that the reception signal D1 is written in the digital memory 21, the output signal D2 is read from the digital memory 21.

[0018]

Therefore, since it cannot be determined whether or not there is a margin in the timing interval between the read synchronization signal S20 and the actual write synchronization signal S13, a read data error occurs near the time t24. There was a problem.

Further, the read synchronization signal S20 at time t24
The pulse of the actual write synchronization signal S13 is overlapped with the pulse of the actual write synchronization signal S13, and the synchronization signal coincidence detection circuit 31 changes the signal level of the switching signal S14 to generate the pulse of the actual write synchronization signal S13 at time t25. Therefore, the time t2
The received signal D1 written in the digital memory 21 from 4 to time t25 is overwritten from time t25 because the address value of the write address signal AD1 is initialized, resulting in a problem that data loss occurs. there were.

The present invention has been made in view of the above circumstances, and provides a sufficient phase difference between the write sync signal and the read sync signal at the start of reception to prevent occurrence of read data error due to fluctuation of the received signal. It is an object of the present invention to provide a phase control device for preventing.

[0021]

FIG. 1 is a principle diagram of a phase control apparatus of the present invention which achieves the above object. In the figure,
The phase controller comprises a sync signal switching circuit 12, a coincidence signal switching circuit 13, a memory 20, a sync signal coincidence detection circuit 31, a write enable signal coincidence detection circuit 32, and a write enable signal generation circuit 33.

The storage means 20 temporarily stores the received signal D1. The synchronization signal switching circuit 12 uses the switching signal S15 to generate two write synchronization signals S which are shifted from each other by a half cycle.
Either one of 12a and S12b is output as the actual write synchronization signal S13. Sync signal coincidence detection circuit 31
Detects a match between the actual write sync signal S13 and the read sync signal S20 and outputs a sync match signal S16. The write enable signal generation circuit 33 outputs a write enable signal S21 having a predetermined cycle difference from the read synchronization signal S20. The write permission coincidence detection circuit 32 detects the coincidence between the actual write synchronization signal S13 and the write permission signal S21, and the write permission coincidence signal S17.
Is output. The coincidence signal switching circuit 13 receives the reception state signal S1.
8, the write enable coincidence detection signal S17 is selected at the start of reception, and the synchronization coincidence signal S is selected at a time other than the start of reception.
16 is selected and the switching signal S15 is output.

[0023]

When the reception is started, the write permission coincidence detection circuit 32 detects the coincidence between the actual write synchronization signal S13 and the write permission signal S21 and outputs the write permission coincidence signal S17.

When the reception is not started, the sync signal coincidence detection circuit 31 detects the coincidence between the actual write sync signal S13 and the read sync signal S20 and outputs the sync coincidence signal S16. The coincidence signal switching circuit 13 monitors the signal state signal S18, selects the write enable coincidence detection signal S17 at the start of reception, selects the synchronization coincidence signal S16 at the time other than the start of reception, and outputs the switching signal S15. .. By this switching signal S15, the synchronizing signal switching circuit 12 causes the writing synchronizing signal S12a,
One of S12b is the actual write synchronization signal S13.
Output as.

At the start of reception, by outputting one of the write synchronization signals S12a and S12b having a predetermined deviation from the read synchronization signal S20 as the actual write synchronization signal S13, the read synchronization signal S20 and the actual write signal are output. A sufficient phase difference is provided with the synchronization signal S13.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of the phase control device of the present invention. In the figure, the phase control device is shown in FIG.
0, write sync signal generation circuit 11, sync signal switching circuit 1
2, a coincidence signal switching circuit 13, a storage unit 20, a synchronization signal coincidence detection circuit 31, a write permission signal coincidence detection circuit 32, and a write permission signal generation circuit 33. The storage means 20 comprises a digital memory 21, a write address signal counter 22 and a read address signal counter 23.

The signal receiving unit 10 receives a communication signal S10 transmitted through a transmission medium such as a communication cable, detects a synchronization pattern such as a leading pulse of the communication signal S10, and outputs a reception signal D1 and a frame synchronization signal S11. To do.
The write sync signal generation circuit 11 receives the frame sync signal S11 and outputs two write sync signals S12a and S12b which are shifted from each other by a half cycle. The length of one cycle of the two write synchronization signals S12a and S12b is the same as the length of the frame synchronization signal S11.

The synchronizing signal switching circuit 12 outputs one of the two writing synchronizing signals S12a and S12b as the actual writing synchronizing signal S13 according to the switching signal S15. The match signal switching circuit 13 monitors the signal status signal S18, and at the start of reception, the write enable match detection signal S17.
Is selected and the synchronization coincidence signal S16 is selected except when the reception is started, and is output as the switching signal S15.

The sync signal coincidence detection circuit 31 outputs the sync coincidence signal S16 when the actual write sync signal S13 and the read sync signal S20 coincide with each other. Write enable signal match detection circuit 32
Detects a match between the actual write synchronization signal S13 and the write enable signal S21 and outputs a write enable match signal S17. The write enable signal generation circuit 33 has a 1 / th of the read synchronization signal S20.
The write enable signal S21 having a deviation of 4 cycles is output. The write enable signal S21 may be read synchronous signal S20 and actual write synchronous signal S1 when the signal level is high, for example.
3 indicates that there is a margin in the timing interval with respect to 3 and the signal level is in the low level, it means that there is no margin in the timing interval between the read synchronization signal S20 and the actual write synchronization signal S13. It is a signal shown.

In the storage means 20, the write address signal counter 22 starts counting by the actual write synchronization signal S13 and outputs the write address signal AD1 which is an address for writing the received signal D1 in the digital memory 21. The write address of the digital memory 21 is sequentially selected by the write address signal AD1, and the received signal D1 is written in the digital memory 21 bit by bit. On the other hand, the read address signal counter 23 starts counting by the read synchronizing signal S20 and outputs the output signal D2.
The read address signal AD2, which is an address for reading the data into the digital memory 21, is output. The read address of the digital memory 21 is sequentially selected by the read address signal AD2, and the output signal D2 is read from the digital memory 21 bit by bit. The digital memory 21 is a buffer memory including a 12-bit parallel memory, temporarily stores the reception signal D1 in synchronization with the write address signal AD1, and reads the read address signal AD1.
The output signal D2 is output in synchronization with 2.

The signal receiving unit 10 outputs a high-level reception state signal S18 at the start of reception, and the reception signal D
1 becomes abnormal, or when the transmission device having the phase control device stops, the low-level reception state signal S1
8 is output. Further, the coincidence signal switching circuit 13 selects and outputs the coincidence detection signal S17 when the signal level is low level, and selects and outputs the synchronization coincidence signal S16 when the signal level is high level. Further, the synchronization signal switching circuit 12 selects the write synchronization signal S12a when the switching signal S15 is at the low level, and selects the write synchronization signal S12b when the switching signal S15 is at the high level, for actual writing. It is output as the synchronization signal S13.

Next, the operation of the phase control device of the present invention will be described. At the start of reception, that is, at the start of use of the transmission device having the phase controller, the sync signal switching circuit 12 outputs the write sync signal S12a as the actual write sync signal S13. Further, the coincidence signal switching circuit 13 receives the reception state signal S
While monitoring 18, the write permission coincidence detection signal S17 is output as the switching signal S15. Then, the write permission coincidence detection circuit 32 checks whether or not the actual write synchronization signal S13 output from the synchronization signal switching circuit 12 is in the safe area. Specifically, when the actual write synchronization signal S13 is output, it is checked whether or not the signal level of the write enable signal S21 is in the high level state.

If the signal level of the write enable signal S21 is not in the high level when the actual write synchronization signal S13 is output, the write enable match detection circuit 32 detects the low level write enable match. The signal S17 is output. The coincidence signal switching circuit 13 outputs the write permission coincidence detection signal S17 as a switching signal S15. Low level switching signal S
The synchronization signal switching circuit 12 which has received the write signal 15 receives the write synchronization signal S.
12b is output as the actual write synchronization signal S13.

Next, when the actual write synchronization signal S13 is output, if the signal level of the write enable signal S21 is in the high level state, the write enable coincidence detection circuit 32 outputs the high level write enable coincidence. The detection signal S17 is output. The match signal switching circuit 13 receives the write enable match detection signal S17 that changes from the low level to the high level, and then the sync match signal S16.
Is output as a switching signal S15.

Thus, the actual write sync signal S13 output from the sync signal switching circuit 12 is always output in the safe area. Therefore, even when the received signal D1 fluctuates, it is possible to reliably prevent the occurrence of a read data error due to the fluctuation of the received signal D1 within the range of the 1/4 cycle before and after the read synchronizing signal S20.

FIG. 3 is a time chart of signals by the phase control device of the present invention. The same signals as those in FIG. 2 are given the same signal names. In the figure, the reception status signal S18, the read synchronization signal S20, the read address signal AD2, the output signal D2, the received signal D1, the frame synchronization signal S11, the write synchronization signals S12a and S12b, the write enable signal S21, and the switching are shown in this order from the top. Signal S15, actual write synchronization signal S1
3, write address signal AD1 and coincidence signal switching circuit 13
Signals such as a selection signal of the synchronization coincidence signal S16 or the write permission coincidence detection signal S17 and the data content are shown.

Next, the operation of the phase control device of the present invention will be described based on a time chart. First, at time t1,
The signal receiving unit 10 outputs a high level reception state signal S18 indicating the start of reception. Then, the synchronization signal switching circuit 12
Outputs the write synchronization signal S12a as the actual write synchronization signal S13.

Here, the pulse of the read sync signal S20 rises at time t2 and falls at time t3. Further, the pulse of the actual write synchronization signal S13 rises at time t3.
Therefore, the sync signal coincidence detection circuit 31 does not detect the overlap between the pulse of the read sync signal S20 and the pulse of the actual write sync signal S13.

However, at the time t3, when the pulse of the actual write synchronization signal S13 rises, the write enable signal S21.
The signal level of is a low level. Therefore, the write permission match detection circuit 32 determines that there is no margin in the timing interval between the actual write synchronization signal S13 and the read synchronization signal S20, and the write permission match detection signal S17 that was initially at the high level.
The signal level of is switched to the low level and output. The match signal switching circuit 13, which has received the write enable match detection signal S17, outputs it as a switch signal S15 as shown by an arrow X1.

In response to the change of the switching signal S15, the synchronizing signal switching circuit 12 receives the time t4 as shown by the arrow X2.
Then, the write synchronization signal S12b is output as the actual write synchronization signal S13. At this time, the write address signal counter 22 is reset by the actual write synchronization signal S13, and the address value of the write address signal AD1 is initialized from "6" to "1".

Then, when the next pulse of the actual write synchronization signal S13 rises, the signal level of the write enable signal S21 is at a high level. Therefore, the write permission coincidence detection circuit 32 determines that the actual write synchronization signal S13 has a margin in the timing interval with the read synchronization signal S20, and sets the signal level of the write permission coincidence detection signal S17 that was low level to high. Switch to level and output. The match signal switching circuit 13, which receives the write enable match detection signal S17, switches the sync match signal S16 to the switch signal S, as shown by an arrow X3.
Output as 15. At this time, the synchronization coincidence signal S16 output as the switching signal S15 is at a low level. Therefore, the synchronization signal switching circuit 12 causes the read synchronization signal S2
The write synchronization signal S12b having a sufficient phase difference from 0 is output as it is as the actual write synchronization signal S13.

Thereafter, the signal level of the selection signal in the coincidence signal switching circuit 13 is maintained until the reception state signal S18 becomes low level, that is, the reception signal D1 becomes abnormal, or the transmission device having the phase control device operates. It is maintained until stopped.

Thus, at the start of reception, the actual write synchronization signal S
13 and the read synchronization signal S20 have a sufficient phase difference, the write timing of the received signal D1 and the output signal D2
It is possible to prevent coincidence with the read timing of. That is, since the writing address signal counter 22 and the reading address signal counter 23 start counting differently, the writing address signal AD1 and the reading address signal AD2
The output signal D2 can be read correctly without the addresses of and overlapping.

The received signal D1 is transferred to the digital memory 2
Since there is a margin between the timing of writing to 1 and the timing of reading the output signal D2 from the digital memory 21, it is possible to reliably prevent data loss even when fluctuation occurs in the received signal D1.

In the above explanation, the digital memory 21 which inputs and outputs signals according to the write address signal AD1 and the read address signal AD2 is applied to the storage means 20, but according to the actual write sync signal S13 and the read sync signal S20. Other memories capable of inputting / outputting signals may be applied.

Although a buffer memory composed of a 12-bit parallel memory is applied to the digital memory 21, another memory such as a 256-bit matrix memory may be applied.

[0047]

As described above, in the present invention, the coincidence signal switching circuit selects the write enable coincidence signal at the start of reception, selects the synchronization coincidence signal at times other than the start of reception, and outputs the switching signal. Of the two write sync signals, the sync signal switching circuit is configured to output the write sync signal with a margin between the actual write sync signal and the read sync signal as the actual write sync signal. A sufficient phase difference can be provided between the actual write sync signal and the read sync signal from the start, and the occurrence of read data error due to fluctuations in the received signal can be prevented.

Further, since there is a margin between the timing of writing the received signal to the memory and the timing of reading the output signal from the memory, it is possible to reliably prevent the loss of data even when fluctuations occur in the communication signal and the received signal. ..

[Brief description of drawings]

FIG. 1 is a principle diagram of a phase control device of the present invention.

FIG. 2 is a diagram showing an embodiment of a phase control device of the present invention.

FIG. 3 is a time chart of signals by the phase control device of the present invention.

FIG. 4 is a schematic block diagram of a conventional phase control device.

FIG. 5 is a time chart of signals by a conventional phase control device.

FIG. 6 is a time chart when fluctuation occurs in a received signal.

[Explanation of symbols]

 12 sync signal switching circuit 13 coincidence signal switching circuit 20 storage means 31 sync signal coincidence detection circuit 32 write enable signal coincidence detection circuit 33 write enable signal generation circuit

Claims (3)

[Claims] 1. A phase control device for writing a received signal to a storage means according to a write synchronization signal and reading an output signal from the storage means according to a read synchronization signal, wherein a shift signal (S15) causes a shift of a half cycle from each other. Of the two write sync signals (S12a, S12b),
A synchronization signal switching circuit (12) for outputting one of them as an actual write synchronization signal (S13), the actual write synchronization signal (S13) and the read synchronization signal (S2).
0) and a sync signal coincidence detection circuit (31) for outputting a sync coincidence signal (S16), and a write enable signal (S21) having a predetermined cycle difference from the read sync signal (S20). A write enable signal generating circuit (33) for outputting the actual write synchronization signal (S13) and the write enable signal (S).
21) is detected, and a write enable match signal (S17)
And the write enable match detection signal (S17) at the start of reception, and the sync match signal (S1) at a time other than the start of reception.
6) and the coincidence signal switching circuit (13) for outputting the switching signal (S15) and the reception signal (D) in synchronization with the actual write synchronization signal (S13).
A phase control device comprising: a storage unit (20) for writing 1) and reading an output signal (D2) in synchronization with the read synchronization signal (S20). 2. The storage means (20) includes a write address signal counter (22) for outputting a write address signal (AD1) according to the actual write synchronization signal (S13), and the read synchronization signal (S20). ), The read address signal counter (2) that outputs the read address signal (AD2)
3), the reception signal (D1) is written in synchronization with the write address signal (AD1), and the read address signal (AD2) is written.
2. The phase control device according to claim 1, further comprising a digital memory (21) for reading the output signal (D2) in synchronization with. 3. The write enable signal generating circuit (33) comprises:
The write enable signal (S21) is replaced with the read synchronization signal (S2).
2. The phase control device according to claim 1, wherein the phase control device is configured so as to be shifted by 1/4 cycle and output.