JP2531456B2 - Sync protector - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization protection device, and more particularly to receiving a digital signal such as a voice or image formed of a data stream group in which a synchronization signal is added to each data stream via a transmission system or a recording / reproducing system. The present invention relates to a synchronization protection device that performs time axis correction and outputs a data string of a predetermined length.

[0002]

2. Description of the Related Art Generally, when transmitting or recording / reproducing a digital signal such as voice or image, the digital signal is divided, and a sync signal, an address signal,
An error correction code or the like is added to form a data string of a specified length, and a plurality of data strings are made continuous to form one data string group (frame).

By the way, in a data string input through a transmission system or a reproduction system, a sync signal is missing or jitter occurs due to a burst error or the like. For this reason, the intervals of the synchronization signals added to each data string may fluctuate irregularly, and error correction processing and signal processing of the data string may not be executed correctly. Therefore, by providing a synchronization protection device to correct the time axis, the jitter of each data string input through the transmission system and the reproduction system is absorbed and the length of each data string does not fluctuate irregularly. .

FIG. 5 is a block diagram showing an example of a conventional synchronization protection device.

Here, the sync detection circuit 21 detects a sync signal from the data string of the input data D1 and outputs a sync detection signal S1 when the sync signal matches the specified sync pattern. The synchronization protection circuit 22 outputs a protection synchronization signal S2 according to the synchronization detection signal S1. In this case, when the sync detection circuit 21 cannot detect the sync signal from the data string, the protection sync signal S2 is artificially output at the timing of counting the data string length from the previous sync detection signal.

The data FIFO memory 23 and the synchronization FIFO memory 24 are controlled by the write control circuit 25 and the read control circuit 26, respectively, and store and read the input data D1 and the synchronization signal S2, respectively.

The write control circuit 25 receives the protection synchronization signal S2 and the period signal Sd supplied from the outside, and receives the write reset signal W at the start point of the first data string of the data string group.
Output R. The period signal Sd is a signal sent to the gap between the data string groups, and the starting point and the effective period of the data string group can be known from this signal.

The read control circuit 26 reads the protection synchronization signal written in the synchronization FIFO memory 24 as a signal S3 in response to a data request signal S6 from an error correction device or a signal processing device (not shown) and outputs this signal S3. Based on this, an abnormality in the head of the data string and the length of the data string is detected, and the read reset signal RR and the read enable signal RE are output.

Here, the data FIFO memory 23 and the synchronization FIFO memory 24 have the write reset signal W.
When R is received, the write address counter is reset, and then the count is incremented every clock to generate a write address and writing is performed. When the read reset signal RR is received, the read address counter is reset, and then the count is incremented every clock to generate the read address to perform the read operation, and the read operation is interrupted according to the read enable signal RE. By controlling the data FIFO memory 7 by such a write / read control signal, the output data D23 in which the input data D1 is time-axis corrected is generated and sent to an error correction device or a signal processing device (not shown). .

Next, the operation will be described with reference to the timing chart shown in FIG.

(A) shows one data string group of the input data D1. This data string group is composed of data strings d1 to dm, and a sync signal is added to the head of each data string. Here, the data strings d1, d3, d5
..., dm is a normal data string having a specified data string length,
The data string d2 is shorter than the specified data string length, and the data string d4 is longer than the specified data string length. Also,
The specified data string length is n symbols, and the data string d2 is y (y <
The n) symbol and the data string d4 are z (z> n) symbols.

(B) shows a sync detection signal S1 generated from the input data D1 by the sync detection circuit 21, and (c) shows a protection sync signal generated from the sync detection signal S1 by the sync protection circuit 22. S2 is shown. The write control circuit 25 sends a write reset signal WR to the data FIFO memory 23 and the synchronization FIFO memory 24 at the start of the data string group, and the input data D1 and the protection synchronization shown in (a) and (c) of FIG. Signal S2
Are sequentially stored. (D) is a data FIF
The data string group stored in the O memory 7 is shown.

The read control circuit 26 monitors the protection synchronization signal S3 read from the synchronization FIFO memory 24, and (e)
The read enable signal RE is generated as shown in (1), and the time is adjusted so that the data string length becomes the specified interval. For example, for a data string d2 of y (y <n) symbols,
Read enable signal R only for the time of (ny) symbols
By setting E to the “L” level and interrupting the reading, the data string d2 is corrected to have n symbols, and for the data string d4 of z (z> n) symbols,
The read enable signal RE is set to the “L” level for a time corresponding to the (n−z) symbol to interrupt the reading, thereby correcting the data string d4 to have 2n symbols. By controlling the data FIFO memory 23 in this way to read the data strings, each data string is corrected to a specified length (n symbols) or an integral multiple of the specified length (2n symbols) as shown in (f). Output data D2
3 is obtained.

[0014]

In the above-mentioned conventional synchronization protection device, the protection synchronization signal stored in the synchronization FIFO memory is read, and when the data string length is not normal, the reading from the data FIFO memory is interrupted. I am adjusting the time. Therefore, the corrected data string group becomes longer than the specified data string group length, which causes a shortage of processing time in the subsequent error correction processing and signal processing. Therefore, it is necessary to take measures such as increasing the data processing speed. Further, in the case of correcting the data string length of input data that has passed through a plurality of transmission paths (channels) and integrating the channels, the data string group output by the synchronization protection device provided for each channel. The length is different,
There is a problem that a circuit for unifying these is required and the circuit scale becomes large.

An object of the present invention is to correct each data string to a fixed length so that the data string group can fit within a specified length, and to correct the data string length for the input data that has passed through a plurality of transmission lines. An object of the present invention is to provide a synchronization protection device that can simplify the circuit scale when integrated.

[0016]

The synchronization protection apparatus of the present invention receives a digital signal composed of a data sequence group in which a synchronization signal is added to each data sequence via a transmission system or a recording / reproducing system and corrects the time axis. And a synchronization detection circuit for detecting the synchronization signal from each data sequence of the received data sequence group and outputting a synchronization detection signal. A data string length measuring circuit that measures the data length of each data string based on a signal and outputs a data string length signal, and a signal that indicates the valid period of the data string group supplied from the outside and the synchronization detection signal. Status code generating means for generating a status code indicating whether each data string is valid or invalid, and a status code for replacing the synchronization signal of each data string with the status code. A conversion circuit, a FIFO memory that stores and reads the data string output by the status code replacement circuit, and the status code contained in each data string read from the FIFO memory is detected to stop the sending of an invalid data string. A status code monitoring circuit, a write control circuit that controls the FIFO memory based on the data string length signal to write each data string so that the data string has a specified length, and a write control circuit that responds to a data request signal from the outside. And a read control circuit for continuously reading a data string written in the FIFO memory, wherein the write control circuit, when the data string is shorter than the specified length, digs into the area of the next data string and sets the specified length. Is written and then the remaining data is discarded. Further, in the case of a data string longer than the specified length, the control is performed so that the specified length is written and the remaining data is discarded.

Further, the synchronization protection apparatus of the present invention receives a digital signal consisting of a data sequence group in which a synchronization signal is added to each data sequence, receives it through a transmission system or a recording / reproduction system, corrects the time axis, and defines it. A synchronization protection device that outputs as a long data string, wherein a synchronization detection circuit that detects the synchronization signal from each data string of the received data string group and outputs a synchronization detection signal, and the synchronization detection circuit based on the synchronization detection signal A data string length measuring circuit for measuring a data length of each data string and outputting a data string length signal, the synchronization detection signal and a signal indicating the effective period of the data string group supplied from the outside and the data string length signal And a status code generation circuit for indicating whether each data string is valid or invalid and for generating a status code including data string length information, and synchronization of each data string. A status code replacement circuit for replacing a code with the corresponding status code, a delay circuit provided on the input side of the status code replacement circuit for delaying the data string length, and a data string output by the status code replacement circuit. A FIFO memory for storing and reading, and a status code monitoring circuit for detecting the status code contained in each data string read from the FIFO memory, stopping sending of an invalid data string, and sending the data string length information. A write control circuit for performing write control of the FIFO memory based on the data string length signal to write each data string into the FIFO memory, and the FIFO according to a data request signal from the outside and the data string length information. And a read control circuit for performing read control of the memory to read the written data string, wherein the write control circuit has a specified length. And a data string shorter than the specified length are written as they are, and in the case of a data string longer than the specified length, control is performed such that the specified length is written and the remaining data is discarded. In the case of a data string shorter than the specified length, reading is interrupted based on the data string length information and control is performed so that the specified length is achieved.

[0018]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. Here, the synchronization detection circuit 1 uses the input data D
A sync signal is detected from each data string of No. 1 and the sync detection signal S1 is output when the sync signal matches the specified sync pattern. Upon receiving the synchronization detection signal S1, the data string length measuring circuit 2 counts the length (the number of symbols) of each data string and outputs a data string length signal S4 indicating the data string length.

The status code generation circuit 3 uses the synchronization detection signal S
1 and a period signal Sd indicating the valid period of the data string group, respectively, and a status code S5 indicating whether each data string is valid or invalid is generated. Status code replacement circuit 4
Replaces the synchronization signal of each data string with the status code S5. The FIFO memory 5 is controlled by the write control circuit 6 and the read control circuit 7 to store and read the data string output by the state code replacing circuit 4. The status code monitoring circuit 8 detects the status code contained in each data string and stops the sending of the invalid data string.

The write control circuit 6 sends a write reset signal WR and a write enable signal WE to the FIFO memory 5 based on the data string length signal S4 so that the length of each data string becomes a specified length. I do. That is, as shown in FIG. 2A, the data string d11 having the specified length (n symbols) is written as it is, but the data string d12 shorter than the specified length (y symbols) is the next data string d13.
(N-y) symbols are digged into the area for writing a prescribed number of n symbols, and writing of the remaining data (y symbols) is stopped and discarded. Therefore, the data string d having a short data string length
The data string d13 next to 12 is destroyed. FIG.
As shown in (b), in the data string d22 having a length (n + z symbols) longer than the specified length, after writing a specified number of symbols, writing of the remaining data (z symbols) is stopped and discarded.

As described above, although the data string is destroyed by forcibly performing the writing process so that the specified data string length is obtained, it is necessary to subject the data string group to processes such as shuffling and error correction code. As a result, the data string can be restored, and the influence on the signal quality can be reduced.

The read control circuit 7 sends a read reset signal RR in response to a data request signal S6 from an error correction device or a signal processing device (not shown). Here, the FIFO memory 5 receiving the read reset signal RR resets the read address counter and then counts up every clock to generate a read address and continuously read the data string. Then, the read reset signal RR for the next data string group is transmitted in response to the next data request signal S6.

As described above, by writing data in the FIFO memory 5 so that the length of the data string becomes the specified length and then reading the data string, the synchronization FIFO memory is not used and the circuit configuration is not complicated. A data string unified to the specified length can be output within the specified data string group length. Therefore, even when the input data that has passed through a plurality of transmission lines (channels) are corrected for the data string length and the channels are integrated, the output of the synchronization protection device provided for each channel is simply selected. Therefore, the circuit scale can be simplified.

FIG. 3 is a block diagram showing a second embodiment of the present invention, and the same components as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals.

By the way, in the first embodiment, when the data string length is shorter than the specified length, writing is performed by cutting into the next data string. Therefore, when the next data string is normal, it has the drawback of making this an error data string. The second embodiment has improved such drawbacks.

Here, the status code generation circuit 9 generates a status code S7 including data string length information in addition to information indicating whether the data string is valid or invalid. The data string length information is generated based on the data string length signal S4. Then, the status code replacement circuit 4 replaces the synchronization signal of each data string with the status code S7. For this reason, the delay circuit 10 is provided, and the data string is delayed by the period until the synchronization detection signal S1 of the next data string is output.
Is being supplied to. The data string length measuring circuit 2 measures the next data string length within this delay period. Further, the status code monitoring circuit 13 detects the status code of each data string and stops the sending of the invalid data string, and at the same time, the data string length information S
It has a function of extracting 8 and sending it to the read control circuit 12.

The write control circuit 11 uses the data string length signal S4.
Then, the write reset signal WR and the write enable signal WE are sent to the FIFO memory 5 to control the writing. In this case, as shown in FIG. 4, the data strings d31, d33, d35 having the specified length (n symbols) and the data string d32 shorter than the specified length (y symbols) are written as they are as in the conventional example, and the data lengths larger than the specified length are written. For the longest (n + z symbol) data string d34, after writing n symbols of a prescribed length as in the first embodiment, writing of the remaining data (n symbols) is stopped and discarded.

The read control circuit 12 uses the data request signal S6.
In response to this, the read reset signal RR is sent to the FIFO memory 5 and the reading of the data string is started. After that, according to the data string length information S8 sent from the status code monitoring circuit 13, as shown in FIG.
Is output. That is, the data string d3 shorter than the specified length
For 2, the read enable signal RE is set to the “L” level for the time of (n−y) symbols, the reading is interrupted, and the number of symbols is corrected to n symbols. By doing so, unlike the first embodiment, when the data string length is shorter than the specified length, the next normal data string will not be an error data string.

[0030]

As described above, according to the present invention, the data length of each data string is measured, and a status code indicating the validity / invalidity of the data string is generated to replace the synchronization signal of the data string for measurement. By writing to and reading from the FIFO memory so that the specified length is compulsorily based on the data length,
A data string having a specified length can be output within the specified data string group length without using a synchronization FIFO memory and without complicating the circuit configuration. Therefore,
The circuit scale can be simplified in the case of channel integration of data that has passed through a plurality of transmission lines (channels).

Further, when a status code including data string length information is generated to replace the sync signal of the data string and the data string is written to the FIFO memory, in the case of the specified length and the data string shorter than the specified length, If the data string is written as it is, and the data string is longer than the specified length, the specified length is written, and then the remaining data is stopped to be written and discarded.
When reading a data string from the O memory, if the data string is shorter than the specified length, the reading is interrupted based on the data string length information and the time is controlled so that the length becomes the specified length. When the length is shorter than that, it is possible to prevent the next normal data string from becoming an error data string.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of write control circuit 6 shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining operations of write control circuit 11 and read control circuit 12 shown in FIG.

FIG. 5 is a block diagram showing an example of a conventional synchronization protection device.

FIG. 6 is a timing chart for explaining the operation of the conventional synchronization protection device shown in FIG.

[Explanation of symbols]

 1 synchronization detection circuit 2 data string length measurement circuit 3, 9 status code generation circuit 4 status code replacement circuit 5 FIFO memory 6, 11 write control circuit 7, 12 read control circuit 8, 13 status code monitoring circuit 10 delay circuit D1 input Data D21, D22 Output data Sd Period signal S1 Synchronization detection signal S4 Data string length signal S5, S7 Status code S6 Data request signal S8 Data string length information RE Read enable signal RR Read reset signal WE write enable signal WR Write reset signal

Claims (2)

(57) [Claims] 1. A synchronization for receiving a digital signal composed of a data string group in which a synchronizing signal is added to each data string via a transmission system or a recording / reproducing system, correcting the time axis, and outputting as a data string of a specified length. A protection device, which detects a synchronization signal from each data string of the received data string group and outputs a synchronization detection signal, and measures the data length of each data string based on the synchronization detection signal. And a data string length measuring circuit for outputting a data string length signal, and receiving the synchronization detection signal and a signal indicating the valid period of the data string group supplied from the outside to determine whether each data string is valid or invalid. A status code generating means for generating a status code indicating whether there is a status code, a status code replacement circuit for replacing the synchronization signal of each data string with the status code, and a status code replacement circuit are provided. A FIFO memory for storing and reading the data string to be stored, a status code monitoring circuit for detecting the status code contained in each data string read from the FIFO memory and stopping the sending of the invalid data string, and the data string length. A write control circuit that controls the FIFO memory based on a signal to write each data string so as to have a specified length, and a data string written to the FIFO memory in response to a data request signal from the outside. And a read control circuit for reading, the write control circuit, in the case of a data string shorter than a specified length, digs into the area of the next data string and writes the specified length, and then discards the remaining data, Further, in the case of a data string longer than a specified length, the synchronization protection device is characterized in that after the specified length is written, the remaining data is controlled to be discarded. 2. A synchronization for receiving a digital signal consisting of a data string group in which a synchronizing signal is added to each data string via a transmission system or a recording / reproducing system, correcting the time axis, and outputting as a data string of a specified length. A protection device, which detects a synchronization signal from each data string of the received data string group and outputs a synchronization detection signal, and measures the data length of each data string based on the synchronization detection signal. A data string length measuring circuit for outputting a data string length signal, and a signal indicating the valid period of the data string group supplied from the outside and the synchronization detection signal and the data string length signal to receive each data string. A status code generation circuit that generates a status code including data string length information and indicates whether the status code is valid or invalid, and the status code corresponding to a synchronization signal of each data string. A status code replacement circuit for replacement, a delay circuit provided on the input side of the status code replacement circuit for delaying the data string length, and a FIFO memory for storing and reading the data string output by the status code replacement circuit, A status code monitoring circuit that detects the status code contained in each data string read from the FIFO memory, stops sending of an invalid data string, and sends the data string length information, and a status code monitoring circuit based on the data string length signal. The FIF
O data write control is performed to write each data string to the FIFO.
A write control circuit for writing in the O memory, and the FIFO in response to an external data request signal and the data string length information.
And a read control circuit for performing read control of the memory to read the written data string, wherein the write control circuit writes the specified length and a data string shorter than the specified length as it is, and also specifies the specified length. In the case of a data string longer than this, control is performed so that the remaining data is discarded after writing the specified length, and the read control circuit further comprises:
In the case of a data string shorter than a specified length, the synchronization protection device is characterized in that reading is interrupted on the basis of the data string length information so that the length becomes a specified length.