JPH0642661B2 - Communication device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a communication device in a communication method in which an error in transmitted data is corrected on a receiving device side, and for example, a high-speed channel transmitting / receiving unit of an ultra-high-speed facsimile. It is suitable for

[Prior Art] Recently, research on a broadband communication line using a satellite or an optical cable has been advanced, but in the case of performing redundancy suppression encoding, error correction is required to maintain high image quality. As a control method for error correction, there is a method of retransmitting an error frame.
Since there is a delay of 0.6 seconds, the time for resending an error frame cannot be ignored with respect to the screen transmission time, and there is a drawback in that transmission efficiency deteriorates.

Next, FIG. 1 shows a block diagram of an example of the data transmitting / receiving apparatus. This device is intended to send and receive data using a telephone line.

First, the outline of processing of data to be transmitted will be described. The digital data TDATA2 to be transmitted is sent to the transmission syndrome register TSR, and an error correction code of a predetermined bit is added in response to the gate signal G1. The data is sent to either the first memory M1 or the second memory M2 via the multiplexer PMX4, and is stored for conversion from the standard array to the interleaved array (vertical / horizontal conversion). Then, the data of the interleaved array read out in a predetermined order via the multiplexer MPX5 is sent to the sync code adding circuit SYN, and the sync code is added to the head. Here, writing to the first memory M1 and the second memory M2,
Alternatively, the reading from these memories is carried out under the addressing of the first and second address counters AC1 and AC2, which operate independently of each other.

On the other hand, the data transmitted through the line is introduced into the synchronous code detection circuit DET as the received data RDATA1 after undergoing a predetermined process. Then, in response to the detection of the synchronization code, the timing signal generation circuit GEN is energized to perform the address control of various memories and the timing control necessary for the error correction operation. Then, contrary to the case of transmission, in order to restore the interleaved array to the standard array, storage in the memories M1 and M2 and reading from these memories are performed.

The data returned to the standard array is introduced into the third memory M3 and the error position detection circuit EDET. Based on the syndrome (group) obtained as a result, the corresponding bit is inverted by the exclusive OR circuit EXOR, and the corrected data
RDATA2 is obtained.

The address of the above-mentioned third memory is designated by the third address counter AC3. Further, a control signal for clearing the syndrome register (not shown) or for latching the resulting syndrome is given from the timing signal generating circuit GEN.

As described above, in the device according to the related art, it is necessary to hold the two interleaving address counters, the address counter of the error correction memory, the timing signal generating circuit, and the like as independent hardware. As a result, there was a drawback in that the scale of the entire device had to be increased.

Further, if the control timing is changed or the specifications are changed, each of these circuits must be redesigned, and the inflexibility of the circuit itself has been a problem.

[Object] In view of the above points, an object of the present invention is to provide a communication method in which transmission data is converted into an interleaved array for transmission on the transmitting side, and data in the interleaved array is received on the receiving side and converted into a standard array, It is an object of the present invention to provide a communication device that simplifies the circuit configuration for the above conversion of the communication device to reduce the scale of the device and can easily cope with a change in communication data format.

In order to achieve such an object, the communication device of the present invention counts the number of bits of the data sequentially input by the input unit that sequentially inputs the data of the first array with a predetermined bit as one unit. Counting means, first and second storage means for storing data input by the input means, and one of the first and second storage means with each count value by the counting means as an address. Third storage means storing control information for designating the input data as the write destination and the other as the data read source,
Fourth storage means storing a write address for writing the input data in the first or second storage means, using each count value by the count means as an address, and each count value by the count means As an address
Fifth storage means for storing a read address for reading data from the first or second storage means,
In response to the output of the count value from the counting means, the third
The storage means specified as the writing destination by the control information stored in the address of the count value in the storage means
Writing control means for controlling the writing of the input data to the write address stored in the address of the count value of the storage means, and the third value in response to the output of the count value from the counting means. Data is read from the read address stored in the address of the count value of the fifth storage means of the storage means specified as the read source by the control information stored in the address of the count value of the storage means of Read control means for controlling
The data of the first array is converted into the data of the second array and output.

Hereinafter, the present invention will be described in detail with reference to the drawings.

[Embodiment] FIG. 2 is a block diagram showing a transmitting / receiving unit of a high speed facsimile to which the present invention is applied. Here, TDATA2 is 120-bit data to be transmitted, 2 is a transmission syndrome register for adding a 7-bit error correction code (Hamming code) to the end of each data, 4 is a multiplexer, and M1 and M2 are 127 respectively. It is a 16-bit memory. Again 10
Is a multiplexer, and 12 is a sync code adding circuit for adding a 32-bit sync code to the interleaved data.

14 is a 32-bit shift register for sequentially receiving the received data RDATA1 sent from the line side, 16 is a flag detector that monitors the contents of the shift register 14 and detects a synchronization code (flag), and 18 is a response to flag detection ROM1 to ROM3 are read-only memories for inputting the count output value of the block synchronization counter and the transmission / reception switching signal T / R sent from the microprocessor (not shown) as addresses. Is.

M3 is a 127-bit memory that stores deinterleaved data (an array returned from the interleaved data to the standard data array). 22 is a receive syndrome register for introducing the same data as memory M3 to determine the syndrome. Is a latch circuit that temporarily holds the determined syndrome, and ROM4 is a read-only memory that outputs the error bit position (address of the memory M3) using the output of the latch circuit 24 as an address. 26 introduces the same bit position (address) information of the memory M3, and when it coincides with the output of ROM4, it outputs a logical "1" signal to the exclusive OR gate 28 for inverting the content of the bit position. It is a comparator for sending.

Next, the operation of this embodiment will be described.

First, at the time of transmission, the data (120 bits) TDATA to be transmitted in response to the gate signal GATE1 sent from ROM1 to ROM3.
The 2nd clock is stopped and a 7-bit error correction code is added. This allows the receiving side to correct a 1-bit data error in the 120-bit data.

127-bit data is sent to memory M1 via multiplexer 4.
Or it is stored in either M2. These memories are memories for converting a standard data array to an interleaved array, and as shown in FIG. 3, they are sequentially stored in units of 127 bits in the vertical (X) direction of the memory. Then, at the time of reading, it is sequentially read in 16-bit units in the horizontal (Y) direction. By this, the conversion from the standard array to the interleaved array is performed. On the contrary, on the receiving side, the received data is written in the horizontal (Y) direction, and when reading it, it is written vertically.
The data is read out in the (X) direction and the standard array data is obtained again.

By adopting the interrib array in this way, it becomes possible to correct a burst error of 16 bits or less that occurs during line transmission. Since such a theory is well known, detailed description thereof will be omitted.

The above-mentioned memories M1 and M2 are M1 / M2 sent from ROM1 to ROM3.
It is switched every 2032 (16 × 127) bits according to the M2 switching signal. Thus, while one memory M1 or M2 is being written to, the other memory will drive multiplexer 10
Data is transmitted to the synchronous code adding circuit 12 via the. The multiplexers 4 and 10 described above are configured in advance so as to change their connection order also by the transmission / reception switching signal T / R.

The transmission data read via the multiplexer 10 is
As shown in FIG. 4, a 32-bit synchronization code is added to every 4064 bits and transmitted to the line side. Here, the synchronization code and gate signal GATE introduced into the synchronization code adding circuit 12
3 is a signal transmitted from ROM1 to ROM3.

Next, an error correction operation when data is received from the line side will be described.

When the received data RDATA1 is sequentially introduced into the shift register (32 bits) 14, the flag detector 16 checks whether the 16 bits match the flag (synchronization code). When the synchronization code (32 bits) is detected, the block synchronization counter 20 which is a 4096-ary counter is initialized (reset) by the synchronization circuit 18. However, 32 bits in the data may coincide with the synchronization code by chance. Therefore, it is checked whether the timing at which the carry is issued from the block synchronization counter 20 and the detection timing of the next synchronization code match.

When such timing coincidence occurs several times, it is determined that the synchronization is achieved, and all the processing timings of the received data are controlled with reference to the count value 0-4095 of the block synchronization counter 20. Therefore, the hardware for switching the memories M1 and M2 for each 2032 (16 × 127) bits and generating the address for every 16th address skip is unnecessary.

The received data that has passed through the shift register 14 is the synchronization code (32
Memory) via multiplexer 4
It is stored in either M1 or M2. That is, since the received data is interleaved, the memory M1,
By changing the order of reading from M2, restoration to the standard array is performed.

In this way, when 127-bit unit data is read by the operation opposite to that at the time of transmission, it is introduced into the memory M3 and the reception syndrome register 22 via the multiplexer 10.

Since the syndrome is determined when all 127-bit data are stored in the memory M3, the latch circuit 24 outputs the syndrome latch signal (transmitted from ROM1 to ROM3).
Retain the syndrome in response to.

The ROM4, which has the latched syndrome as an address, outputs the error bit address in the memory M3. Then, the next 127-bit data is introduced into the memory M3, and at the same time, the immediately preceding data is read from the memory M3.
At this time, since the addressing signal of the memory M3 is also supplied to the comparator 26 at the same time, the data is read from the bit address in which the error occurs, and at the same time, the signal of the logic level "1" is transmitted from the comparator 26. To be done. As a result, the contents of the erroneous bit are inverted and corrected.

When there is no error, that is, when the syndrome is zero, an unused address (zero address) is output from the ROM 4, and the comparator 4 does not output the inversion output.

Finally, the functions of ROM1 to ROM3 are listed.

Send the X and Y addresses. Here, while the X address is sequentially changing to 1,2,3 ... 2032, the Y address is changed to 1,17,33 ... 2032 in 16 jumps (and vice versa).

The switching signals of the memories M1 and M2 are sent to the multiplexers 4 and 10 in 2032 bit units.

Controls addition and deletion of block sync signal (32 bits). That is, the generation of the synchronization signal itself and GATE3
Sends a signal.

The Z address (continuously changing from 1 to 127) supplied to the error correction memory M3 is transmitted.

A control signal related to the reception syndrome register 22 is transmitted. That is, the GATE2 signal clears the reception syndrome register, and the syndrome latch signal latches the syndrome.

Supply GATE1 signal to transmission syndrome register 2 and
The timing for adding the bit error correction code is controlled.

To switch between the control timing for transmission and the control timing for reception, it is only necessary to change the level of the transmission / reception switching signal T / R.

[Effect] As described above, according to the present invention, in the communication method in which the transmission side converts the transmission data into the interleaved array and transmits the data, and the reception side receives the data in the interleaved array and converts the data into the standard array, By changing the reading order and writing order of the memory, the data array is converted, two such memories are prepared, and while writing to one memory,
The reading is performed in parallel from the other memory to perform the conversion at high speed, and the control information for designating the memory to be written and read, the read address, and the write address are counted as one. Since the count value of the means is obtained from the storage means for storing each as an address, it is not necessary to provide a plurality of counting means to obtain these addresses and control information, the circuit configuration can be simplified, and the scale of the device can be increased. There is an effect that it can be reduced.

Further, there is an effect that a change in the communication data format can be easily dealt with by changing the storage content of the storage means.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a conventional technique, FIG. 2 is a block diagram for showing an embodiment of the present invention, FIG. 3 is a diagram for explaining the concept of interleaving, and FIGS. 4 (A) to 4 (C) are It is a figure which shows the data format in a present Example. 2 …… Transmission syndrome register, 4,10 …… Multiplexer, M1, M2, M3, …… Memory, ROM1, ROM2, ROM3, ROM4… Read-only memory, 12 …… Synchronization signal addition circuit, 14 …… Shift register , 16 ... Flag detector, 18 ... Synchronous circuit, 20 ... Block synchronous counter, 22 ... Reception syndrome register, 24 ... Latch circuit, 26 ... Comparator, 28 ... Exclusive OR circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinji Tetsuya 1-2356 Take, Yokosuka City, Kanagawa Kanagawa Yokosuka Telecommunications Research Institute (72) Inventor Asao Watanabe 3-30-2 Shimomaruko, Ota-ku, Tokyo No. Canon Inc. (72) Inventor Shigetoshi Kitani 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) Reference JP-A-54-12213 (JP, A) JP-A-58- 100549 (JP, A) JP-A-57-76939 (JP, A)

Claims (2)

[Claims] 1. Input means for sequentially inputting data of a first array having a predetermined bit as a unit, counting means for counting the number of bits of data sequentially input by the input means, and input by the input means. First and second storage means for storing data to be stored, and one of the first and second storage means as a write destination of the input data, using each count value by the counting means as an address. Third storage means storing control information for designating the other and designating the other as a data read source, and the count values by the counting means as addresses are input to the first or second storage means. A fourth storage means in which a write address for writing data is stored, and data is read from the first or second storage means by using each count value by the counting means as an address. A fifth storage means for reading address is stored, in response to the output of the count value of from said counting means, said third
The storage means specified as the writing destination by the control information stored in the address of the count value in the storage means
Write control means for controlling the writing of the input data to the write address stored in the address of the count value of the storage means, and the third control means in response to the output of the count value from the counting means.
The storage means designated as the reading source by the control information stored in the address of the count value of the storage means,
Read control means for controlling the data to be read from the read address stored in the address of the count value of the storage means of the first array data, and converting the data of the first array into the data of the second array. A communication device characterized by outputting. 2. A detection means for detecting a synchronization code from the data input from the input means, and control for starting the counting operation of the counting means in response to the detection of the synchronization code by the detection means. The communication device according to claim 1, further comprising: