JPH0566778B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an error correction circuit for a coded transmission type teletext receiver, and more particularly to an error correction circuit suitable for shortening processing time for error correction.

[Background of the invention]

Coded transmission teletext is a system that transmits character and graphic information encoded from a television signal during the vertical blanking period and displays it on a television receiver. This encoded transmission type teletext has a faster transmission speed than the pattern type teletext, in which character and graphic information is transmitted after being broken down into dot patterns, and a large amount of character and graphic information can be transmitted. However, bit errors that occur in the transmission path only cause dot interference in pattern-based teletext broadcasting, but in coded transmission-based teletext broadcasting, there is a risk that the bit errors may result in different characters or missing characters, making it impossible to transmit accurate information. . Therefore, it is necessary to employ an effective error correction method with good transmission efficiency. Therefore, for coded transmission system teletext broadcasting, the Technical Report of the Television Society
As described in ICS61-3 (1983) by Yanagimachi et al., ``Study of character code broadcasting methods'',
(272190) Adopts an error correction method using a difference set majority code. This error correction method will be described below. If the unit of the teletext signal transmitted during one horizontal scanning period of the television signal is called one packet, the transmission structure of the packet signal using the (272190) difference set majority code is as shown in Fig. 1. and a data section. The synchronization section consists of a clock run-in (hereinafter abbreviated as CR) and a framing code (hereinafter abbreviated as FC). CR is a signal that synchronizes the phase of the sampling clock for extracting the teletext signal with the bit clock of the teletext signal. is a signal for detecting the beginning of the data section. In addition, the data part is divided into 190 bits and information bits according to the (272190) difference set majority vote code.
Consists of 82 test bits. A coded transmission type teletext receiver for receiving and processing a teletext signal having such a configuration will be described next. A block diagram of a conventional coded transmission teletext receiver is shown in FIG. In the figure, 1 is a tuner and video detection circuit, 2 is a character data extraction circuit that extracts a teletext signal, 3 is a CR signal detection circuit that extracts a CR signal and creates a signal that serves as a reference for the phase of the sampling clock, and 4 is a video signal detection circuit. a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from a signal, 5
6 is a clock generation circuit that generates various clock signals used in the receiver based on the burst signal in the video signal; 6 is a multiple gate generation circuit that indicates the period during which teletext signals are multiplexed during the vertical blanking period; 7
1 is a sampling clock generation circuit for sampling teletext signals, 8 is a serial-to-parallel conversion circuit for converting serial data into parallel data, 9 is an FC detection circuit, and 10 is a clock controlled by the output of the FC detection circuit. Control circuit, 11 is an address counter, 12 is an address switching circuit, 13 is a buffer memory, 14 is a microcomputer (hereinafter abbreviated as MPU), 15 is an error correction circuit, 16
17 is a random access memory, 17 is a read-only memory, 18 is an interface circuit for external devices such as a remote control, an LED display, and a printer, 19
2 is a display memory circuit; 20 is a television receiving circuit for receiving television signals; 21 is a television character switching circuit for switching between television signals and teletext signals; and 22 is a cathode ray tube. In this block diagram, first, the operation of the teletext receiver will be described. Based on the composite video signal video-detected by the tuner and video detection circuit 1, the multiplex gate generation circuit 6 uses the horizontal synchronization signal and vertical synchronization signal separated by the synchronization separation circuit 4 to detect the period during which the teletext signal is multiplexed. generates a gate signal.
By this gate signal, the character data extraction circuit 2
The teletext signal is extracted. Further, a sampling clock generating circuit 7 uses a signal serving as the reference phase of the sampling clock obtained by the CR signal detecting circuit 3 and a clock obtained by the clock generating circuit 5 to obtain a sampling clock synchronized with the bit clock of the teletext signal. Using this sampling clock, the teletext signal from the character data extraction circuit 2 is converted into parallel data by the serial-parallel conversion circuit 8. This parallel data is compared bit by bit with FC by the FC detection circuit 9, and since parallel conversion is performed by a shift register, all 8 bits of FC match when the last bit of FC is input to the shift register. , at that point the FC detection circuit 9 generates an FC detection signal. The FC detection signal is a synchronization signal indicating the beginning of the data portion, and is used as a control signal for temporarily storing only the data portion of the teletext signal into the buffer memory 13 via the address switching circuit 12 by the clock control circuit 10 and address counter 11. work.
Since the data stored in the buffer memory in this way is the transmitted data itself,
Contains transmission errors. In order to perform this error correction, conventionally, data is input/output in parallel to the error correction circuit 15 via the MPU 14, the data from the buffer memory 13 is corrected by the error correction circuit 15, and then the data is sent back to the buffer memory 13. Remember. The error-corrected data obtained in this way is processed by the MPU 14, and the character corresponding to the character code is written into the recall display memory 19 from among the character patterns stored in the read-only memory 17, and the television character switching circuit 21 and displayed on a cathode ray tube 22.
The above is an overview of the operation of the teletext receiver. The details of the operation of the error correction circuit of such a receiver will be described below. A simple configuration diagram of the error correction circuit 15 in FIG. 2 is shown in FIG. In Figure 3,
23 converts parallel data to serial data,
Or a conversion circuit for converting serial data into parallel data, 24 is a data register consisting of a 272-bit shift register, 25 is the final stage of the shift register by exclusive OR (hereinafter abbreviated as EOR) with the 82-bit shift register. Syndrome register consisting of a circuit for feeding back the output, 26
27 is an EOR circuit that performs EOR on the contents of 82 shift registers of the syndrome register 25 in a certain combination and obtains 17 outputs. The majority circuit 28 that makes a determination is based on the output of the majority circuit 27 and the output of the data register 24.
29 is an EOR circuit that takes EOR and performs error correction; 29 is an EOR circuit that takes EOR of the serial data before error correction, the output of the final stage shift register of syndrome register 25, and the output of majority circuit 27;
31 is an error detection circuit that determines whether or not there is an error based on the contents of the shift register of the syndrome register 25; 31 is an output port for transmitting data and control signals from the MPU side to the error correction circuit;
32 is an input port for passing the corrected data from the error correction circuit and the output of the error detection circuit 30 to the MPU side; 33 is a timing signal and a clock signal to each block of the error correction circuit according to a control signal from the output port 31; This is a timing generation circuit that supplies In this configuration diagram, the operation of the error correction circuit begins with the output port 31 from the MPU side.
The clear signal output from the register 25 sets all contents of the syndrome register 25 to LOW level. Next, in response to a load signal from the output port 31, the data before error correction stored in the buffer memory is input to the conversion circuit 23 in 16-bit units via the output port 31, converting the parallel data to serial data, and inputting the data into the data register 23. is serially input to the syndrome register 25. At this time, since one packet of data is 272 bits, the MPU writes one packet of data to the data register 24 and the syndrome register 25 using the load signal 17 times.
The syndrome register 25 converts serially input 272-bit data into a generating polynomial G(X)=
X ⁸² +X ⁷⁷ +X ⁷⁶ +X ⁷¹ +X ⁶⁷ +X ⁶⁶ +X ⁵⁶ +X ⁵² +
X ⁴⁸ +X ⁴⁰ +X ³⁶ +X ³⁴ +X ²⁴ +X ²² +X ¹⁸ +X ¹⁰ +X ⁴
This is a circuit that divides by +X ¹ and stores the 82 bits of the remainder, and the contents of the 82 shift registers that make up the syndrome register represent the remainder. When loading of one packet data is completed, output port 3
A load end signal of 1 causes only the syndrome register 25 to be cyclically shifted by 1 bit. This is because the code used for error correction is a shortened difference set cyclic majority code shortened by one bit. As described in Japanese Patent Application No. 58-54002 "Error Correction Decoding System" (inventor Osamu Yamada), by changing the EOR combination of the contents of the 82 shift registers of the syndrome register. It is also possible to eliminate the need to cyclically shift only the syndrome register by one bit. Next, the MPU
The data register 24 and the syndrome register 25 are shifted by 16 bits by the collect signal outputted to the output port 31 from the data register 24 and the syndrome register 25. At this time, the EOR circuit 26 performs EOR on the contents of the 82 shift registers of the syndrome register 25 in a certain combination for each 1-bit shift, and the majority decision circuit 27
The sum of the contents of the 17 outputs of the EOR circuit 26 is calculated. If the value of the equation at that time exceeds 8, the output of the majority circuit 27 becomes high level, indicating that there is an error in the first bit of the data register 24. Therefore, the leading bit of the data register can be corrected by one bit by the EOR circuit 28 which takes the EOR of the output of the data register 24 and the output of the majority circuit 27. Thereafter, by shifting the data register 24 and the syndrome register 25 by one bit and repeating the majority decision operation and EOR operation described above, the data can be error-corrected bit by bit. The data after error correction is 190 bits of information data in one packet, and the 82 check bits are unnecessary, so error correction of the information bits in one packet is performed using the collect signal from the MPU 14.
Complete by outputting 12 times. Furthermore, for one collect signal, error-corrected serial data is converted into parallel data by the conversion circuit 23, read out onto the data bus via the input port 32, and written into the buffer memory 13 again. That is, error correction of one packet of data involves reading the teletext data stored in the buffer memory 13, transferring it to the error correction circuit 15, issuing an error correction command, and then reading out the data corrected by the error correction circuit 15 again. This is achieved through processing. Specifically, since the error correction circuit 15 performs serial processing in units of 16 bits per instruction, the error correction circuit 1
The MPU 14 writes 272 bits of data for one packet in 17 times according to the load signal, and when reading it out, the 82 check bits in one packet are not needed, so only the 190 bits of information are written in 12 times. It will be read out separately. The processing time for such conventional error correction processing is
As mentioned above, MPU1 is used for input/output of teletext data.
It takes about 1.5 ms per packet because it requires 4 program processing steps. The superimposition period of the teletext signal is considered to be the 12H interval of the vertical retrace period of the television signal, and if the teletext signal is superimposed on the entire 12H interval, the time required for error correction is 1.5ms x 12
= 18 ms, exceeding the 16.5 ms period of one field of a television signal, and had the disadvantage that not only could it not perform error correction processing in one field period, but it could not convert character codes into character patterns and display them. . Furthermore, conventional error correction circuits have a disadvantage in that they are large in circuit size because they are configured to convert parallel data into serial data, perform error correction processing, and then convert serial data back into parallel data.

[Purpose of the invention]

An object of the present invention is to provide an error correction circuit that eliminates the drawbacks of the conventional error correction circuit described above and reduces the time required for error correction.

[Summary of the invention]

The feature of the present invention is that, where A is the transmission clock of packet data, the transmission time of one packet data is A, and the time from the end of packet data until the next packet data is transmitted is B, the transmission clock is at least A/B times the transmission clock. A high-speed clock generation circuit that generates a high-speed clock signal with a frequency higher than or equal to the above frequency is provided, and the data input to the error correction circuit is operated by the transmission clock until the data setting is completed.
By correcting errors in 1 packet data, 1
The point is that error correction of packet data can be performed within the transmission period of packet data.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a diagram for showing an overview of this embodiment. In FIG. 4, the numbers 1 to 22 indicate the second
34 is an error correction clock generation circuit that converts the 5.73MHz transmission clock of the teletext signal obtained by the clock generation circuit 5 in FIG. An error correction circuit 36 having a configuration different from the error correction circuit 15 in the figure is a serial-parallel conversion circuit that converts serial data into parallel data. In FIG. 4, the serial data from the character data detection circuit 2 is input to the error correction circuit 35, and the output of the error correction circuit 35 is input as serial data to the serial-parallel conversion circuit 36 at the next stage. It is different in configuration from the conventional example shown in Figure 2,
Parallel data input/output to the error correction circuit 15, which was required by the MPU 14 in the conventional example, is not required. An example of the configuration of the error correction circuit 35 shown in FIG. 4 is shown in FIG. In Figure 5, the numbers 25 to 3
0 is the same as in Figure 3, 37 is a data register consisting of a 190-bit shift register, and 38 is a data register consisting of a 190-bit shift register.
3 is a gate signal generation circuit that generates a gate signal necessary for the error correction circuit 35 according to the FC detection signal;
9 is a clock switching circuit for switching between a sampling clock and an error correction clock; 40 to 4;
The circuits up to 3 are two-input AND circuits. Further, FIG. 6 shows signal waveforms at various parts in FIG. 5. In FIG. 6, 1 is a signal transmission configuration diagram when a teletext signal is superimposed on the horizontal scanning period, and 2 to 5 are signals output from the gate signal generation circuit 38.
2 is an S clock gate that gates the clock signal to the syndrome register 25, 3 is an S data gate that gates input data to the syndrome register 25, and 4 is a data register 37.
A D clock gate 5 gates the clock signal to the data register 37, and a D data gate 5 gates the input data to the data register 37. Also, 6 is CR
7 is the FC detection signal indicating the output signal of the FC detection circuit 9; 8 is the FC
190 indicates the timing when 190 sampling clocks have been counted from the timing of detection signal 7.
A count signal, 9 is a 272 count signal indicating the timing when the sampling clock is counted 272 times from the timing of the FC detection signal 7, and 10 is a 272 count signal.
The F272 count signal indicates the timing when the error correction clock is counted 272 times from the timing of the 272 count signal 9. The embodiment will be explained below with reference to FIGS. 5 and 6. First, the transmitted teletext signal is extracted one packet at a time by the character data extraction circuit 2 shown in FIG. The extracted data is input to the serial-to-parallel converter circuit 8 and the error correction circuit 35, but is sent to the FC via the serial-to-parallel converter circuit 8.
Based on the FC detection signal obtained from the detection circuit 9, the gate signal generation circuit 38 in FIG.
1 and 43, the data after FC of the teletext signal is sent to syndrome register 25 and data register 3.
7 is input. On the other hand, since the data register 37 and the syndrome register 25 are constructed of shift registers, they are circuits that shift one bit per clock. Therefore, the gate signal generation circuit 38 in FIG. 5 generates the S clock gate 2 and the D clock gate 4, and the syndrome register 25 generates the
The S data gate 3 and the S clock gate 2 sequentially shift the 190 information bits and 82 check bits of the teletext signal using the sampling clock, and use the data for error correction during the period when the S data gate 3 is at a high level. The setup is complete. On the other hand, in the data register 37, only 190 information bits of the teletext signal are sequentially shifted by the sampling clock by the D data gate 5 and the D clock gate 4, and the information bits are processed during the period when the D data gate 5 is at a high level. After the data set is completed in this way, the clock is switched by the clock switching circuit 39 in response to the 272 count signal 9, and the syndrome register 25 and data register 3 are switched.
7 is shifted by an error correction clock having a frequency three times that of the sampling clock, and errors are corrected bit by bit sequentially. That is, during the period when the S data gate 3 and the D data gate 5 are at a low level and the period when the S clock gate 2 and the D clock gate 4 are at a high level, 272 information bits are shifted using an error correction clock that is four times as large as the sampling clock. Error correction can be performed by At this time, there is a time of 68 sampling clocks from the end of the check bit to the start of CR of the next horizontal scanning period, and 272 clocks of error correction clock with a frequency four times that of the sampling clock.
The time for bit shifting and error correction is 272/3
=68 sampling clocks, and the error correction process for one packet of data can be completed before the sixth clear signal obtained by the CR signal detection circuit 3 in the next horizontal scanning period. Therefore, by clearing the syndrome register with the clear signal 6 obtained by the CR signal detection circuit 3, initial settings for error correction of the next teletext signal can be made.

Figure 7 shows the gate signal generation circuit 3 in Figure 5.
8. The clock switching circuit 39 is shown in detail, and can be constructed with a simple circuit as shown in this figure. With the above error correction circuit, the information bits and check bits of the teletext signal are loaded into the error correction circuit using the transmission clock of the teletext signal, and after data loading is completed, error correction is performed using a high-speed clock and the next Since error correction is completed before the information bits of the teletext signal are sent during the horizontal scanning period, the processing time required for error correction of one packet data is one horizontal scanning period, or approximately 63 μs.
Therefore, the speed can be increased compared to the conventional method.

In this embodiment, the error correction clock is four times as large as the sampling clock. During a period of 92 clocks with the sampling clock
A clock frequency that can shift 272 bits is often used, specifically the 272/272 bit frequency of the sampling clock.
It is sufficient if it is 92 times or more. In addition, in this embodiment, the signal that is the reference phase of the sampling clock obtained by the CR signal detection circuit 3 is used as the clear signal for the syndrome register, but from the time when the error correction of the teletext signal for one horizontal scanning period is completed. As long as the period is until the start of the information bit of the teletext signal in the next horizontal scanning period, a CR gate signal for extracting CR or a signal obtained by delaying the horizontal synchronization signal may be used.

In addition, as shown in FIG. 8, a delayed teletext signal 3 is generated by delaying the teletext signal, and this delayed teletext signal is used as an input signal to the error correction circuit, and the input timing of the input signal to the error correction circuit is changed by delaying the input timing of the input signal of the error correction circuit. Even when the delayed FC detection signal 4, which is the FC detection signal of the teletext signal, is used, and the FC detection signal 2 of the teletext signal 1 before being delayed is used as the clear signal for the syndrome register of the error correction circuit, the error correction circuit The present invention is effective in that, when viewed from the syndrome register, the clearing operation is performed before data input, and the clearing signal can be used to initialize the error correction of the next teletext signal.

〔Effect of the invention〕

According to the present invention, since error correction of one packet data can be processed within one horizontal scanning period, high-speed error correction can be realized in about 1/23 of the conventional processing time.

[Brief explanation of drawings]

Fig. 1 is a transmission block diagram of a coded transmission teletext signal, Fig. 2 is a block diagram of a conventional coded transmission teletext receiver, Fig. 3 is a block diagram of a conventional error correction circuit, and Fig. 4 is a block diagram of a coded transmission type teletext receiver employing an embodiment of the present invention, FIG. 5 is a configuration diagram showing an embodiment of the present invention, and FIG. 6 is a waveform diagram of each part in FIG. 5. FIG. 7 is a specific circuit diagram of FIG. 5, and FIG. 8 is a waveform diagram for explaining another embodiment. 34...Error correction clock generation circuit, 38...
Gate signal generation circuit, 39...clock switching circuit.

Claims (1)

[Scope of Claims] 1. A majority decision circuit for error correcting packet data consisting of at least information data and check data using a majority decision set cyclic code;
An error correction circuit comprising a syndrome register and a data register, comprising: a write clock generating means for storing the packet data in the syndrome register and the data register; and a write clock generating means for storing the packet data in the syndrome register and the data register; a high-speed clock generation means for generating a high-speed clock faster than a transmission clock; and an input clock to the error correction circuit that is a packet data write clock from the write clock generation means or for high-speed correction from the high-speed clock generation means. 1. An error correction circuit comprising: clock selection means for selecting a high-speed clock, and configured to operate error correction in the error correction circuit using the high-speed clock. 2. In the error correction circuit according to claim 1, the write clock generating means outputs a write clock having a transmission clock frequency of the packet data, and the high speed clock generating means outputs a write clock having a transmission clock frequency of the packet data, and the high speed clock generating means outputs a write clock having a transmission clock frequency of the packet data. , where B is the time from the end of the packet data until the next packet data is transmitted, generate a high-speed clock signal with a frequency at least A/B times the write clock, and complete error correction of the packet data. an initialization signal generation circuit that generates an initialization signal for initializing the syndrome register of the error correction circuit during the period up to the start position of the next packet data after the initialization, and at least information data and inspection data of the packet data are excluded. clock switching control means for controlling the clock selection means so as to supply a high-speed clock for high-speed correction outputted from the high-speed clock generation means to the error correction circuit during the initialization signal generation circuit; initializing the syndrome register of the error correction circuit by the initialization signal, and by the clock switching control means, the clock selection means selects the packet data write clock from the write clock generation means;
The information data and test data of the packet data are supplied to the syndrome register and the data register of the error correction circuit in response to the write clock output from the write clock generating means, and the information data and test data of the packet data are supplied to the syndrome register and the data register. After the data is stored, the clock switching control means causes the clock selection means to select a high-speed clock for high-speed correction from the high-speed clock generation means, and uses the high-speed clock output from the high-speed clock generation means to An error correction circuit characterized in that the error correction circuit is configured to perform error correction of one packet data within a transmission cycle of the packet data by operating the error correction circuit. 3. In the error correction circuit as set forth in claim 2, the clock switching control means performs the following steps: The clock selection means is controlled to select the packet data write clock from the write clock generation means, and furthermore, the clock selection means is controlled to select the packet data write clock from the high speed clock generation means at the end of writing the packet data to the syndrome register and the data register. An error correction circuit characterized in that it controls the selection of a high-speed clock for high-speed correction.