JPH0771269B2 - Teletext receiver circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a teletext receiving circuit, and more particularly, to time division in a vertical blanking period of a video signal received from a multiplexed television signal of a coded transmission system. The present invention relates to a teletext reception circuit configured to display teletext contents on a display unit by extracting multiplexed teletext signals and performing serial / parallel conversion processing, error correction processing, decoding processing, display processing, and the like. .

<Technical Background and Prior Art> In a teletext system using a coded transmission method that has recently been put into practical use, a teletext signal uses a vertical blanking period of a television video signal, In the 1-horizontal scanning period, the data packet format has a unit length of data that is superimposed, and is time-division multiplexed in the form of digital data. That is, the signal relating to one teletext program is superposed almost continuously in the vertical blanking period, one packet at a time in 1-vertical blanking period. Therefore, it is necessary to capture all the teletext signals superimposed in the 1-vertical blanking period before the teletext signals superimposed in the next vertical blanking period arrive.

On the other hand, as shown in FIG. 5, a teletext signal can be superimposed on up to 12 programs (12 packets of 10H to 21H) in the 1-vertical blanking period.

By the way, when a data memory capable of storing data of a plurality of teletext programs is not provided like the conventional teletext receiving circuit, only the program selected by the receiver needs to be fetched. There was no problem because there was no problem in time because there was no problem as long as one data packet could be fetched during the blanking period, but a data memory capable of storing the data of a plurality of teletext programs was provided, and the data memory When storing and accumulating the latest data in, especially when a large number of data packets are superposed in the 1-vertical blanking period, the processing of fetching the large number of data packets is performed in the next vertical blanking period. Must be completed before the arrival of the data packet superimposed on
CPU acquisition processing time becomes a big problem.

That is, the data is transferred to one buffer RAM in the order of transmission.
In the teletext receiving circuit of the conventional configuration by the simple means of sequentially using the 1-V, as shown in FIG.
During the period, the data in the buffer RAM after error correction processing is performed while performing operations such as primary acquisition processing of superimposition data, data transfer to buffer RAM after error correction processing, error checking, confirmation of reservation status and selected programs. You have to do the CPU processing that is stored in the data memory. Moreover, the error correction unit has a higher correction capability if the threshold value of the correction bit is increased to perform the error correction process, but the error correction process may be performed a plurality of times. Will increase. Moreover, if the number of superposed H of data packets is large, the error correction processing time is correspondingly increased.
Therefore, the worse the reception state is, and the larger the number of overlapping H of data packets is, the longer the error correction processing time is, and the shorter the time t at which the CPU can take in the processing is. In addition, the fetch processing time of the CPU becomes longer as the number of superposed H of data packets increases, so that there is a limit to the number of superposed H of data packets that can be simultaneously taken.

<Objects of the Invention> The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to store data of a plurality of teletext programs so that a plurality of teletext programs can be stored and accumulated. We will provide a large-capacity data memory that can be used to store the latest data in the data memory, and at the same time, provide a teletext receiving circuit that does not pose a problem with CPU processing time as in the past. To do.

<Structure of the Invention> In order to achieve such an object, the coded transmission type teletext receiving circuit according to the present invention has a basic configuration as described at the beginning, and stores data of a plurality of teletext programs. Large-capacity data memory that can be
An error correction unit that performs an error correction process on the teletext signal extracted from the video signal, and a plurality of error correction data that is output from the error correction unit are stored, and a plurality of data that outputs the data to the data memory are stored. By providing a buffer memory and a CPU for storing the error-corrected data output from the error correction unit in the buffer memory by time-division switching according to the data acquisition processing speed, C
It has the feature that it can increase the PU processable time.

<Example> Hereinafter, a specific example of the present invention will be described with reference to the drawings (Figs. 1 to 4).

FIG. 1 is a schematic block circuit configuration diagram of a main part of a teletext receiving circuit according to the present embodiment. In the figure, 1 is an antenna, 2 is a teletext signal sampling unit, 3 is serial-parallel conversion and error correction unit, 4 is a buffer memory having a plurality of buffer RAMs, 5 is a CPU, 6 is a large-capacity data memory for storing data of a plurality of teletext programs, 7 is a decoding and display processing unit, 8 is a CRT or Shows a display such as a liquid crystal display, receives the multiplexed television signal sent from the broadcasting station by the antenna 1, and superimposes the characters from the multiplexed television signal in the vertical blanking period of the video signal. The broadcast signal is extracted by the teletext signal extracting unit 2, and the extracted data is subjected to error correction processing in packet units by the serial-parallel conversion and error correction unit 3 and then the data is buffered. The data is transferred to the memory 4, and the CPU 5 sequentially processes the data in the buffer memory 4 after checking the error. In the case of a system in which program reservation is possible, the data is stored in the data memory 6 in program units. Is stored / accumulated, and the accumulated data is transferred to the decoding / display processing unit 7 in accordance with the program selection of the receiver by key input from an operation panel (not shown),
Decode and display processing to convert to pixel data,
It is configured to display on the display 8.

As described above, in the coded transmission type teletext receiving circuit according to the present invention, the large-capacity data memory 6 is provided so that a plurality of teletext programs can be stored and accumulated, and the plurality of buffer RAMs are provided. The buffer memory 4 is provided to improve the workable time of the CPU 5, but for the sake of simplicity, the buffer memory 4 is used.
As regards the case where two buffer RAMs are provided, the operation will be described with reference to the detailed block circuit configuration diagram of the main part shown in FIG. 2, the buffer RAM switching timing chart of FIG. 3 and the operation explanatory diagram of FIG. explain. In addition,
FIG. 2 is conceptual, and positive logic and negative logic are not taken into consideration.

That is, as shown in FIGS. 2 and 3, the serial-parallel conversion and error correction unit 3 receives the V-synchronization signal, the H-synchronization signal, serial data, the operation clock, etc., and performs serial-parallel conversion processing and error correction. After performing the correction process, the error-corrected data and the specified address on the buffer RAMs 4I and 4II, which will be described later, are output, and the error correction process of all the data superimposed in the 1-vertical blanking period. Error-completion signal indicating that the process has finished and the buffer RAM4I, 4II
Outputs a bus control signal for switching the access destination of the serial-parallel conversion and error correction unit 3 and the CPU 5. The two buffer RAMs 4I and 4II have an address bus and a data bus from the CPU 5 and a serial / parallel conversion and error correction unit 3
The multiplexers 4i and 4ii for switching the address bus and the data bus from the above are connected one by one respectively.

The CPU 5 signals a CPU fetching process end signal indicating that the fetching process of the data superimposed in the previous vertical blanking period has ended. By outputting this CPU capture processing end signal, it indicates that the CPU 5 is ready to process the data superimposed in the next vertical blanking period. On the other hand, the error correction processing end signal is output when the error correction processing of the data superimposed in the vertical blanking period to be captured is completed. Therefore, in order to take in the data, the process of taking in the data superimposed in the previous vertical blanking period is completed, and the error correction process of the current data is also completed. The start point is the acquisition processing start signal, which is the later signal of the error correction processing end signal, and the CP
U5 will take in the data that was superimposed during the current vertical blanking period. This operation is a delay signal sampling circuit
14 and the output is input to the flip-flop 10 as a fetch processing start signal, and the two buffer RAMs 4
It serves as a reference signal for switching between I, 4II and multiplexers 4i, 4ii.

The CPU 5 accepts the fetching process start signal and starts the fetching process.

The address bus and data bus from the CPU 5 are connected to the respective buffer RAMs 4I and 4II via the two multiplexers 4i and 4ii, and the chip select terminals of the respective buffer RAMs 4I and 4II via the address decoder 9. Are in control.

The V-synchronization signal, the error correction processing end signal, the CPU acquisition processing end signal and the acquisition processing start signal are as shown in (a), (b), (c) and (d) of FIG. 3, respectively. It is a waveform signal. The fetching process start signal is a signal for starting the fetching process with respect to the CPU 5. The select signal of the multiplexer 4i which changes at the fall of the fetching process start signal via the flip-flop 10 (FIG. 3). (E) in (1) is generated, and the select signal of the multiplexer 4i is inverted by the inverting element 11 to generate the select signal of the multiplexer 4ii {(f) in FIG. On the other hand, the period for receiving the signal from the serial / parallel conversion and error correction unit 3 and the period for receiving the signal from the CPU 5 are alternately shifted in time.

Therefore, the two buffer RAMs 4I and 4II mutually take the timing of the access from the serial / parallel conversion and error correction unit 3 and the access from the CPU 5 for one cycle of the access processing start signal with reference to the input processing start signal. The operation is performed with a shift, and the operation is performed with two cycles of the capture processing start signal as a unit cycle.

On the other hand, the serial-parallel conversion and error correction unit 3 has two buffers.
Bus control signal {3rd for RAM4I, 4II respectively
(T) in the figure is output, but the bus control signal and the select signals of both the multiplexers,
Then, the control signals relating to the read / write of the buffer RAM, which are sent from the serial / parallel conversion and error correction unit 3 to both the buffer RAMs 4I and 4II, are alternately switched by the signal via the AND elements 12 and 13. Further, in response to the select signal of each multiplexer (4i, 4ii) made by the flip-flop 10, the buffer RAM4I, which is output from the CPU 5,
The control signals for reading and writing the buffer RAM sent to 4II are alternately switched.

As described above, the host for accessing each of the buffer RAMs 4I and 4II is the control signal of the buffer RAM4I shown in FIG. 3 (h), and the buffer RAM4II shown in FIG. 3 (ri).
It changes like the control signal of, and increases the time that can be spent on the CPU5 capture processing.

That is, as shown in FIG. 4, CP in the case of the present invention
The time T that can be spent in the U5 capture process is from the vertical blanking period during which the data currently being captured is superimposed to the data superimposition start position after the 2-vertical blanking period. In the conventional case shown in FIG.
This significantly increases the time t that can be spent for CPU acquisition processing.

Depending on the method of capturing teletext, it may take a relatively long time to capture a certain data packet (eg, page header control unit, program index data header, etc.).

According to the present invention, it is possible to deal with the case where the data packets which take up the processing time are overlapped in a certain vertical blanking period, and in the long run, the data in which 1-vertical blanking periods are superimposed is averaged. It suffices that the time for the CPU 5 to take in the processing be within the 1-V synchronization period.

Although only the timing of the acquisition processing operation of the CPU 5 is entered in FIG. 3, the CPU 5 executes other processing (for example, decoding of the selected program until the acquisition processing start signal is input and the next acquisition processing start signal is input. Processing, display processing) may be performed.

Further, in order to speed up the processing, a plurality of CPUs may be provided and the processing functions may be divided, one of which may be a CPU dedicated to the import processing.

When the power is turned on or when the data starts to be superimposed,
When the CPU is not performing the fetch operation, the delay signal sampling circuit must be reset by the V-sync signal.

<Effects of the Invention> As is apparent from the above detailed description, according to the teletext receiving circuit of the coded transmission system according to the present invention, large-capacity data capable of storing data of a plurality of teletext programs. A memory, an error correction unit that performs error correction processing on a teletext signal extracted from a video signal, and error-corrected data output from the error correction unit are stored, and the data is output to the data memory. A plurality of buffer memories and a CPU for storing the error-corrected data output from the error correction unit in the buffer memory by time-division switching according to the data acquisition processing speed are provided. It is possible to store and store multiple teletext programs as well as to store the latest data in the data memory because the time that can be taken in is increased. Of course, in the case where a large number of data packets are superposed within the 1-vertical blanking period,
The data output from the error correction unit is stored in a plurality of buffer memories at the data acquisition processing speed of the CPU rather than by a simple means of sequentially acquiring the data in one buffer memory in the order in which they are transmitted as in the past. Accordingly, it becomes possible to simultaneously capture and process a plurality of data packets within the extended CPU available processing time by means of switching and storing in time division.
Even if a large number of data packets are superposed and transmitted within the 1-vertical blanking period, the CP
An excellent effect that all the data packets can be processed with a sufficient margin without causing a problem in the U acquisition processing time is exhibited.

[Brief description of drawings]

1 to 4 show a concrete embodiment of a teletext receiving circuit according to the present invention. FIG. 1 is a schematic block circuit configuration diagram of a main part, and FIG. 2 is a detailed block circuit of a main part thereof. FIG. 3 is a configuration diagram, FIG. 3 is a timing chart of signals of respective parts, and FIG. 4 is an explanatory diagram of operation. Also, FIGS. 5 and 6 are for explaining the technical background of the present invention and the problems of the prior art,
FIG. 5 is a diagram for explaining the state of the multiplexed television video signal, and FIG. 6 is a diagram for explaining the operation of the conventional teletext receiving circuit. 2 ... teletext signal sampling unit, 3 ... serial-parallel conversion and error correction unit, 4 (4I, 4II) ... buffer memory (RAM),
5 ... CPU, 6 ... Large-capacity data memory, 7 ... Decoding and display processing section.

Claims (1)

[Claims] 1. A character-broadcast signal time-division multiplexed during a vertical blanking period of the video signal is extracted from a received multiplexed television signal of a coded transmission system, and serial-parallel conversion processing, error correction processing, By performing decoding processing, display processing, etc., it is possible to store the data of multiple teletext programs in the teletext receiving circuit of the coded transmission system configured to display the teletext contents on the display unit. A large-capacity data memory, an error correction unit that performs error correction processing on a teletext signal extracted from a video signal, and error-corrected data output from the error correction unit are stored, and the data is stored in the data memory. A plurality of buffer memories for outputting to the buffer memory, and the error-corrected data output from the error correction unit to the buffer memory, depending on the data acquisition processing speed. A teletext receiving circuit, characterized in that it is provided with a CPU for switching and storing by division.